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-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_dds_compiler_0_1;
ARCHITECTURE design_1_dds_compiler_0_1_arch OF design_1_dds_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 29,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "10110000001010010,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 32,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END design_1_dds_compiler_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_dds_compiler_0_1;
ARCHITECTURE design_1_dds_compiler_0_1_arch OF design_1_dds_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 29,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "10110000001010010,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 32,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END design_1_dds_compiler_0_1_arch;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : entity fifo_dsn.1clk_fifo
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : ENTITY fifo_dsn.1clk_fifo
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Wed Mar 01 10:29:47 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished_0 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
href_0 : in STD_LOGIC;
href_1 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
resend : in STD_LOGIC;
scl_0 : out STD_LOGIC;
scl_1 : out STD_LOGIC;
sda_0 : inout STD_LOGIC;
sda_1 : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_out_en : out STD_LOGIC;
resend : in STD_LOGIC;
config_finished_0 : out STD_LOGIC;
scl_0 : out STD_LOGIC;
sda_0 : inout STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
scl_1 : out STD_LOGIC;
sda_1 : inout STD_LOGIC;
href_0 : in STD_LOGIC;
href_1 : in STD_LOGIC;
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
config_finished_0 => config_finished_0,
config_finished_1 => config_finished_1,
data_0(7 downto 0) => data_0(7 downto 0),
data_1(7 downto 0) => data_1(7 downto 0),
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en,
href_0 => href_0,
href_1 => href_1,
pclk_0 => pclk_0,
pclk_1 => pclk_1,
resend => resend,
scl_0 => scl_0,
scl_1 => scl_1,
sda_0 => sda_0,
sda_1 => sda_1,
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync_0 => vsync_0,
vsync_1 => vsync_1,
xclk_0 => xclk_0,
xclk_1 => xclk_1
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_64x512_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1677.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01677ent IS
END c09s01b00x00p08n01i01677ent;
ARCHITECTURE c09s01b00x00p08n01i01677arch OF c09s01b00x00p08n01i01677ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL v_slice : bit_vector_8 := B"1010_1100";
BEGIN
labeled : block
port ( v : OUT bit_vector_4 := "1010");
port map ( v_slice ( 0 to 3 ));
begin
v <= B"0101" after 10 ns; -- only driver created ..
end block;
TESTING: PROCESS
BEGIN
assert (v_slice = B"1010_1100")
report "Condition error: value of signal V_SLICE incorrect"
severity failure;
wait for 10 ns;
assert NOT(v_slice = B"0101_1100")
report "***PASSED TEST: c09s01b00x00p08n01i01677"
severity NOTE;
assert (v_slice = B"0101_1100")
report "***FAILED TEST: c09s01b00x00p08n01i01677 - The value of signal V_SLICE was not properly updated."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p08n01i01677arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1677.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01677ent IS
END c09s01b00x00p08n01i01677ent;
ARCHITECTURE c09s01b00x00p08n01i01677arch OF c09s01b00x00p08n01i01677ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL v_slice : bit_vector_8 := B"1010_1100";
BEGIN
labeled : block
port ( v : OUT bit_vector_4 := "1010");
port map ( v_slice ( 0 to 3 ));
begin
v <= B"0101" after 10 ns; -- only driver created ..
end block;
TESTING: PROCESS
BEGIN
assert (v_slice = B"1010_1100")
report "Condition error: value of signal V_SLICE incorrect"
severity failure;
wait for 10 ns;
assert NOT(v_slice = B"0101_1100")
report "***PASSED TEST: c09s01b00x00p08n01i01677"
severity NOTE;
assert (v_slice = B"0101_1100")
report "***FAILED TEST: c09s01b00x00p08n01i01677 - The value of signal V_SLICE was not properly updated."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p08n01i01677arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1677.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01677ent IS
END c09s01b00x00p08n01i01677ent;
ARCHITECTURE c09s01b00x00p08n01i01677arch OF c09s01b00x00p08n01i01677ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL v_slice : bit_vector_8 := B"1010_1100";
BEGIN
labeled : block
port ( v : OUT bit_vector_4 := "1010");
port map ( v_slice ( 0 to 3 ));
begin
v <= B"0101" after 10 ns; -- only driver created ..
end block;
TESTING: PROCESS
BEGIN
assert (v_slice = B"1010_1100")
report "Condition error: value of signal V_SLICE incorrect"
severity failure;
wait for 10 ns;
assert NOT(v_slice = B"0101_1100")
report "***PASSED TEST: c09s01b00x00p08n01i01677"
severity NOTE;
assert (v_slice = B"0101_1100")
report "***FAILED TEST: c09s01b00x00p08n01i01677 - The value of signal V_SLICE was not properly updated."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p08n01i01677arch;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_boot is
generic (
-- width of set selection
width_set_sel_g : integer := 4;
-- width of bit counter: minimum 6, maximum 12
width_bit_cnt_g : integer := 6;
-- width of image counter: minimum 0, maximum n
width_img_cnt_g : integer := 2;
-- number of bits required to address one image
num_bits_per_img_g : integer := 18;
-- SD specific initialization
sd_init_g : integer := 0;
-- clock divider to reach 400 kHz for MMC compatibility
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
-- active level of reset_i
reset_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
-- Card Interface ---------------------------------------------------------
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
-- FPGA Configuration Interface -------------------------------------------
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end spi_boot;
library ieee;
use ieee.numeric_std.all;
use work.spi_boot_pack.all;
architecture rtl of spi_boot is
component spi_counter
generic (
cnt_width_g : integer := 4;
cnt_max_g : integer := 15
);
port (
clk_i : in std_logic;
reset_i : in boolean;
cnt_en_i : in boolean;
cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
cnt_ovfl_o : out boolean
);
end component;
-----------------------------------------------------------------------------
-- States of the controller FSM
--
type ctrl_states_t is (POWER_UP1, POWER_UP2,
CMD0,
CMD1,
CMD55, ACMD41,
CMD16,
WAIT_START,
WAIT_INIT_LOW, WAIT_INIT_HIGH,
CMD18, CMD18_DATA,
CMD12,
INC_IMG_CNT);
--
signal ctrl_fsm_q,
ctrl_fsm_s : ctrl_states_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- States of the command FSM
--
type cmd_states_t is (CMD, START, R1, PAUSE);
--
signal cmd_fsm_q,
cmd_fsm_s : cmd_states_t;
--
-----------------------------------------------------------------------------
subtype op_r is integer range 5 downto 0;
type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0);
signal res_bc_s : res_bc_t;
signal upper_bitcnt_zero_s : boolean;
signal cfg_dat_q : std_logic;
signal spi_clk_q : std_logic;
signal spi_clk_rising_q : boolean;
signal spi_clk_falling_q : boolean;
signal spi_dat_q,
spi_dat_s : std_logic;
signal spi_cs_n_q,
spi_cs_n_s : std_logic;
signal cfg_clk_q : std_logic;
signal start_q : std_logic;
signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0);
signal cnt_en_img_s : boolean;
signal mmc_cnt_ovfl_s : boolean;
signal mmc_compat_s : boolean;
signal cmd_finished_s : boolean;
signal r1_result_q : std_logic;
signal done_q,
send_cmd12_q : boolean;
signal en_outs_s,
en_outs_q : boolean;
signal reset_s : boolean;
signal true_s : boolean;
begin
true_s <= true;
reset_s <= true
when (reset_level_g = 1 and reset_i = '1') or
(reset_level_g = 0 and reset_i = '0') else
false;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements several sequential elements.
--
seq: process (clk_i, reset_s)
variable bit_cnt_v : unsigned(1 downto 0);
begin
if reset_s then
-- reset bit counter to 63 for power up
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "111111";
spi_dat_q <= '1';
spi_cs_n_q <= '1';
cfg_dat_q <= '1';
start_q <= '0';
done_q <= false;
send_cmd12_q <= false;
ctrl_fsm_q <= POWER_UP1;
cmd_fsm_q <= CMD;
r1_result_q <= '0';
en_outs_q <= false;
elsif clk_i'event and clk_i = '1' then
-- bit counter control
if spi_clk_rising_q then
case res_bc_s is
when NONE =>
bit_cnt_q <= bit_cnt_q - 1;
when RES_MAX =>
bit_cnt_q <= (others => '1');
when RES_47 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "101111";
when RES_15 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "001111";
when RES_7 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "000111";
when others =>
bit_cnt_q <= (others => '0');
end case;
end if;
-- Card data output register
-- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
-- As soon as this mode is left, the register must start latching.
-- There is no explicit relation to spi_clk_q anymore in normal mode.
-- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
-- value after the rising edge of spi_clk_q.
-- -> spi_dat_q changes upon falling edge of spi_clk_q
if spi_clk_falling_q or not mmc_compat_s then
spi_dat_q <= spi_dat_s;
end if;
-- config data output register
-- a new value is loaded when config clock is high,
-- i.e. input data is sampled with rising spi_clk
-- while output value changes on falling edge of cfg_clk
if cfg_clk_q = '1' and spi_clk_rising_q then
cfg_dat_q <= spi_data_in_i;
end if;
-- Controller FSM state
ctrl_fsm_q <= ctrl_fsm_s;
-- Command FSM state
cmd_fsm_q <= cmd_fsm_s;
-- CS signal for SPI card
if spi_clk_q = '1' then
spi_cs_n_q <= spi_cs_n_s;
end if;
-- Extract flags from R1 response
if cmd_fsm_q = R1 then
bit_cnt_v := bit_cnt_q(1 downto 0);
case bit_cnt_v(1 downto 0) is
when "10" =>
-- always save "Illegal Command" flag
r1_result_q <= to_X01(spi_data_in_i);
when "00" =>
-- overwrite with "Idle State" flag when not in CMD55
if ctrl_fsm_q /= CMD55 then
r1_result_q <= to_X01(spi_data_in_i);
end if;
when others =>
null;
end case;
end if;
-- Start trigger register for rising edge detection
-- the reset value is '0' thus a rising edge will always be detected
-- after reset even though start_i is tied to '1'
if start_i = '0' then
start_q <= '0';
elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
start_q <= start_i;
end if;
-- Marker for cfg_done and dat_done
if ctrl_fsm_q = CMD18_DATA then
if cfg_done_i = '1' and dat_done_i = '1' then
done_q <= true;
end if;
if done_q and
(not upper_bitcnt_zero_s or cmd_fsm_q = START) then
-- activate sending of CMD12 when it is safe:
-- * upper bits of bit counter are not zero
-- -> transmission of CMD12 is not running
-- * cmd FSM is in START state
-- -> also no transmission running
send_cmd12_q <= true;
end if;
elsif ctrl_fsm_q = WAIT_START then
-- reset done_q when WAIT_START has been reached
-- this is necessary to let the stop transmission process come to
-- an end without interruption or generation of unwanted cfg_clk_q
done_q <= false;
send_cmd12_q <= false;
end if;
-- output enable
if spi_clk_rising_q then
en_outs_q <= en_outs_s;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process upper_bits
--
-- Purpose:
-- Detects that the upper bits of the bit counter are zero.
-- Upper bits = n downto 6, i.e. the optional part that is not required for
-- commands but for extension of data blocks.
--
upper_bits: process (bit_cnt_q)
variable zero_v : boolean;
begin
zero_v := true;
for i in bit_cnt_q'high downto 6 loop
if bit_cnt_q(i) = '1' then
zero_v := false;
end if;
end loop;
upper_bitcnt_zero_s <= zero_v;
end process upper_bits;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process clk_gen
--
-- Purpose:
-- Generates clocks for card and FPGA configuration.
-- The card clock is free running with a divide by two of clk_i.
-- The clock for FPGA config has an enable and is stopped on high level.
-- There is a phase shift of half a period between spi_clk and cfg_clk.
--
clk_gen: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_q <= '0';
cfg_clk_q <= '1';
elsif clk_i'event and clk_i = '1' then
-- spi_clk_q rises according to the flag
-- it falls with overflow indication
-- the resulting duty cycle is not exactly 50:50,
-- high time is a bit longer
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_q rises when flagged by spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
elsif mmc_cnt_ovfl_s then
-- upon counter overflow spi_clk_q falls in case it does not rise
spi_clk_q <= '0';
end if;
else
-- normal mode
-- spi_clk_q follows spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
else
spi_clk_q <= '0';
end if;
end if;
-- clock for FPGA config must be enabled and follows spi_clk
if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
not done_q then
cfg_clk_q <= spi_clk_q;
else
cfg_clk_q <= '1';
end if;
end if;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Indication flags for rising and falling spi_clk_q.
-- Essential for MMC clock compatibility mode.
-----------------------------------------------------------------------------
mmc_comap: if mmc_compat_clk_div_g > 0 generate
mmc_compat_sig: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
elsif clk_i'event and clk_i = '1' then
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
-- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
if mmc_cnt_ovfl_s then
spi_clk_rising_q <= spi_clk_q = '0';
spi_clk_falling_q <= spi_clk_q = '1';
else
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
end if;
else
-- normal mode
spi_clk_rising_q <= not spi_clk_rising_q;
spi_clk_falling_q <= true;
end if;
end if;
end process mmc_compat_sig;
end generate;
no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
-- SPI clock rising whenever spi_clk_q is '0'
spi_clk_rising_q <= spi_clk_q = '0';
-- SPI clock falling whenever spi_clk_q is '1'
spi_clk_falling_q <= spi_clk_q = '1';
end generate;
-----------------------------------------------------------------------------
-- Process ctrl_fsm
--
-- Purpose:
-- Implements the controller FSM.
--
ctrl_fsm: process (ctrl_fsm_q,
cmd_finished_s, r1_result_q,
start_i, start_q, mode_i,
cfg_init_n_i)
variable mmc_compat_v : boolean;
begin
-- default assignments
ctrl_fsm_s <= POWER_UP1;
config_n_o <= '1';
cnt_en_img_s <= false;
spi_cs_n_s <= '0';
mmc_compat_v := false;
en_outs_s <= true;
case ctrl_fsm_q is
-- Let card finish power up, step 1 -------------------------------------
when POWER_UP1 =>
mmc_compat_v := true;
spi_cs_n_s <= '1';
if cmd_finished_s then
ctrl_fsm_s <= POWER_UP2;
else
ctrl_fsm_s <= POWER_UP1;
end if;
-- Let card finish power up, step 2 -------------------------------------
when POWER_UP2 =>
mmc_compat_v := true;
if cmd_finished_s then
ctrl_fsm_s <= CMD0;
else
spi_cs_n_s <= '1';
ctrl_fsm_s <= POWER_UP2;
end if;
-- Issue CMD0: GO_IDLE_STATE --------------------------------------------
when CMD0 =>
mmc_compat_v := true;
if cmd_finished_s then
if sd_init_g = 1 then
ctrl_fsm_s <= CMD55;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD0;
end if;
-- Issue CMD55: APP_CMD -------------------------------------------------
when CMD55 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_result_q = '0' then
-- command accepted, it's an SD card
ctrl_fsm_s <= ACMD41;
else
-- command rejected, it's an MMC card
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD55;
end if;
end if;
-- Issue ACMD41: SEND_OP_COND -------------------------------------------
when ACMD41 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_result_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD55;
end if;
else
ctrl_fsm_s <= ACMD41;
end if;
end if;
-- Issue CMD1: SEND_OP_COND ---------------------------------------------
when CMD1 =>
mmc_compat_v := true;
if cmd_finished_s then
if r1_result_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD1;
end if;
-- Issue CMD16: SET_BLOCKLEN --------------------------------------------
when CMD16 =>
if cmd_finished_s then
ctrl_fsm_s <= WAIT_START;
else
ctrl_fsm_s <= CMD16;
end if;
-- Wait for configuration start request ---------------------------------
when WAIT_START =>
spi_cs_n_s <= '1';
-- detect rising edge of start_i
if start_i = '1' and start_q = '0' then
-- decide which mode is requested
if cmd_finished_s then
if mode_i = '0' then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
-- Wait for INIT to become low ------------------------------------------
when WAIT_INIT_LOW =>
spi_cs_n_s <= '1';
-- activate FPGA configuration
config_n_o <= '0';
if cfg_init_n_i = '0' then
ctrl_fsm_s <= WAIT_INIT_HIGH;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
-- Wait for INIT to become high -----------------------------------------
when WAIT_INIT_HIGH =>
spi_cs_n_s <= '1';
if cfg_init_n_i = '1' and cmd_finished_s then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_HIGH;
end if;
-- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
when CMD18 =>
if cmd_finished_s then
ctrl_fsm_s <= CMD18_DATA;
else
ctrl_fsm_s <= CMD18;
end if;
--
-- receive a data block
when CMD18_DATA =>
if cmd_finished_s then
ctrl_fsm_s <= CMD12;
else
ctrl_fsm_s <= CMD18_DATA;
end if;
-- Issued CMD12: STOP_TRANSMISSION --------------------------------------
when CMD12 =>
if cmd_finished_s then
ctrl_fsm_s <= INC_IMG_CNT;
else
ctrl_fsm_s <= CMD12;
end if;
-- Increment Image Counter ----------------------------------------------
when INC_IMG_CNT =>
spi_cs_n_s <= '1';
ctrl_fsm_s <= WAIT_START;
cnt_en_img_s <= true;
when others =>
null;
end case;
-- mmc_compat_s is suppressed if MMC clock compatibility is not required
if mmc_compat_clk_div_g > 0 then
mmc_compat_s <= mmc_compat_v;
else
mmc_compat_s <= false;
end if;
end process ctrl_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process cmd_fsm
--
-- Purpose:
-- Implements the command FSM.
--
cmd_fsm: process (spi_clk_rising_q,
spi_data_in_i,
bit_cnt_q,
ctrl_fsm_q,
cmd_fsm_q,
send_cmd12_q)
variable cnt_zero_v : boolean;
variable spi_data_low_v : boolean;
variable no_startbit_v : boolean;
begin
-- default assignments
cmd_finished_s <= false;
cmd_fsm_s <= CMD;
res_bc_s <= NONE;
cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0;
spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
-- these are no real commands thus there will be no startbit
case ctrl_fsm_q is
when POWER_UP1 | POWER_UP2 |
WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
no_startbit_v := true;
when others =>
no_startbit_v := false;
end case;
case cmd_fsm_q is
-- Send the command -----------------------------------------------------
when CMD =>
if cnt_zero_v then
if ctrl_fsm_q /= CMD18_DATA then
-- normal commands including CMD12 require startbit of R1 response
cmd_fsm_s <= START;
else
if not send_cmd12_q then
-- CMD18_DATA needs to read CRC
cmd_fsm_s <= R1;
res_bc_s <= RES_15;
else
-- CMD18_DATA finished, scan for startbit of response
cmd_finished_s <= true;
cmd_fsm_s <= START;
end if;
end if;
else
cmd_fsm_s <= CMD;
end if;
-- Wait for startbit of response ----------------------------------------
when START =>
-- startbit detection or skip of this check
if no_startbit_v and spi_clk_rising_q then
cmd_fsm_s <= R1;
res_bc_s <= RES_7;
elsif spi_data_low_v then
if ctrl_fsm_q /= CMD18_DATA then
cmd_fsm_s <= R1;
else
-- CMD18_DATA startbit detected, read payload
cmd_fsm_s <= CMD;
res_bc_s <= RES_MAX;
end if;
else
cmd_fsm_s <= START;
res_bc_s <= RES_7;
end if;
-- Read R1 response -----------------------------------------------------
when R1 =>
if cnt_zero_v then
res_bc_s <= RES_7;
if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
cmd_fsm_s <= PAUSE;
else
-- CMD18 needs another startbit detection for the data token.
-- CMD18_DATA needs a startbit after having received the CRC, either
-- * next data token
-- * R1 response of CMD12
cmd_fsm_s <= START;
if ctrl_fsm_q = CMD18 then
-- CMD18 response received -> advance to CMD18_DATA
cmd_finished_s <= true;
end if;
end if;
else
cmd_fsm_s <= R1;
end if;
-- PAUSE state -> required for Nrc, card response to host command -------
when PAUSE =>
if cnt_zero_v then
cmd_fsm_s <= CMD;
res_bc_s <= RES_47;
cmd_finished_s <= true;
else
cmd_fsm_s <= PAUSE;
end if;
when others =>
null;
end case;
end process cmd_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process transmit
--
-- Purpose:
-- Generates the serial data output values based on the current FSM state
--
-- The local variable cmd_v is 64 bits wide in contrast to an SPI command
-- with 48 bits. There are two reasons for this:
-- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
-- counter will start from 3F on its lowest 6 bits. Therefore, it is
-- necessary to provide all 64 positions in cmd_v.
-- * Reduces logic.
--
transmit: process (ctrl_fsm_q,
cmd_fsm_q,
bit_cnt_q,
img_cnt_s,
send_cmd12_q,
set_sel_i,
upper_bitcnt_zero_s)
subtype cmd_r is natural range 47 downto 0;
subtype cmd_t is std_logic_vector(cmd_r);
subtype ext_cmd_t is std_logic_vector(63 downto 0);
-- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101";
constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1";
constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1";
constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1";
constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1";
constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1";
constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
variable cmd_v : ext_cmd_t;
variable tx_v : boolean;
begin
-- default assignments
spi_dat_s <= '1';
cmd_v := (others => '1');
tx_v := false;
if cmd_fsm_q = CMD then
case ctrl_fsm_q is
when CMD0 =>
cmd_v(cmd_r) := cmd0_c;
tx_v := true;
when CMD1 =>
cmd_v(cmd_r) := cmd1_c;
tx_v := true;
when CMD16 =>
cmd_v(cmd_r) := cmd16_c;
cmd_v(8 + width_bit_cnt_g-3) := '1';
tx_v := true;
when CMD18 =>
cmd_v(cmd_r) := cmd18_c;
-- insert image counter
cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
downto 8 + num_bits_per_img_g) := img_cnt_s;
-- insert set selection
cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1
downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
tx_v := true;
when CMD18_DATA =>
cmd_v(cmd_r) := cmd12_c;
if send_cmd12_q and upper_bitcnt_zero_s then
tx_v := true;
end if;
when CMD55 =>
cmd_v(cmd_r) := cmd55_c;
tx_v := true;
when ACMD41 =>
cmd_v(cmd_r) := acmd41_c;
tx_v := true;
when others =>
null;
end case;
end if;
if tx_v then
spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
end if;
end process transmit;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Optional Image Counter
-----------------------------------------------------------------------------
img_cnt: if width_img_cnt_g > 0 generate
img_cnt_b : spi_counter
generic map (
cnt_width_g => width_img_cnt_g,
cnt_max_g => 2**width_img_cnt_g - 1
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => cnt_en_img_s,
cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0),
cnt_ovfl_o => open
);
img_cnt_s(width_img_cnt_g) <= '0';
end generate;
no_img_cnt: if width_img_cnt_g = 0 generate
img_cnt_s <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- Optional MMC compatibility counter
-----------------------------------------------------------------------------
mmc_cnt: if mmc_compat_clk_div_g > 0 generate
mmc_cnt_b : spi_counter
generic map (
cnt_width_g => width_mmc_clk_div_g,
cnt_max_g => mmc_compat_clk_div_g
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => true_s,
cnt_o => open,
cnt_ovfl_o => mmc_cnt_ovfl_s
);
end generate;
no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
mmc_cnt_ovfl_s <= true;
end generate;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_q;
spi_cs_n_o <= spi_cs_n_q;
spi_data_out_o <= spi_dat_q;
spi_en_outs_o <= '1'
when en_outs_q else
'0';
cfg_clk_o <= cfg_clk_q;
cfg_dat_o <= cfg_dat_q;
detached_o <= '0'
when en_outs_q else
'1';
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: spi_boot.vhd,v $
-- Revision 1.9 2007/02/25 18:24:12 arniml
-- fix type handling of resets
--
-- Revision 1.8 2006/09/11 23:03:36 arniml
-- disable outputs with reset
--
-- Revision 1.7 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.6 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.5 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.4 2005/02/18 06:42:08 arniml
-- clarify wording for images
--
-- Revision 1.3 2005/02/16 18:59:10 arniml
-- include output enable control for SPI outputs
--
-- Revision 1.2 2005/02/13 17:25:51 arniml
-- major update to fix several problems
-- configuration/data download of multiple sets works now
--
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_and_or_inv is
end entity tb_and_or_inv;
architecture test of tb_and_or_inv is
signal a1, a2, b1, b2, y : bit;
begin
dut : entity work.and_or_inv(primitive)
port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
y => y );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111" );
begin
for i in stim_vector'range loop
(a1, a2, b1, b2) <= stim_vector(i);
wait for 10 ns;
assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
or (stim_vector(i)(2) and stim_vector(i)(3)) );
end loop;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_and_or_inv is
end entity tb_and_or_inv;
architecture test of tb_and_or_inv is
signal a1, a2, b1, b2, y : bit;
begin
dut : entity work.and_or_inv(primitive)
port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
y => y );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111" );
begin
for i in stim_vector'range loop
(a1, a2, b1, b2) <= stim_vector(i);
wait for 10 ns;
assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
or (stim_vector(i)(2) and stim_vector(i)(3)) );
end loop;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_and_or_inv is
end entity tb_and_or_inv;
architecture test of tb_and_or_inv is
signal a1, a2, b1, b2, y : bit;
begin
dut : entity work.and_or_inv(primitive)
port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
y => y );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111" );
begin
for i in stim_vector'range loop
(a1, a2, b1, b2) <= stim_vector(i);
wait for 10 ns;
assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
or (stim_vector(i)(2) and stim_vector(i)(3)) );
end loop;
wait;
end process stimulus;
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity iotpanel is
port (
clk: in std_logic;
cs: inout std_logic;
--di: in std_logic;
rgb: out std_logic_vector(5 downto 0);
col: out std_logic_vector(3 downto 0);
stb: out std_logic;
clko: out std_logic;
--idtr: in std_logic;
gpio13: in std_logic;
gpio14: in std_logic;
espreset: out std_logic;
espen: inout std_logic;
esptx: in std_logic;
esprx: out std_logic;
gpio2: inout std_logic;
gpio0: inout std_logic;
gpio5: inout std_logic;
gpio4: inout std_logic;
--espchpd: out std_logic;
gpio16: inout std_logic;
gpio12: inout std_logic;
oe: inout std_logic;
panelen: inout std_logic;
usr: inout std_logic_vector(6 downto 3);
iusr: in std_logic
);
end iotpanel;
architecture Behavioral of iotpanel is
signal shifter: std_logic_vector(9 downto 0);
alias irx: std_logic is usr(5);
alias idtr:std_logic is usr(4);
signal internal_reset_q: std_logic;
signal hclock: std_logic;
signal data_queued: std_logic;
signal internalcs: std_logic;
alias di: std_logic is gpio13;
begin
-- CH_PD Pull-up
-- GPIO16/RST Pull-up
-- GPIO15 Pull-down
-- GPIO2 Pull-up
-- GPIO0 Pull-up for normal or pull-down for bootloader mode.
gpio2 <= 'Z'; -- External pullup
--gpio0 <= not irx; -- RX from external programmer.
gpio0 <= usr(3);
gpio16 <= 'Z'; -- External pullup
gpio12 <= 'Z';
gpio5 <= 'Z';
cs <= '0' when gpio16='1' else 'Z'; -- Startup/Working CS mode.
-- CS is now gpio4
internalcs <= gpio4 when gpio16='0' else '1'; -- Ignore commands when SW not running.
--usr(3) <= gpio4;--'Z';
esprx <= usr(5);
usr(6) <= esptx;
oe <= gpio5 when gpio16='0' else '1';
panelen <= 'Z'; -- not used yet
espen <= 'Z'; -- not used yet
espreset<='0' when idtr='1' else '1';
--espen<='0' when idtr='0' and irx='1' else '1';
stb <= gpio12;
--stb <= clk;
--clko <= gpio14;
process(clk,internalcs)
begin
if internalcs='1' then
shifter <= (others => '0');
elsif rising_edge(clk) then
if internal_reset_q='1' then
shifter(8 downto 2) <= (others => '0');
shifter(1) <= shifter(0);
shifter(0) <= di;
else
shifter <= shifter(shifter'HIGH-1 downto 0) & di;
end if;
end if;
end process;
--clko <= shifter(8);
clko <= hclock;
process(clk,internalcs)
begin
if internalcs='1' then
internal_reset_q<='0';
data_queued<='0';
elsif rising_edge(clk) then
if internal_reset_q='1' then
internal_reset_q<='0';
else
internal_reset_q <= shifter(8);
if shifter(8)='1' then
data_queued<='1';
end if;
end if;
if hclock='1' then
data_queued<='0';
end if;
end if;
end process;
process(clk,internalcs)
begin
if internalcs='1' then
hclock<='0';
elsif rising_edge(clk) then
if shifter(8 downto 6)="001" then
hclock<='0';
else
--if internal_reset_q='1' then
if data_queued='1' and shifter(3)='1' and internal_reset_q='0' then
hclock <= '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if shifter(8 downto 6)="001" then
rgb <= shifter(4 downto 0) & di;
end if;
end if;
end process;
process(gpio4)
begin
if rising_edge(gpio4) then
if shifter(8)='0' then
col <= shifter(3 downto 0);
end if;
end if;
end process;
end Behavioral;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 14;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_12_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_12_no_dsp_32_u : component convolve_kernel_ap_fadd_12_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rawUVCfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rawUVCfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rawUVCfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rawUVCfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rawUVCfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rawUVCfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"0180C01B_0182681B_0202601B_00000020", -- Loc 0C, 08, 04, 00
X"AC130004_AC120004_8DA90000_AC180004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_AC09000C", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Gandhi Puvvada and Prasanjeet Das
-- Date : 07/26/09
--************************************************
-- tag opcode mnemonics result
--************************************************
-- 0 0202601B div $12, $16, $2 $12 = (16/2 = 8)
-- 1 0182681B div $13, $12, $2 $13 = (8/2 = 4)
-- 2 0180C01B div $24, $12, $0 $24 = (8/0 = FFFFFFFF)
-- 3 AC180004 sw $24, 4($0) dmem(1) = FFFFFFFF
-- 4 8DA90000 lw $9, 0($13) $9 = dmem(1) = FFFFFFFF
-- 5 AC120004 sw $18, 4($0) dmem(1)= 18
-- 6 AC130004 sw $19, 4($0) dmem(1)= 19
-- 7 AC09000C sw $9,12($0) dmem(3)= FFFFFFFF
--*************************************************
-- "lw" will be waiting for $13 for about 16 clocks
-- for address calculation.
-- 1st "sw" will be waiting for $24 for about 24 clocks
-- the last two "sw"'s will wait until the "lw" has its address
-- then the last two "sw"'s will bypass "lw", count = 2, addbuffmatch = 2
-- then the first "sw" will leave and addbuffmatch = 3
-- then the first "sw" commits and addbuffmatch = 2
-- Now that the "lw" has no "sw" older in the queue and addbuffmatch = count
-- It gets issued.
-- We can see the CDB tag and CDB valid to recognize the order of appearance on CDB
-- ==================================================================================
-- *******************************************************
-- The expected order of appearance on CDB leaving NOP's
-- ******************************************************
-- first 0 0050601B div $12, $16, $2
-- second 1 004C681B div $13, $12, $2
-- third 5 AC120004 sw $18, 4($0)
-- fourth 6 AC130004 sw $19, 4($0)
-- fifth 2 000CC01B div $24, $0, $12
-- sixth 3 AC180004 sw $24, 4($0)
-- seventh 4 8DA90000 lw $9, 0($13)
-- *****************************************************
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"0180C01B_0182681B_0202601B_00000020", -- Loc 0C, 08, 04, 00
X"AC130004_AC120004_8DA90000_AC180004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_AC09000C", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Gandhi Puvvada and Prasanjeet Das
-- Date : 07/26/09
--************************************************
-- tag opcode mnemonics result
--************************************************
-- 0 0202601B div $12, $16, $2 $12 = (16/2 = 8)
-- 1 0182681B div $13, $12, $2 $13 = (8/2 = 4)
-- 2 0180C01B div $24, $12, $0 $24 = (8/0 = FFFFFFFF)
-- 3 AC180004 sw $24, 4($0) dmem(1) = FFFFFFFF
-- 4 8DA90000 lw $9, 0($13) $9 = dmem(1) = FFFFFFFF
-- 5 AC120004 sw $18, 4($0) dmem(1)= 18
-- 6 AC130004 sw $19, 4($0) dmem(1)= 19
-- 7 AC09000C sw $9,12($0) dmem(3)= FFFFFFFF
--*************************************************
-- "lw" will be waiting for $13 for about 16 clocks
-- for address calculation.
-- 1st "sw" will be waiting for $24 for about 24 clocks
-- the last two "sw"'s will wait until the "lw" has its address
-- then the last two "sw"'s will bypass "lw", count = 2, addbuffmatch = 2
-- then the first "sw" will leave and addbuffmatch = 3
-- then the first "sw" commits and addbuffmatch = 2
-- Now that the "lw" has no "sw" older in the queue and addbuffmatch = count
-- It gets issued.
-- We can see the CDB tag and CDB valid to recognize the order of appearance on CDB
-- ==================================================================================
-- *******************************************************
-- The expected order of appearance on CDB leaving NOP's
-- ******************************************************
-- first 0 0050601B div $12, $16, $2
-- second 1 004C681B div $13, $12, $2
-- third 5 AC120004 sw $18, 4($0)
-- fourth 6 AC130004 sw $19, 4($0)
-- fifth 2 000CC01B div $24, $0, $12
-- sixth 3 AC180004 sw $24, 4($0)
-- seventh 4 8DA90000 lw $9, 0($13)
-- *****************************************************
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"0180C01B_0182681B_0202601B_00000020", -- Loc 0C, 08, 04, 00
X"AC130004_AC120004_8DA90000_AC180004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_AC09000C", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Gandhi Puvvada and Prasanjeet Das
-- Date : 07/26/09
--************************************************
-- tag opcode mnemonics result
--************************************************
-- 0 0202601B div $12, $16, $2 $12 = (16/2 = 8)
-- 1 0182681B div $13, $12, $2 $13 = (8/2 = 4)
-- 2 0180C01B div $24, $12, $0 $24 = (8/0 = FFFFFFFF)
-- 3 AC180004 sw $24, 4($0) dmem(1) = FFFFFFFF
-- 4 8DA90000 lw $9, 0($13) $9 = dmem(1) = FFFFFFFF
-- 5 AC120004 sw $18, 4($0) dmem(1)= 18
-- 6 AC130004 sw $19, 4($0) dmem(1)= 19
-- 7 AC09000C sw $9,12($0) dmem(3)= FFFFFFFF
--*************************************************
-- "lw" will be waiting for $13 for about 16 clocks
-- for address calculation.
-- 1st "sw" will be waiting for $24 for about 24 clocks
-- the last two "sw"'s will wait until the "lw" has its address
-- then the last two "sw"'s will bypass "lw", count = 2, addbuffmatch = 2
-- then the first "sw" will leave and addbuffmatch = 3
-- then the first "sw" commits and addbuffmatch = 2
-- Now that the "lw" has no "sw" older in the queue and addbuffmatch = count
-- It gets issued.
-- We can see the CDB tag and CDB valid to recognize the order of appearance on CDB
-- ==================================================================================
-- *******************************************************
-- The expected order of appearance on CDB leaving NOP's
-- ******************************************************
-- first 0 0050601B div $12, $16, $2
-- second 1 004C681B div $13, $12, $2
-- third 5 AC120004 sw $18, 4($0)
-- fourth 6 AC130004 sw $19, 4($0)
-- fifth 2 000CC01B div $24, $0, $12
-- sixth 3 AC180004 sw $24, 4($0)
-- seventh 4 8DA90000 lw $9, 0($13)
-- *****************************************************
|
-- Copyright (c) 2017 Tampere University of Technology.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : LSU for AlmaIF Integrator
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : fu_lsu_32b.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-05-28
-- Last update: 2019-05-28
-- Platform :
-------------------------------------------------------------------------------
-- Description: 32 bit wide LSU with parametric endianness
-- External ports:
-- | Signal | Comment
-- ---------------------------------------------------------------------------
-- | read_idx_out | Read index from the FU to the debug interface
-- ---------------------------------------------------------------------------
--
-- Revisions :
-- Date Version Author Description
-- 2019-05-28 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fu_aql_minimal is
port(
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic;
-- External signals
read_idx_out : out std_logic_vector(64-1 downto 0);
read_idx_clear_in : in std_logic_vector(0 downto 0);
-- Architectural ports
t1_data_in : in std_logic_vector(32-1 downto 0);
t1_load_in : in std_logic;
t1_opcode_in : in std_logic_vector(0 downto 0);
r1_data_out : out std_logic_vector(32-1 downto 0)
);
end fu_aql_minimal;
architecture rtl of fu_aql_minimal is
constant OPC_GET_READ_IDX_LOW : std_logic_vector(t1_opcode_in'range) := "0";
constant OPC_INC_READ_IDX : std_logic_vector(t1_opcode_in'range) := "1";
signal read_idx_r : std_logic_vector(read_idx_out'range);
signal result_r : std_logic_vector(32 - 1 downto 0);
begin
read_idx_out <= read_idx_r;
r1_data_out <= result_r;
operation_logic : process(clk, rstx)
begin
if rstx = '0' then
read_idx_r <= (others => '0');
result_r <= (others => '0');
elsif rising_edge(clk) then
if read_idx_clear_in = "1" then
read_idx_r <= (others => '0');
end if;
if glock = '0' then
if t1_load_in = '1' then
case t1_opcode_in is
when OPC_GET_READ_IDX_LOW =>
result_r <= read_idx_r(result_r'range);
when others => -- Increment
read_idx_r <= std_logic_vector(unsigned(read_idx_r)
+ unsigned(t1_data_in));
end case;
end if;
end if;
end if;
end process operation_logic;
end rtl;
|
-- Copyright (c) 2017 Tampere University of Technology.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : LSU for AlmaIF Integrator
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : fu_lsu_32b.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-05-28
-- Last update: 2019-05-28
-- Platform :
-------------------------------------------------------------------------------
-- Description: 32 bit wide LSU with parametric endianness
-- External ports:
-- | Signal | Comment
-- ---------------------------------------------------------------------------
-- | read_idx_out | Read index from the FU to the debug interface
-- ---------------------------------------------------------------------------
--
-- Revisions :
-- Date Version Author Description
-- 2019-05-28 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fu_aql_minimal is
port(
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic;
-- External signals
read_idx_out : out std_logic_vector(64-1 downto 0);
read_idx_clear_in : in std_logic_vector(0 downto 0);
-- Architectural ports
t1_data_in : in std_logic_vector(32-1 downto 0);
t1_load_in : in std_logic;
t1_opcode_in : in std_logic_vector(0 downto 0);
r1_data_out : out std_logic_vector(32-1 downto 0)
);
end fu_aql_minimal;
architecture rtl of fu_aql_minimal is
constant OPC_GET_READ_IDX_LOW : std_logic_vector(t1_opcode_in'range) := "0";
constant OPC_INC_READ_IDX : std_logic_vector(t1_opcode_in'range) := "1";
signal read_idx_r : std_logic_vector(read_idx_out'range);
signal result_r : std_logic_vector(32 - 1 downto 0);
begin
read_idx_out <= read_idx_r;
r1_data_out <= result_r;
operation_logic : process(clk, rstx)
begin
if rstx = '0' then
read_idx_r <= (others => '0');
result_r <= (others => '0');
elsif rising_edge(clk) then
if read_idx_clear_in = "1" then
read_idx_r <= (others => '0');
end if;
if glock = '0' then
if t1_load_in = '1' then
case t1_opcode_in is
when OPC_GET_READ_IDX_LOW =>
result_r <= read_idx_r(result_r'range);
when others => -- Increment
read_idx_r <= std_logic_vector(unsigned(read_idx_r)
+ unsigned(t1_data_in));
end case;
end if;
end if;
end if;
end process operation_logic;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1868.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01868ent IS
END c07s01b00x00p08n01i01868ent;
ARCHITECTURE c07s01b00x00p08n01i01868arch OF c07s01b00x00p08n01i01868ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
blk : block (s_int = 0)
begin
with blk select -- block label illegal here
obus(0) <= 5 after 5 ns when true;
end block blk;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01868 - Block labels are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01868arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1868.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01868ent IS
END c07s01b00x00p08n01i01868ent;
ARCHITECTURE c07s01b00x00p08n01i01868arch OF c07s01b00x00p08n01i01868ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
blk : block (s_int = 0)
begin
with blk select -- block label illegal here
obus(0) <= 5 after 5 ns when true;
end block blk;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01868 - Block labels are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01868arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1868.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01868ent IS
END c07s01b00x00p08n01i01868ent;
ARCHITECTURE c07s01b00x00p08n01i01868arch OF c07s01b00x00p08n01i01868ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
blk : block (s_int = 0)
begin
with blk select -- block label illegal here
obus(0) <= 5 after 5 ns when true;
end block blk;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01868 - Block labels are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01868arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and2to1 is
port (
A: in std_logic;
B: in std_logic;
Z: out std_logic
);
end and2to1;
architecture behavioral of and2to1 is
begin
Z <= A and B;
end behavioral; |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: ahbarb
-- File: ahbarb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB arbiter and decoder
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity ahbarb is
generic (
masters : integer := 2; -- number of masters
defmast : integer := 1 -- default master
);
port (
rst : in std_logic;
clk : in clk_type;
msti : out ahb_mst_in_vector(0 to masters-1);
msto : in ahb_mst_out_vector(0 to masters-1);
slvi : out ahb_slv_in_vector(0 to AHB_SLV_MAX-1);
slvo : in ahb_slv_out_vector(0 to AHB_SLV_MAX-1)
);
end;
architecture rtl of ahbarb is
constant MIMAX : integer := log2x(masters) - 1;
constant SIMAX : integer := log2(AHB_SLV_MAX+1) - 1;
type reg_type is record
hmaster : std_logic_vector(MIMAX downto 0);
hmasterd : std_logic_vector(MIMAX downto 0);
hslave : std_logic_vector(SIMAX downto 0);
hready : std_logic; -- needed for two-cycle error response
hlock : std_logic;
hmasterlock : std_logic;
htrans : std_logic_vector(1 downto 0); -- transfer type
end record;
constant ahbmin : integer := AHB_SLV_ADDR_MSB-1;
type nmstarr is array ( 1 to 5) of integer range 0 to masters-1;
type nvalarr is array ( 1 to 5) of boolean;
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(masters-1 downto 0);
begin
comb : process(rst, msto, slvo, r, rsplit)
variable rv : reg_type;
variable rhmaster, rhmasterd : integer range 0 to masters -1;
variable rhslave : integer range 0 to AHB_SLV_MAX;
variable nhmaster, hmaster : integer range 0 to masters -1;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable hrdata : std_logic_vector(31 downto 0); -- read data bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hresp : std_logic_vector(1 downto 0); -- respons type
variable hwrite : std_logic; -- read/write
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hprot : std_logic_vector(3 downto 0); -- protection info
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hgrant : std_logic_vector(0 to masters-1); -- bus grant
variable hsel : std_logic_vector(0 to AHB_SLV_MAX); -- slave select
variable hready : std_logic; -- ready
variable hmastlock : std_logic;
variable nslave : natural range 0 to AHB_SLV_MAX;
variable ahbaddr : std_logic_vector(ahbmin downto 0);
variable vsplit : std_logic_vector(masters-1 downto 0);
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable htmp : std_logic_vector(3 downto 0);
begin
rv := r; rv.hready := '0';
-- bus multiplexers
-- pragma translate_off
if not is_x(r.hmaster) then
-- pragma translate_on
rhmaster := conv_integer(unsigned(r.hmaster));
-- pragma translate_off
end if;
if not is_x(r.hmasterd) then
-- pragma translate_on
rhmasterd := conv_integer(unsigned(r.hmasterd));
-- pragma translate_off
end if;
if not is_x(r.hslave) then
-- pragma translate_on
rhslave := conv_integer(unsigned(r.hslave));
-- pragma translate_off
end if;
-- pragma translate_on
haddr := msto(rhmaster).haddr;
htrans := msto(rhmaster).htrans;
hwrite := msto(rhmaster).hwrite;
hsize := msto(rhmaster).hsize;
hprot := msto(rhmaster).hprot;
hburst := msto(rhmaster).hburst;
hmastlock := msto(rhmaster).hlock;
hwdata := msto(rhmasterd).hwdata;
if rhslave /= AHB_SLV_MAX then
hready := slvo(rhslave).hready;
hrdata := slvo(rhslave).hrdata;
hresp := slvo(rhslave).hresp ;
else
-- default slave
hrdata := (others => '-');
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; rv.hready := not r.hready;
end if;
end if;
-- Find next master:
-- * priority is fixed, highest index has highest priority
-- * splitted masters are not granted
-- * burst transfers can be interrupted
nvalid(1 to 4) := (others => false); nvalid(5) := true;
nmst(1 to 4) := (others => 0); nmst(5) := defmast; nhmaster := rhmaster;
if ((r.hmasterlock = '0') and (msto(rhmaster).htrans /= HTRANS_SEQ)) then
for i in 0 to (masters -1) loop
if ((rsplit(i) = '0') or not AHB_SPLIT) then
if (msto(i).hbusreq = '1') then
nmst(3) := i; nvalid(3) := true;
end if;
if not ((nmst(4) = defmast) and nvalid(4)) then
nmst(4) := i; nvalid(4) := true;
end if;
end if;
end loop;
for i in 1 to 5 loop
if nvalid(i) then nhmaster := nmst(i); exit; end if;
end loop;
end if;
rv.hlock := msto(nhmaster).hlock;
hgrant := (others => '0'); hgrant(nhmaster) := '1';
-- select slave
nslave := AHB_SLV_MAX;
ahbaddr := haddr(31 downto (31 - ahbmin));
for i in AHB_SLVTABLE'range loop --'
if AHB_SLVTABLE(i).enable and
(ahbaddr >= AHB_SLVTABLE(i).firstaddr(ahbmin downto 0)) and
(ahbaddr <= AHB_SLVTABLE(i).lastaddr(ahbmin downto 0))
then nslave := AHB_SLVTABLE(i).index; end if;
end loop;
if htrans = HTRANS_IDLE then nslave := AHB_SLV_MAX; end if;
hsel := (others => '0'); hsel(nslave) := '1';
-- latch active master and slave
if hready = '1' then
rv.hmaster := std_logic_vector(conv_unsigned(nhmaster, MIMAX + 1));
rv.hmasterd := r.hmaster;
rv.hslave := std_logic_vector(conv_unsigned(nslave, SIMAX + 1));
rv.htrans := htrans;
rv.hmasterlock := r.hlock;
end if;
-- latch HLOCK
-- split support
vsplit := (others => '0');
if AHB_SPLIT then
vsplit := rsplit;
if hresp = HRESP_SPLIT then vsplit(rhmasterd) := '1'; end if;
for i in AHB_SLVTABLE'range loop --'
if AHB_SLVTABLE(i).split then
vsplit := vsplit and not slvo(AHB_SLVTABLE(i).index).hsplit(masters-1 downto 0);
end if;
end loop;
end if;
-- reset operation
if (rst = '0') then
rv.hmaster := (others => '0'); rv.hmasterlock := '0';
rv.hslave := std_logic_vector(conv_unsigned(AHB_SLV_MAX, SIMAX+1));
hsel := (others => '0'); rv.htrans := HTRANS_IDLE;
hready := '1'; vsplit := (others => '0');
end if;
-- drive master inputs
for i in 0 to (masters -1) loop
msti(i).hgrant <= hgrant(i);
msti(i).hready <= hready;
msti(i).hrdata <= hrdata;
msti(i).hresp <= hresp;
end loop;
-- drive slave inputs
for i in 0 to (AHB_SLV_MAX -1) loop
slvi(i).haddr <= haddr;
slvi(i).htrans <= htrans;
slvi(i).hwrite <= hwrite;
slvi(i).hsize <= hsize;
slvi(i).hburst <= hburst;
slvi(i).hready <= hready;
slvi(i).hwdata <= hwdata;
slvi(i).hsel <= hsel(i);
htmp := "0000"; htmp(MIMAX downto 0) := r.hmaster;
slvi(i).hmaster <= htmp;
slvi(i).hmastlock <= r.hmasterlock;
end loop;
-- assign register inputs
rin <= rv;
rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
splitreg : if AHB_SPLIT generate
reg1 : process(clk)
begin if rising_edge(clk) then rsplit <= rsplitin; end if; end process;
end generate;
end;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_nov;
architecture behaviour of s1494_nov is
constant s000000: std_logic_vector(5 downto 0) := "000000";
constant s001110: std_logic_vector(5 downto 0) := "000001";
constant s011000: std_logic_vector(5 downto 0) := "101100";
constant s010100: std_logic_vector(5 downto 0) := "100111";
constant s010011: std_logic_vector(5 downto 0) := "111011";
constant s000100: std_logic_vector(5 downto 0) := "100110";
constant s010111: std_logic_vector(5 downto 0) := "110011";
constant s001100: std_logic_vector(5 downto 0) := "010111";
constant s011011: std_logic_vector(5 downto 0) := "110110";
constant s100110: std_logic_vector(5 downto 0) := "010110";
constant s011101: std_logic_vector(5 downto 0) := "011101";
constant s101110: std_logic_vector(5 downto 0) := "000111";
constant s010101: std_logic_vector(5 downto 0) := "101111";
constant s111110: std_logic_vector(5 downto 0) := "000110";
constant s000011: std_logic_vector(5 downto 0) := "111111";
constant s111011: std_logic_vector(5 downto 0) := "000010";
constant s100111: std_logic_vector(5 downto 0) := "001111";
constant s010000: std_logic_vector(5 downto 0) := "010000";
constant s011010: std_logic_vector(5 downto 0) := "111001";
constant s110010: std_logic_vector(5 downto 0) := "001110";
constant s011100: std_logic_vector(5 downto 0) := "110101";
constant s101010: std_logic_vector(5 downto 0) := "100101";
constant s111010: std_logic_vector(5 downto 0) := "111110";
constant s100000: std_logic_vector(5 downto 0) := "100100";
constant s101000: std_logic_vector(5 downto 0) := "111010";
constant s010010: std_logic_vector(5 downto 0) := "000101";
constant s001010: std_logic_vector(5 downto 0) := "111100";
constant s100100: std_logic_vector(5 downto 0) := "101011";
constant s001011: std_logic_vector(5 downto 0) := "110010";
constant s110100: std_logic_vector(5 downto 0) := "101010";
constant s111000: std_logic_vector(5 downto 0) := "010101";
constant s001000: std_logic_vector(5 downto 0) := "011111";
constant s011110: std_logic_vector(5 downto 0) := "110111";
constant s000010: std_logic_vector(5 downto 0) := "011011";
constant s110011: std_logic_vector(5 downto 0) := "000100";
constant s000111: std_logic_vector(5 downto 0) := "110001";
constant s101011: std_logic_vector(5 downto 0) := "010100";
constant s001111: std_logic_vector(5 downto 0) := "111000";
constant s110000: std_logic_vector(5 downto 0) := "101110";
constant s000110: std_logic_vector(5 downto 0) := "101001";
constant s100010: std_logic_vector(5 downto 0) := "001101";
constant s010001: std_logic_vector(5 downto 0) := "111101";
constant s110110: std_logic_vector(5 downto 0) := "001100";
constant s011111: std_logic_vector(5 downto 0) := "110100";
constant s010110: std_logic_vector(5 downto 0) := "101101";
constant s111100: std_logic_vector(5 downto 0) := "001000";
constant s100011: std_logic_vector(5 downto 0) := "011110";
constant s101100: std_logic_vector(5 downto 0) := "011100";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (3 downto 0);
SomaResult: out std_logic_vector (3 downto 0);
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (3 downto 1);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
BEGIN
--somador--
Som0: Soma1 PORT MAP (
CarryIn,
val1(0),
val2(0),
SomaResult(0),
carry(1)
);
Som1: Soma1 PORT MAP (
carry(1),
val1(1),
val2(1),
SomaResult(1),
carry(2)
);
Som2: Soma1 PORT MAP (
carry(2),
val1(2),
val2(2),
SomaResult(2),
carry(3)
);
Som3: Soma1 PORT MAP (
carry(3),
val1(3),
val2(3),
SomaResult(3),
CarryOut
);
END strc_RCA ; |
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (3 downto 0);
SomaResult: out std_logic_vector (3 downto 0);
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (3 downto 1);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
BEGIN
--somador--
Som0: Soma1 PORT MAP (
CarryIn,
val1(0),
val2(0),
SomaResult(0),
carry(1)
);
Som1: Soma1 PORT MAP (
carry(1),
val1(1),
val2(1),
SomaResult(1),
carry(2)
);
Som2: Soma1 PORT MAP (
carry(2),
val1(2),
val2(2),
SomaResult(2),
carry(3)
);
Som3: Soma1 PORT MAP (
carry(3),
val1(3),
val2(3),
SomaResult(3),
CarryOut
);
END strc_RCA ; |
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (3 downto 0);
SomaResult: out std_logic_vector (3 downto 0);
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (3 downto 1);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
BEGIN
--somador--
Som0: Soma1 PORT MAP (
CarryIn,
val1(0),
val2(0),
SomaResult(0),
carry(1)
);
Som1: Soma1 PORT MAP (
carry(1),
val1(1),
val2(1),
SomaResult(1),
carry(2)
);
Som2: Soma1 PORT MAP (
carry(2),
val1(2),
val2(2),
SomaResult(2),
carry(3)
);
Som3: Soma1 PORT MAP (
carry(3),
val1(3),
val2(3),
SomaResult(3),
CarryOut
);
END strc_RCA ; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY arctan IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END arctan;
ARCHITECTURE arctan_arch OF arctan IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF arctan_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF arctan_arch: ARCHITECTURE IS "cordic_v6_0_11,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF arctan_arch : ARCHITECTURE IS "arctan,cordic_v6_0_11,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF arctan_arch: ARCHITECTURE IS "arctan,cordic_v6_0_11,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cordic,x_ipVersion=6.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ARCHITECTURE=2,C_CORDIC_FUNCTION=3,C_COARSE_ROTATE=0,C_DATA_FORMAT=0,C_XDEVICEFAMILY=zynq,C_HAS_ACLKEN=0,C_HAS_ACLK=1,C_HAS_S_AXIS_CARTESIAN=1,C_HAS_S_AXIS_PHASE=0,C_HAS_ARESETN=0,C_INPUT_WIDTH=16,C_ITERATIONS=0,C_OUTPUT_WIDTH=16,C_PHASE_FORMAT=0,C_PIPELINE_MODE=-2,C_PRECISION=0,C_ROUND_MODE=0,C_SCALE_COMP=0,C_THROTTLE" &
"_SCHEME=3,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_PHASE_TUSER=0,C_HAS_S_AXIS_PHASE_TLAST=0,C_S_AXIS_PHASE_TDATA_WIDTH=16,C_S_AXIS_PHASE_TUSER_WIDTH=1,C_HAS_S_AXIS_CARTESIAN_TUSER=0,C_HAS_S_AXIS_CARTESIAN_TLAST=0,C_S_AXIS_CARTESIAN_TDATA_WIDTH=32,C_S_AXIS_CARTESIAN_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=16,C_M_AXIS_DOUT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 3,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 0,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END arctan_arch;
|
---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity vga is
port (
-- Comum
clk_27Mhz, rstn : in std_logic;
-- Conexao com a memoria
main_mem_clk : out std_logic;
main_mem_addr : out std_logic_vector(10 downto 0);
main_mem_data : in std_logic_vector(7 downto 0);
-- Conexao com o mouse
mouse_pos_x : in std_logic_vector(9 downto 0);
mouse_pos_y : in std_logic_vector(9 downto 0);
mouse_click_l : in std_logic;
-- Conexao com o controlador jogo
time_u, time_d, time_c : in std_logic_vector (3 downto 0);
mine_u, mine_d, mine_c : in std_logic_vector (3 downto 0);
game_state : in std_logic_vector(1 downto 0);
-- Conexao com o monitor
vga_hsync, vga_vsync : out std_logic;
vga_r, vga_g, vga_b : out std_logic_vector(3 downto 0)
);
end entity;
architecture vga_logic of vga is
signal gfx_x, gfx_y : std_logic_vector(3 downto 0);
signal gfx_elem : std_logic_vector(5 downto 0);
signal gfx_data : std_logic_vector(3 downto 0);
signal mouse_data : std_logic_vector(3 downto 0);
signal mouse_visible : std_logic;
signal vga_data : std_logic_vector(3 downto 0);
signal h_count, h_count_d : std_logic_vector(9 downto 0);
signal v_count, v_count_d : std_logic_vector(9 downto 0);
signal vga_clk : std_logic;
begin
main_mem_clk <= vga_clk;
main_mem_addr <= v_count(8 downto 4) & h_count(9 downto 4);
ELEMDEC: vga_elem_dec port map (main_mem_data,
v_count_d(3 downto 0), h_count_d(3 downto 0),
time_u, time_d, time_c, mine_u, mine_d, mine_c,
mouse_click_l, game_state, gfx_x, gfx_y, gfx_elem);
MOUSEDEC: vga_mouse_dec port map (h_count_d, v_count_d,
mouse_pos_x, mouse_pos_y, mouse_data, mouse_visible);
COMPOSER: vga_data <= mouse_data when mouse_visible = '1' else gfx_data;
GFXROM: gfx port map (gfx_elem & gfx_y & gfx_x, vga_clk, gfx_data);
VGACOUNT: vga_counter port map (clk_27Mhz, rstn, vga_data,
vga_hsync, vga_vsync, vga_r, vga_g, vga_b, vga_clk,
h_count, h_count_d, v_count, v_count_d);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc124.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n15i00124ent IS
port (PT: linkage BOOLEAN);
END c04s03b02x00p29n15i00124ent;
ARCHITECTURE c04s03b02x00p29n15i00124arch OF c04s03b02x00p29n15i00124ent IS
BEGIN
TESTING: PROCESS
Variable I2 : BOOLEAN;
BEGIN
I2 := PT'LAST_VALUE; -- Failure_here
-- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n15i00124 - Attributes of interface elements of mode linkage can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n15i00124arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc124.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n15i00124ent IS
port (PT: linkage BOOLEAN);
END c04s03b02x00p29n15i00124ent;
ARCHITECTURE c04s03b02x00p29n15i00124arch OF c04s03b02x00p29n15i00124ent IS
BEGIN
TESTING: PROCESS
Variable I2 : BOOLEAN;
BEGIN
I2 := PT'LAST_VALUE; -- Failure_here
-- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n15i00124 - Attributes of interface elements of mode linkage can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n15i00124arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc124.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n15i00124ent IS
port (PT: linkage BOOLEAN);
END c04s03b02x00p29n15i00124ent;
ARCHITECTURE c04s03b02x00p29n15i00124arch OF c04s03b02x00p29n15i00124ent IS
BEGIN
TESTING: PROCESS
Variable I2 : BOOLEAN;
BEGIN
I2 := PT'LAST_VALUE; -- Failure_here
-- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n15i00124 - Attributes of interface elements of mode linkage can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n15i00124arch;
|
--------------------------------------------------
-- Register mapping
--------------------------------------------------
--
-- reg 0 (partial R/W)
-- 15-00:16 : Number of data items per frame
-- 31-16:16 : Max number of data items per frame (read-only)
--
-- reg 1 (partial R/W)
-- 15-00:16 : Number of neurons in first stage
-- 31-16:16 : Max number of neurons in first stage (read-only)
--
-- reg 2 (partial R/W)
-- 15-00:16 : Number of neurons in second stage
-- 31-16:16 : Max number of neurons in second stage (read-only)
--
-- reg 3 (partial R/W)
-- 03-00:4 : What the PC is sending
-- 0000 = nothing
-- 0001 = frame data
-- 0010 = config for level 1
-- 0100 = config for recoding 1-2
-- 1000 = config for level 2
-- 08:1 : clear all (not written to register)
-- 09:1 : Read master AXI busy state
--
-- reg 4 (unused) : sortie de la première FIFO
-- reg 5 (unused) : sortie de la deuxième FIFO
--
-- reg 6 (R/W)
-- 31-00:32 : Number of NN output values to write back to DDR
--
-- reg 7 (unused) : sortie de la troisième FIFO
-- reg 8 (unused) : sortie de la quatrième FIFO
-- reg 9 (unused)
--
-- reg 10 (R/W)
-- 31-00:32 : Address for DDR read
--
-- reg 11 (R/W)
-- 31-00:32 : Address for DDR write
--
-- reg 12 (R/W)
-- 31-00:32 : Number of bursts for DDR Read. Start on write.
--
-- reg 13 (R/W)
-- 31-00:32 : Number of bursts for DDR write. Start on write.
--
-- reg 14 (read only)
-- 07-00:8 : count of fifo between level 1 and recoding 1-2
-- 15-08:8 : count of fifo between recoding 1-2 and level 2
-- 23-16:8 : count of fifo after level 2
--
-- reg 15 (read only)
-- 31-16:16 : fifo rdy/ack signals, in and out: 12 signals
--
--------------------------------------------------
-- Protocol description
--------------------------------------------------
--
-- One weight per DDR word
-- One data per DDR word
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myaxifullmaster_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
mymaster_addr_inw : out std_logic_vector(31 downto 0);
mymaster_addr_inr : out std_logic_vector(31 downto 0);
mymaster_burstnb_inw : out std_logic_vector(31 downto 0);
mymaster_burstnb_inr : out std_logic_vector(31 downto 0);
mymaster_startw : out std_logic;
mymaster_startr : out std_logic;
mymaster_busyw : in std_logic;
mymaster_busyr : in std_logic;
mymaster_sensor : in std_logic_vector(31 downto 0); -- For various debug signals
mymaster_fifor_data : in std_logic_vector(31 downto 0);
mymaster_fifor_en : in std_logic;
mymaster_fifor_cnt : out std_logic_vector(15 downto 0);
mymaster_fifow_data : out std_logic_vector(31 downto 0);
mymaster_fifow_en : in std_logic;
mymaster_fifow_cnt : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end myaxifullmaster_v1_0_S00_AXI;
architecture arch_imp of myaxifullmaster_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
-- Some signals to make reset last longer
--------------------------------------------------
constant RESET_DURATION : natural := 64;
signal reset_counter : unsigned(15 downto 0) := (others => '0');
signal reset_reg : std_logic := '0';
------------------------------------------------
-- Signals for user logic register space
--------------------------------------------------
-- Number of Slave Registers 16
signal slv_reg0 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg1 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg2 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg3 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg4 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg5 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg6 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg7 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg8 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg9 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg10 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg11 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg12 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg13 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg14 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg15 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal slv_reg_rdaddr : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal slv_reg_wraddr : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal slv_reg_rddata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_wrdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_wstrb : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
----------------------------------------------------
-- Definitions for the neural network
----------------------------------------------------
constant LAYER1_WDATA : natural := 32;
constant LAYER1_WWEIGHT : natural := 16;
constant LAYER1_WACCU : natural := 32;
constant LAYER1_FSIZE : natural := 784;
--constant LAYER1_FSIZE : natural := 64;
constant LAYER1_NBNEU : natural := 200;
--constant LAYER1_NBNEU : natural := 4;
constant RECODE_WDATA : natural := LAYER1_WACCU;
constant RECODE_WWEIGHT : natural := 16;
constant RECODE_WOUT : natural := 32;
constant RECODE_FSIZE : natural := LAYER1_NBNEU;
constant LAYER2_WDATA : natural := RECODE_WOUT;
constant LAYER2_WWEIGHT : natural := 16;
constant LAYER2_WACCU : natural := 32;
constant LAYER2_FSIZE : natural := LAYER1_NBNEU;
-- constant LAYER2_NBNEU : natural := 3;
constant LAYER2_NBNEU : natural := 10;
signal req_start_recv : std_logic := '0';
signal req_start_send : std_logic := '0';
signal items_per_frame : unsigned(15 downto 0) := (others => '0');
constant CST_RECV_FRAME : std_logic_vector(3 downto 0) := "0001";
constant CST_RECV_CFG_LEVEL1 : std_logic_vector(3 downto 0) := "0010";
constant CST_RECV_CFG_RECODE12 : std_logic_vector(3 downto 0) := "0100";
constant CST_RECV_CFG_LEVEL2 : std_logic_vector(3 downto 0) := "1000";
signal cur_recv : std_logic_vector(3 downto 0) := CST_RECV_FRAME;
signal recv_frame : std_logic := '0';
signal recv_cfgl1 : std_logic := '0';
signal recv_cfgr1 : std_logic := '0';
signal recv_cfgl2 : std_logic := '0';
-- Signals to control obtaining output values and sending them over PCIe
signal out_cur_nb, out_cur_nb_n : unsigned(31 downto 0) := (others => '0'); -- Number of values obtained
signal out_want_nb : unsigned(31 downto 0) := (others => '0'); -- Number of values to send
signal out_getres, out_getres_n : std_logic := '0';
signal out_gotall, out_gotall_n : std_logic := '0';
constant DDRFIFOS_DEPTH : natural := 64;
constant FIFOS_CNTW : natural := 8;
----------------------------------------------------
-- Components
----------------------------------------------------
-- The circular buffer / FIFO component
component circbuf_fast is
generic (
DATAW : natural := 32;
DEPTH : natural := 64;
CNTW : natural := 8
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end component;
-- Then component for one layel of the NN
component nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACCU : natural := 48;
-- Parameters for frame and number of neurons
FSIZE : natural := 1000;
NBNEU : natural := 1000
);
port (
clk : in std_logic;
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- The component to recode neuron outputs
component recode is
generic(
WDATA : natural;
WWEIGHT : natural;
WOUT : natural;
FSIZE : natural
);
port(
clk : in std_logic;
-- Ports for address control
addr_clear : in std_logic;
-- Ports for Write into memory
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified number of neurons
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Data output
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- Signals to connect the instantiated FIFO for data read from DDR
signal inst_rdbuf_clear : std_logic := '0';
signal inst_rdbuf_in_data : std_logic_vector(31 downto 0);
signal inst_rdbuf_in_rdy : std_logic := '0';
signal inst_rdbuf_in_ack : std_logic := '0';
signal inst_rdbuf_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_rdbuf_out_data : std_logic_vector(31 downto 0);
signal inst_rdbuf_out_rdy : std_logic := '0';
signal inst_rdbuf_out_ack : std_logic := '0';
signal inst_rdbuf_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to instantiate level 1
signal inst_layer1_clear : std_logic;
signal inst_layer1_write_mode : std_logic;
signal inst_layer1_write_data : std_logic_vector(LAYER1_WDATA-1 downto 0);
signal inst_layer1_write_enable : std_logic;
signal inst_layer1_write_ready : std_logic;
signal inst_layer1_user_fsize : std_logic_vector(15 downto 0);
signal inst_layer1_user_nbneu : std_logic_vector(15 downto 0);
signal inst_layer1_data_in : std_logic_vector(LAYER1_WDATA-1 downto 0);
signal inst_layer1_data_in_valid : std_logic;
signal inst_layer1_data_in_ready : std_logic;
signal inst_layer1_data_out : std_logic_vector(LAYER1_WACCU-1 downto 0);
signal inst_layer1_data_out_valid : std_logic;
signal inst_layer1_end_of_frame : std_logic;
signal inst_layer1_out_fifo_room : std_logic_vector(15 downto 0);
-- Signals to instantiate FIFO between level 1 and recode
signal inst_fifo_1r_clear : std_logic := '0';
signal inst_fifo_1r_in_data : std_logic_vector(LAYER1_WACCU-1 downto 0);
signal inst_fifo_1r_in_rdy : std_logic := '0';
signal inst_fifo_1r_in_ack : std_logic := '0';
signal inst_fifo_1r_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_fifo_1r_out_data : std_logic_vector(LAYER1_WACCU-1 downto 0);
signal inst_fifo_1r_out_rdy : std_logic := '0';
signal inst_fifo_1r_out_ack : std_logic := '0';
signal inst_fifo_1r_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to instantiate recoding between levels 1 and 2
signal inst_recode_addr_clear : std_logic;
signal inst_recode_write_mode : std_logic;
signal inst_recode_write_data : std_logic_vector(LAYER1_WACCU - 1 downto 0);
signal inst_recode_write_enable : std_logic;
signal inst_recode_write_ready : std_logic;
signal inst_recode_user_nbneu : std_logic_vector(15 downto 0);
signal inst_recode_data_in : std_logic_vector(RECODE_WDATA-1 downto 0);
signal inst_recode_data_in_valid : std_logic;
signal inst_recode_data_in_ready : std_logic;
signal inst_recode_data_out : std_logic_vector(RECODE_WOUT-1 downto 0);
signal inst_recode_data_out_valid : std_logic;
signal inst_recode_out_fifo_room : std_logic_vector(15 downto 0);
-- Signals to instantiate FIFO between recode and level 2
signal inst_fifo_r2_clear : std_logic := '0';
signal inst_fifo_r2_in_data : std_logic_vector(RECODE_WOUT-1 downto 0);
signal inst_fifo_r2_in_rdy : std_logic := '0';
signal inst_fifo_r2_in_ack : std_logic := '0';
signal inst_fifo_r2_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_fifo_r2_out_data : std_logic_vector(RECODE_WOUT-1 downto 0);
signal inst_fifo_r2_out_rdy : std_logic := '0';
signal inst_fifo_r2_out_ack : std_logic := '0';
signal inst_fifo_r2_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to instantiate level 2
signal inst_layer2_clear : std_logic;
signal inst_layer2_write_mode : std_logic;
signal inst_layer2_write_data : std_logic_vector(LAYER2_WDATA-1 downto 0);
signal inst_layer2_write_enable : std_logic;
signal inst_layer2_write_ready : std_logic;
signal inst_layer2_user_fsize : std_logic_vector(15 downto 0);
signal inst_layer2_user_nbneu : std_logic_vector(15 downto 0);
signal inst_layer2_data_in : std_logic_vector(LAYER2_WDATA-1 downto 0);
signal inst_layer2_data_in_valid : std_logic;
signal inst_layer2_data_in_ready : std_logic;
signal inst_layer2_data_out : std_logic_vector(LAYER2_WACCU-1 downto 0);
signal inst_layer2_data_out_valid : std_logic;
signal inst_layer2_end_of_frame : std_logic;
signal inst_layer2_out_fifo_room : std_logic_vector(15 downto 0);
-- Signals to instantiate FIFO between level 2 and output
signal inst_fifo_2o_clear : std_logic := '0';
signal inst_fifo_2o_in_data : std_logic_vector(LAYER2_WACCU-1 downto 0);
signal inst_fifo_2o_in_rdy : std_logic := '0';
signal inst_fifo_2o_in_ack : std_logic := '0';
signal inst_fifo_2o_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_fifo_2o_out_data : std_logic_vector(LAYER2_WACCU-1 downto 0);
signal inst_fifo_2o_out_rdy : std_logic := '0';
signal inst_fifo_2o_out_ack : std_logic := '0';
signal inst_fifo_2o_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to connect the instantiated FIFO for data read from DDR
signal inst_wrbuf_clear : std_logic := '0';
signal inst_wrbuf_in_data : std_logic_vector(31 downto 0);
signal inst_wrbuf_in_rdy : std_logic := '0';
signal inst_wrbuf_in_ack : std_logic := '0';
signal inst_wrbuf_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_wrbuf_out_data : std_logic_vector(31 downto 0);
signal inst_wrbuf_out_rdy : std_logic := '0';
signal inst_wrbuf_out_ack : std_logic := '0';
signal inst_wrbuf_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
begin
----------------------------------
-- AXI functionality
----------------------------------
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- State machine for AXI Write operations
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
axi_awready <= '0';
axi_awaddr <= (others => '0');
else
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both S_AXI_AWVALID and S_AXI_WVALID are asserted.
if axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' then
-- Slave is ready to accept write data when there is a valid write address and write data on the write address and data bus.
-- This design expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both S_AXI_AWVALID and S_AXI_WVALID are asserted.
if axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
-- Slave is ready to accept write address when there is a valid write address and write data on the write address and data bus.
-- This design expects no outstanding transactions.
axi_awready <= '1';
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- Write strobes are used to select byte enables of slave registers while writing.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
-- State machine for AXI Write operations
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg_wren <= '0';
else
-- Note: Buffering these signals is optional. It improves routing.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID;
slv_reg_wraddr <= axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
slv_reg_wrdata <= S_AXI_WDATA;
slv_reg_wstrb <= S_AXI_WSTRB;
end if;
end if;
end process;
-- State machine for AXI Write response
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of write transaction.
if axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' then
axi_bvalid <= '1';
axi_bresp <= "00";
end if;
-- Check if bready is asserted while bvalid is high
-- (there is a possibility that bready is always asserted high)
if S_AXI_BREADY = '1' and axi_bvalid = '1' then
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- State machine for AXI Read operation
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '0');
axi_rvalid <= '0';
axi_rresp <= "00";
axi_rdata <= (others => '0');
else
-- Get the read address
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when S_AXI_ARVALID is asserted.
-- The read address is also latched when S_AXI_ARVALID is asserted.
if axi_arready = '0' and S_AXI_ARVALID = '1' then
-- Indicates that the slave has accepted the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
-- Send the read data
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both S_AXI_ARVALID and axi_arready are asserted.
-- The slave registers data are available on the axi_rdata bus at this instance.
-- The assertion of axi_rvalid marks the validity of read data on the bus and axi_rresp indicates the status of read transaction.
if axi_arready = '1' then
axi_rdata <= slv_reg_rddata;
end if;
if axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0' then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
end if;
if (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if; -- S_AXI_ARESETN = '1'
end if; -- rising_edge(S_AXI_ACLK)
end process;
-- Alias signals to be used by the user design
slv_reg_rden <= axi_arready;
slv_reg_rdaddr <= axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
----------------------------------
-- Main design functionality
----------------------------------
-- Alias signals
cur_recv <= slv_reg3(3 downto 0);
recv_frame <= cur_recv(0);
recv_cfgl1 <= cur_recv(1);
recv_cfgr1 <= cur_recv(2);
recv_cfgl2 <= cur_recv(3);
out_want_nb <= unsigned(slv_reg6);
-- Main sequential process: write to config registers, implement all synchronous registers
process (S_AXI_ACLK)
variable tmpvar_slv_reg : std_logic_vector(31 downto 0) := (others => '0');
variable tmpvar_slv_reg_mask_we : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(S_AXI_ACLK) then
-- Hold reset active for a certain duration
if reset_counter > 0 then
reset_counter <= reset_counter - 1;
reset_reg <= '1';
else
reset_reg <= '0';
end if;
-- Generate reset
if S_AXI_ARESETN = '0' then
reset_counter <= to_unsigned(RESET_DURATION, reset_counter'length);
reset_reg <= '1';
end if;
-- Default/reset assignments
req_start_recv <= '0';
req_start_send <= '0';
-- Buffers for output registers
out_cur_nb <= out_cur_nb_n;
out_getres <= out_getres_n;
out_gotall <= out_gotall_n;
if reset_reg = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg0(15 downto 0) <= std_logic_vector(to_unsigned(LAYER1_FSIZE, 16));
slv_reg0(31 downto 16) <= std_logic_vector(to_unsigned(LAYER1_FSIZE, 16));
slv_reg1(15 downto 0) <= std_logic_vector(to_unsigned(LAYER1_NBNEU, 16));
slv_reg1(31 downto 16) <= std_logic_vector(to_unsigned(LAYER1_NBNEU, 16));
slv_reg2(15 downto 0) <= std_logic_vector(to_unsigned(LAYER2_NBNEU, 16));
slv_reg2(31 downto 16) <= std_logic_vector(to_unsigned(LAYER2_NBNEU, 16));
slv_reg3(3 downto 0) <= CST_RECV_FRAME;
else
-- Write to register
if slv_reg_wren = '1' then
case slv_reg_wraddr is
when b"0000" =>
-- Slave register 0
-- Frame size. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"0000FFFF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg0 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
-- Slave register 1
-- Number of neurons in first stage. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"0000FFFF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg1 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
-- Slave register 2
-- Number of neurons in second stage. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"0000FFFF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg2 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
-- Slave register 3
-- Misc status & control flags. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"000000FF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg3 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- Detect the clear requests
if slv_reg_wrdata(8) = '1' then
reset_counter <= to_unsigned(RESET_DURATION, reset_counter'length);
reset_reg <= '1';
end if;
when b"0100" =>
-- Slave register 4
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
-- Slave register 5
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
-- Slave register 6
-- Write the number of values the PC wants to read
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
-- Slave register 7
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
-- Slave register 8
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
-- Slave register 9
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
-- Slave register 10
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
-- Slave register 11
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100" =>
-- Slave register 12
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- Start reading data from DDR, 1-clock pulse
req_start_recv <= '1';
when b"1101" =>
-- Slave register 13
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- Start writing data to DDR, 1-clock pulse
req_start_send <= '1';
when b"1110" =>
-- Slave register 14
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111" =>
-- Slave register 15
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
end case; -- Address
end if; -- Write enable
end if; -- Not reset
end if; -- Clock
end process;
-- Combinatorial process - Control signals for output values
process (
reset_reg,
req_start_send,
out_cur_nb, out_want_nb, out_getres, out_gotall,
inst_fifo_2o_out_rdy, inst_wrbuf_in_rdy
)
begin
-- Default values
out_cur_nb_n <= out_cur_nb;
out_getres_n <= out_getres;
out_gotall_n <= out_gotall;
inst_fifo_2o_out_ack <= '0';
inst_wrbuf_in_ack <= '0';
-- Handle reset and when functionality is disabled
if reset_reg = '1' then
out_cur_nb_n <= (others => '0');
out_getres_n <= '0';
out_gotall_n <= '0';
else
if (req_start_send = '1') and (out_want_nb > 0) then
out_getres_n <= '1';
end if;
-- Fill the Write FIFO with data from the NN level 2
if out_getres = '1' then
inst_fifo_2o_out_ack <= inst_wrbuf_in_rdy;
inst_wrbuf_in_ack <= inst_fifo_2o_out_rdy;
if (inst_wrbuf_in_rdy = '1') and (inst_fifo_2o_out_rdy = '1') then
out_cur_nb_n <= out_cur_nb + 1;
end if;
-- Intentionally simplifying the test expression
if out_cur_nb = out_want_nb then
out_getres_n <= '0';
out_gotall_n <= '1';
end if;
end if;
-- Fill the Write FIFO with junk data
if out_gotall = '1' then
inst_wrbuf_in_ack <= '1';
end if;
end if;
end process;
-- Combinatorial process - Read register, it's a big MUX
process(
reset_reg,
-- The address of the register to read
slv_reg_rdaddr,
-- The register contents
slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7,
slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15,
-- Pipeline sensors
inst_rdbuf_in_rdy, inst_rdbuf_in_ack, inst_rdbuf_out_rdy, inst_rdbuf_out_ack, inst_rdbuf_out_cnt,
inst_wrbuf_in_rdy, inst_wrbuf_in_ack, inst_wrbuf_out_rdy, inst_wrbuf_out_ack, inst_wrbuf_out_cnt,
inst_fifo_1r_in_rdy, inst_fifo_1r_in_ack, inst_fifo_1r_out_rdy, inst_fifo_1r_out_ack, inst_fifo_1r_out_cnt,
inst_fifo_r2_in_rdy, inst_fifo_r2_in_ack, inst_fifo_r2_out_rdy, inst_fifo_r2_out_ack, inst_fifo_r2_out_cnt,
inst_fifo_2o_in_rdy, inst_fifo_2o_in_ack, inst_fifo_2o_out_rdy, inst_fifo_2o_out_ack, inst_fifo_2o_out_cnt,
inst_layer1_write_ready, inst_layer1_data_in_ready, inst_layer1_data_in_valid,
inst_layer2_write_ready, inst_layer2_data_in_ready, inst_layer2_data_in_valid,
-- Various counters
out_getres, out_gotall,
-- Master AXI sensors
mymaster_busyw, mymaster_busyr, mymaster_sensor
)
begin
slv_reg_rddata <= (others => '0');
-- Address decoding for reading registers
case slv_reg_rdaddr is
when b"0000" =>
slv_reg_rddata <= slv_reg0;
when b"0001" =>
slv_reg_rddata <= slv_reg1;
when b"0010" =>
slv_reg_rddata <= slv_reg2;
when b"0011" =>
slv_reg_rddata <= slv_reg3;
slv_reg_rddata(8) <= reset_reg;
slv_reg_rddata(9) <= mymaster_busyw;
slv_reg_rddata(10) <= mymaster_busyr;
slv_reg_rddata(11) <= out_getres;
slv_reg_rddata(12) <= out_gotall;
when b"0100" =>
--slv_reg_rddata <= slv_reg4;
slv_reg_rddata <= mymaster_sensor;
when b"0101" =>
--slv_reg_rddata <= slv_reg5;
when b"0110" =>
slv_reg_rddata <= slv_reg6;
when b"0111" =>
--slv_reg_rddata <= slv_reg7;
when b"1000" =>
slv_reg_rddata <= slv_reg8;
-- to pop data from the fifo between l1 and recode
-- THE RECODE CAN NOT POP FIFO FROM THE FIFO
-- slv_reg_rddata <= inst_fifo_1r_out_data;
--slv_reg_rddata <= inst_fifo_r2_out_data;
-- slv_reg_rddata <= inst_rdbuf_out_data;
when b"1001" =>
--slv_reg_rddata <= slv_reg9;
when b"1010" =>
slv_reg_rddata <= slv_reg10;
when b"1011" =>
slv_reg_rddata <= slv_reg11;
when b"1100" =>
slv_reg_rddata <= slv_reg12;
when b"1101" =>
slv_reg_rddata <= slv_reg13;
when b"1110" =>
slv_reg_rddata <= slv_reg14;
-- Read the amount of data still present in the FIFOs
slv_reg_rddata(7 downto 0) <= inst_fifo_1r_out_cnt;
slv_reg_rddata(15 downto 8) <= inst_fifo_r2_out_cnt;
slv_reg_rddata(23 downto 16) <= inst_fifo_2o_out_cnt;
slv_reg_rddata(31 downto 24) <= inst_rdbuf_out_cnt;
when b"1111" =>
slv_reg_rddata <= slv_reg15;
slv_reg_rddata(7 downto 0) <= inst_wrbuf_out_cnt;
-- Read the FIFO sync signals
slv_reg_rddata(12) <= inst_rdbuf_in_rdy;
slv_reg_rddata(13) <= inst_rdbuf_in_ack;
slv_reg_rddata(14) <= inst_rdbuf_out_rdy;
slv_reg_rddata(15) <= inst_rdbuf_out_ack;
slv_reg_rddata(16) <= inst_fifo_1r_in_rdy;
slv_reg_rddata(17) <= inst_fifo_1r_in_ack;
slv_reg_rddata(18) <= inst_fifo_1r_out_rdy;
slv_reg_rddata(19) <= inst_fifo_1r_out_ack;
slv_reg_rddata(20) <= inst_fifo_r2_in_rdy;
slv_reg_rddata(21) <= inst_fifo_r2_in_ack;
slv_reg_rddata(22) <= inst_fifo_r2_out_rdy;
slv_reg_rddata(23) <= inst_fifo_r2_out_ack;
slv_reg_rddata(24) <= inst_fifo_2o_in_rdy;
slv_reg_rddata(25) <= inst_fifo_2o_in_ack;
slv_reg_rddata(26) <= inst_fifo_2o_out_rdy;
slv_reg_rddata(27) <= inst_fifo_2o_out_ack;
slv_reg_rddata(28) <= inst_wrbuf_in_rdy;
slv_reg_rddata(29) <= inst_wrbuf_in_ack;
slv_reg_rddata(30) <= inst_wrbuf_out_rdy;
slv_reg_rddata(31) <= inst_wrbuf_out_ack;
when others =>
slv_reg_rddata <= (others => '0');
end case;
end process;
----------------------------------
-- FIFO to hold data read from DDR
----------------------------------
-- Instantiate the FIFO for the read values
i_rdbuf : circbuf_fast
generic map (
DATAW => 32,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_rdbuf_clear,
fifo_in_data => inst_rdbuf_in_data,
fifo_in_rdy => inst_rdbuf_in_rdy,
fifo_in_ack => inst_rdbuf_in_ack,
fifo_in_cnt => inst_rdbuf_in_cnt,
fifo_out_data => inst_rdbuf_out_data,
fifo_out_rdy => inst_rdbuf_out_rdy,
fifo_out_ack => inst_rdbuf_out_ack,
fifo_out_cnt => inst_rdbuf_out_cnt
);
inst_rdbuf_clear <= reset_reg;
inst_rdbuf_in_data <= mymaster_fifor_data;
-- for the debug
--inst_rdbuf_in_data <= slv_reg9;
inst_rdbuf_in_ack <= mymaster_fifor_en;
-- for the debug
--inst_rdbuf_in_ack <= '1' when ((slv_reg_wraddr = b"1001") and (slv_reg_wren = '1')) else '0';
inst_rdbuf_out_ack <=
(recv_cfgl1 and inst_layer1_write_ready) or
(recv_cfgr1 and inst_recode_write_ready) or
(recv_cfgl2 and inst_layer2_write_ready) or
(recv_frame and inst_layer1_data_in_ready);
-- for debug
--inst_rdbuf_out_ack <= '1' when ((slv_reg_rdaddr = b"1000") and (slv_reg_rden = '1')) else '0';
----------------------------------
-- Instantiation of NN level 1
----------------------------------
i_layer1 : nnlayer
generic map (
-- Parameters for the neurons
WDATA => LAYER1_WDATA,
WWEIGHT => LAYER1_WWEIGHT,
WACCU => LAYER1_WACCU,
-- Parameters for frame and number of neurons
FSIZE => LAYER1_FSIZE,
NBNEU => LAYER1_NBNEU
)
port map (
clk => S_AXI_ACLK,
clear => inst_layer1_clear,
write_mode => inst_layer1_write_mode,
write_data => inst_layer1_write_data,
write_enable => inst_layer1_write_enable,
write_ready => inst_layer1_write_ready,
user_fsize => inst_layer1_user_fsize,
user_nbneu => inst_layer1_user_nbneu,
data_in => inst_layer1_data_in,
data_in_valid => inst_layer1_data_in_valid,
data_in_ready => inst_layer1_data_in_ready,
data_out => inst_layer1_data_out,
data_out_valid => inst_layer1_data_out_valid,
end_of_frame => inst_layer1_end_of_frame,
out_fifo_room => inst_layer1_out_fifo_room
);
-- Set inputs
inst_layer1_clear <= reset_reg;
inst_layer1_write_mode <= recv_cfgl1;
inst_layer1_write_data <= inst_rdbuf_out_data(LAYER1_WDATA-1 downto 0);
inst_layer1_write_enable <= inst_rdbuf_out_rdy and recv_cfgl1;
inst_layer1_user_fsize <= slv_reg0(15 downto 0);
inst_layer1_user_nbneu <= slv_reg1(15 downto 0);
inst_layer1_data_in <= inst_rdbuf_out_data(LAYER1_WDATA-1 downto 0);
-- protection from reading into the 1st FIFO during configuration of others
inst_layer1_data_in_valid <= inst_rdbuf_out_rdy and recv_frame;
inst_layer1_out_fifo_room <= std_logic_vector(resize(unsigned(inst_fifo_1r_in_cnt), 16));
----------------------------------
-- FIFO between level 1 and recode
----------------------------------
i_fifo1r : circbuf_fast
generic map (
DATAW => LAYER1_WACCU,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_fifo_1r_clear,
fifo_in_data => inst_fifo_1r_in_data,
fifo_in_rdy => inst_fifo_1r_in_rdy,
fifo_in_ack => inst_fifo_1r_in_ack,
fifo_in_cnt => inst_fifo_1r_in_cnt,
fifo_out_data => inst_fifo_1r_out_data,
fifo_out_rdy => inst_fifo_1r_out_rdy,
fifo_out_ack => inst_fifo_1r_out_ack,
fifo_out_cnt => inst_fifo_1r_out_cnt
);
-- Set inputs
inst_fifo_1r_clear <= reset_reg;
inst_fifo_1r_in_data <= inst_layer1_data_out;
inst_fifo_1r_in_ack <= inst_layer1_data_out_valid;
inst_fifo_1r_out_ack <= (inst_recode_data_in_ready and recv_frame);
-- For debug, le recode can not read data from this fifo
--inst_fifo_1r_out_ack <= '1' when ((slv_reg_rdaddr = b"1000") and (slv_reg_rden = '1')) else '0';
----------------------------------
-- Recode between levels 1 and 2
----------------------------------
i_recode : recode
generic map (
WDATA => RECODE_WDATA,
WWEIGHT => RECODE_WWEIGHT,
WOUT => RECODE_WOUT,
FSIZE => RECODE_FSIZE
)
port map (
clk => S_AXI_ACLK,
addr_clear => inst_recode_addr_clear,
write_mode => inst_recode_write_mode,
write_data => inst_recode_write_data,
write_enable => inst_recode_write_enable,
write_ready => inst_recode_write_ready,
user_nbneu => inst_recode_user_nbneu,
data_in => inst_recode_data_in,
data_in_valid => inst_recode_data_in_valid,
data_in_ready => inst_recode_data_in_ready,
data_out => inst_recode_data_out,
data_out_valid => inst_recode_data_out_valid,
out_fifo_room => inst_recode_out_fifo_room
);
-- Set inputs
inst_recode_addr_clear <= reset_reg;
inst_recode_write_mode <= recv_cfgr1;
inst_recode_write_data <= inst_rdbuf_out_data;
inst_recode_write_enable <= inst_rdbuf_out_rdy and recv_cfgr1;
inst_recode_user_nbneu <= slv_reg1(15 downto 0);
inst_recode_data_in <= inst_fifo_1r_out_data;
inst_recode_data_in_valid <= inst_fifo_1r_out_rdy and recv_frame;
inst_recode_out_fifo_room <= std_logic_vector(resize(unsigned(inst_fifo_r2_in_cnt), 16));
----------------------------------
-- FIFO between recode and level 2
----------------------------------
i_fifor2 : circbuf_fast
generic map (
DATAW => RECODE_WOUT,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_fifo_r2_clear,
fifo_in_data => inst_fifo_r2_in_data,
fifo_in_rdy => inst_fifo_r2_in_rdy,
fifo_in_ack => inst_fifo_r2_in_ack,
fifo_in_cnt => inst_fifo_r2_in_cnt,
fifo_out_data => inst_fifo_r2_out_data,
fifo_out_rdy => inst_fifo_r2_out_rdy,
fifo_out_ack => inst_fifo_r2_out_ack,
fifo_out_cnt => inst_fifo_r2_out_cnt
);
-- Set inputs
inst_fifo_r2_clear <= reset_reg;
inst_fifo_r2_in_data <= inst_recode_data_out;
inst_fifo_r2_in_ack <= inst_recode_data_out_valid;
inst_fifo_r2_out_ack <= inst_layer2_data_in_ready and recv_frame;
-- for debug
--inst_fifo_r2_out_ack <= '1' when ((slv_reg_rdaddr = b"1000") and (slv_reg_rden = '1')) else '0';
----------------------------------
-- Instantiation of NN level 2
----------------------------------
i_layer2 : nnlayer
generic map (
-- Parameters for the neurons
WDATA => LAYER2_WDATA,
WWEIGHT => LAYER2_WWEIGHT,
WACCU => LAYER2_WACCU,
-- Parameters for frame and number of neurons
FSIZE => LAYER2_FSIZE,
NBNEU => LAYER2_NBNEU
)
port map (
clk => S_AXI_ACLK,
clear => inst_layer2_clear,
write_mode => inst_layer2_write_mode,
write_data => inst_layer2_write_data,
write_enable => inst_layer2_write_enable,
write_ready => inst_layer2_write_ready,
user_fsize => inst_layer2_user_fsize,
user_nbneu => inst_layer2_user_nbneu,
data_in => inst_layer2_data_in,
data_in_valid => inst_layer2_data_in_valid,
data_in_ready => inst_layer2_data_in_ready,
data_out => inst_layer2_data_out,
data_out_valid => inst_layer2_data_out_valid,
end_of_frame => inst_layer2_end_of_frame,
out_fifo_room => inst_layer2_out_fifo_room
);
-- Set inputs
inst_layer2_clear <= reset_reg;
inst_layer2_write_mode <= recv_cfgl2;
inst_layer2_write_data <= inst_rdbuf_out_data(inst_layer2_write_data'length-1 downto 0);
inst_layer2_write_enable <= inst_rdbuf_out_rdy and recv_cfgl2;
inst_layer2_user_fsize <= slv_reg1(15 downto 0);
inst_layer2_user_nbneu <= slv_reg2(15 downto 0);
inst_layer2_data_in <= inst_fifo_r2_out_data;
inst_layer2_data_in_valid <= inst_fifo_r2_out_rdy and recv_frame;
inst_layer2_out_fifo_room <= std_logic_vector(resize(unsigned(inst_fifo_2o_in_cnt), 16));
----------------------------------
-- FIFO after level 2
----------------------------------
i_fifo2o : circbuf_fast
generic map (
DATAW => LAYER2_WACCU,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_fifo_2o_clear,
fifo_in_data => inst_fifo_2o_in_data,
fifo_in_rdy => inst_fifo_2o_in_rdy,
fifo_in_ack => inst_fifo_2o_in_ack,
fifo_in_cnt => inst_fifo_2o_in_cnt,
fifo_out_data => inst_fifo_2o_out_data,
fifo_out_rdy => inst_fifo_2o_out_rdy,
fifo_out_ack => inst_fifo_2o_out_ack,
fifo_out_cnt => inst_fifo_2o_out_cnt
);
-- Set inputs
inst_fifo_2o_clear <= reset_reg;
inst_fifo_2o_in_data <= inst_layer2_data_out;
inst_fifo_2o_in_ack <= inst_layer2_data_out_valid;
----------------------------------
-- FIFO to write to DDR
----------------------------------
i_wrbuf : circbuf_fast
generic map (
DATAW => 32,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_wrbuf_clear,
fifo_in_data => inst_wrbuf_in_data,
fifo_in_rdy => inst_wrbuf_in_rdy,
fifo_in_ack => inst_wrbuf_in_ack,
fifo_in_cnt => inst_wrbuf_in_cnt,
fifo_out_data => inst_wrbuf_out_data,
fifo_out_rdy => inst_wrbuf_out_rdy,
fifo_out_ack => inst_wrbuf_out_ack,
fifo_out_cnt => inst_wrbuf_out_cnt
);
-- Set inputs
inst_wrbuf_clear <= reset_reg;
inst_wrbuf_in_data <= std_logic_vector(resize(signed(inst_fifo_2o_out_data), 32));
inst_wrbuf_out_ack <= mymaster_fifow_en;
----------------------------------
-- Talk to the Master port
----------------------------------
mymaster_fifow_data <= inst_wrbuf_out_data;
mymaster_fifor_cnt <= std_logic_vector(resize(unsigned(inst_rdbuf_in_cnt), 16));
mymaster_fifow_cnt <= std_logic_vector(resize(unsigned(inst_wrbuf_out_cnt), 16));
mymaster_addr_inr <= slv_reg10;
mymaster_addr_inw <= slv_reg11;
mymaster_burstnb_inr <= slv_reg12;
mymaster_burstnb_inw <= slv_reg13;
mymaster_startr <= req_start_recv;
mymaster_startw <= req_start_send;
end arch_imp;
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_DRP_ILA.vhd
-- /___/ /\ Timestamp : Tue Jun 09 21:47:15 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_DRP_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(69 downto 0);
TRIG0: in std_logic_vector(9 downto 0);
TRIG1: in std_logic_vector(11 downto 0);
TRIG_OUT: out std_logic);
END CSP_DRP_ILA;
ARCHITECTURE CSP_DRP_ILA_a OF CSP_DRP_ILA IS
BEGIN
END CSP_DRP_ILA_a;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (39 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type;
begin
RAM(0)<= "00000000000000000000000000000000";
process (rst,rd,rs1,rs2,dwr,RAM)
begin
if rst = '1' then
RAM <= (others=>"00000000000000000000000000000000");
crs1 <="00000000000000000000000000000000";
crs2 <="00000000000000000000000000000000";
elsif rd /= "000000" then
RAM(conv_integer(rd)) <= dwr;
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
else
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
end if;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00079.P1: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079.P2: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079.P3: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00079: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00079
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00079(ARCH00079)
-- ENT00079_Test_Bench(ARCH00079_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00079 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1 : inout st_arr1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00079.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_1 (st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00079" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00079" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00079" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_arr2 : inout st_arr2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00079.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00079" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00079" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00079" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_arr3 : inout st_arr3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00079.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00079" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00079" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00079" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00079 ;
--
architecture ARCH00079 of ENT00079 is
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_arr1,
counter,
correct,
savtime,
chk_st_arr1
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_arr2,
counter,
correct,
savtime,
chk_st_arr2
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_arr3,
counter,
correct,
savtime,
chk_st_arr3
) ;
end process P3 ;
--
--
end ARCH00079 ;
--
entity ENT00079_Test_Bench is
end ENT00079_Test_Bench ;
--
architecture ARCH00079_Test_Bench of ENT00079_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00079 ( ARCH00079 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00079_Test_Bench ;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- De los puertos A y B, uso el A para escribir y B para leer (uso esta opcion de las 4 posibles de la dual port ram)
entity dual_port_ram is
generic(
data_width : natural := 1;
addr_width : natural := 18
);
port(
clock: in std_logic;
write_enable : in std_logic;
barrido: in std_logic;
addr_A : in std_logic_vector(addr_width-1 downto 0);
addr_B : in std_logic_vector(addr_width-1 downto 0);
data_A : in std_logic_vector(data_width-1 downto 0);
data_B : out std_logic_vector(data_width-1 downto 0)
);
end entity dual_port_ram;
architecture dual_port_ram_arch of dual_port_ram is
--Creo un array donde tengo 2^(addr_width) vectores de largo data_width (posiciones en la memoria).
constant memo_size : natural := 2**(addr_width) -1;
type ram_type is array(0 to memo_size)
of std_logic_vector(data_width-1 downto 0);
signal ram: ram_type := (others => (others => '0'));
signal addr_A_int : integer := 0;
signal addr_B_int : integer := 0;
begin
--Paso a integer los vectores addr_A y addr_B para ubicarme en la posicion de la memoria ram deseada
--y escribir (si clock=1 y write_enable=1) o leer (si clock=1 y write_enable=0)
addr_A_int <= to_integer(unsigned(addr_A));
addr_B_int <= to_integer(unsigned(addr_B));
process(clock, barrido)
begin
-- Reseteo
if (barrido = '1') then
---Ya que addrB sale de la VGA, podríamos escribir 0 en addrB, y en suficiente tiempo se haría el barrido
---ram(addr_B_int) <= (others => '0');
ram <= (others => (others => '0'));
---
data_B <= (others => '0');
elsif (rising_edge(clock)) then
if(write_enable = '1') then
ram(addr_A_int) <= data_A;
end if;
data_B <= ram(addr_B_int);
end if;
end process;
end dual_port_ram_arch;
|
-- SHA256 Hashing Module
-- Kristian Klomsten Skordal <kristian.skordal@wafflemail.net>
-- This module only operates on full 512 bit blocks. Any input data must have
-- been previously padded.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha256_types.all;
use work.sha256_constants.all;
use work.sha256_functions.all;
entity sha256 is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
ready : out std_logic; -- Ready to process the next block
update : in std_logic; -- Start processing the next block
-- Connections to the input buffer; we assume block RAM that presents
-- valid data the cycle after the address has changed:
word_address : out std_logic_vector(3 downto 0); -- Word 0 .. 15
word_input : in std_logic_vector(31 downto 0);
-- Intermediate/final hash values:
hash_output : out std_logic_vector(255 downto 0);
-- Debug port, used in simulation; leave unconnected:
debug_port : out std_logic_vector(31 downto 0)
);
end entity sha256;
architecture behaviour of sha256 is
-- The module's state machine:
type state_type is (IDLE, BUSY, FINAL);
signal state : state_type;
-- The expanded message blocks, W_j:
signal W : expanded_message_block_array;
signal current_w : std_logic_vector(31 downto 0);
-- Final hash values:
signal h0, h1, h2, h3, h4, h5, h6, h7 : std_logic_vector(31 downto 0);
-- Intermediate hash values:
signal a, b, c, d, e, f, g, h : std_logic_vector(31 downto 0);
-- Current iteration:
signal current_iteration : std_logic_vector(5 downto 0);
begin
word_address <= current_iteration(3 downto 0)
when (current_iteration and b"110000") = b"000000"
else (others => '0');
hash_output <= h0 & h1 & h2 & h3 & h4 & h5 & h6 & h7;
ready <= '1' when state = IDLE else '0';
debug_port <= (others => '0'); -- This is currently not used, yay :-)
hasher: process(clk, reset, enable)
begin
if reset = '1' then
reset_intermediate(h0, h1, h2, h3, h4, h5, h6, h7);
current_iteration <= (others => '0');
state <= IDLE;
elsif rising_edge(clk) and enable = '1' then
case state is
when IDLE =>
-- If new data is available, start hashing it:
if update = '1' then
a <= h0;
b <= h1;
c <= h2;
d <= h3;
e <= h4;
f <= h5;
g <= h6;
h <= h7;
current_iteration <= (others => '0');
state <= BUSY;
end if;
when BUSY =>
-- Load a word of data and store it into the expanded message schedule:
W(index(current_iteration)) <= schedule(word_input, W, current_iteration);
-- Run an interation of the compression function:
compress(a, b, c, d, e, f, g, h,
schedule(word_input, W, current_iteration),
constants(index(current_iteration)));
if current_iteration = b"111111" then
state <= FINAL;
else
current_iteration <= std_logic_vector(unsigned(current_iteration) + 1);
end if;
when FINAL =>
h0 <= std_logic_vector(unsigned(a) + unsigned(h0));
h1 <= std_logic_vector(unsigned(b) + unsigned(h1));
h2 <= std_logic_vector(unsigned(c) + unsigned(h2));
h3 <= std_logic_vector(unsigned(d) + unsigned(h3));
h4 <= std_logic_vector(unsigned(e) + unsigned(h4));
h5 <= std_logic_vector(unsigned(f) + unsigned(h5));
h6 <= std_logic_vector(unsigned(g) + unsigned(h6));
h7 <= std_logic_vector(unsigned(h) + unsigned(h7));
state <= IDLE;
end case;
end if;
end process hasher;
end architecture behaviour;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a < b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: macro
-- File: macro.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: some common macro functions
------------------------------------------------------------------------------
-- Version control:
-- 29-11-1997: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.iface.all;
package macro is
constant zero32 : std_Logic_vector(31 downto 0) := (others => '0');
function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_logic;
function xorv(d : std_logic_vector) return std_logic;
function orv(d : std_logic_vector) return std_logic;
end;
package body macro is
-- generic decoder
function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
res := (others => '0');
-- pragma translate_off
i := 0;
if not is_x(v) then
-- pragma translate_on
i := conv_integer(unsigned(v));
res(i) := '1';
-- pragma translate_off
else
res := (others => 'X');
end if;
-- pragma translate_on
return(res);
end;
-- generic multiplexer
function genmux(s,v : std_logic_vector) return std_logic is
variable res : std_logic_vector(v'length-1 downto 0); --'
variable i : integer;
begin
res := v;
-- pragma translate_off
i := 0;
if not is_x(s) then
-- pragma translate_on
i := conv_integer(unsigned(s));
-- pragma translate_off
else
res := (others => 'X');
end if;
-- pragma translate_on
return(res(i));
end;
-- vector XOR
function xorv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in d'range loop tmp := tmp xor d(i); end loop; --'
return(tmp);
end;
-- vector OR
function orv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in d'range loop tmp := tmp or d(i); end loop; --'
return(tmp);
end;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: macro
-- File: macro.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: some common macro functions
------------------------------------------------------------------------------
-- Version control:
-- 29-11-1997: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.iface.all;
package macro is
constant zero32 : std_Logic_vector(31 downto 0) := (others => '0');
function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_logic;
function xorv(d : std_logic_vector) return std_logic;
function orv(d : std_logic_vector) return std_logic;
end;
package body macro is
-- generic decoder
function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
res := (others => '0');
-- pragma translate_off
i := 0;
if not is_x(v) then
-- pragma translate_on
i := conv_integer(unsigned(v));
res(i) := '1';
-- pragma translate_off
else
res := (others => 'X');
end if;
-- pragma translate_on
return(res);
end;
-- generic multiplexer
function genmux(s,v : std_logic_vector) return std_logic is
variable res : std_logic_vector(v'length-1 downto 0); --'
variable i : integer;
begin
res := v;
-- pragma translate_off
i := 0;
if not is_x(s) then
-- pragma translate_on
i := conv_integer(unsigned(s));
-- pragma translate_off
else
res := (others => 'X');
end if;
-- pragma translate_on
return(res(i));
end;
-- vector XOR
function xorv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in d'range loop tmp := tmp xor d(i); end loop; --'
return(tmp);
end;
-- vector OR
function orv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in d'range loop tmp := tmp or d(i); end loop; --'
return(tmp);
end;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: macro
-- File: macro.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: some common macro functions
------------------------------------------------------------------------------
-- Version control:
-- 29-11-1997: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.iface.all;
package macro is
constant zero32 : std_Logic_vector(31 downto 0) := (others => '0');
function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_logic;
function xorv(d : std_logic_vector) return std_logic;
function orv(d : std_logic_vector) return std_logic;
end;
package body macro is
-- generic decoder
function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
res := (others => '0');
-- pragma translate_off
i := 0;
if not is_x(v) then
-- pragma translate_on
i := conv_integer(unsigned(v));
res(i) := '1';
-- pragma translate_off
else
res := (others => 'X');
end if;
-- pragma translate_on
return(res);
end;
-- generic multiplexer
function genmux(s,v : std_logic_vector) return std_logic is
variable res : std_logic_vector(v'length-1 downto 0); --'
variable i : integer;
begin
res := v;
-- pragma translate_off
i := 0;
if not is_x(s) then
-- pragma translate_on
i := conv_integer(unsigned(s));
-- pragma translate_off
else
res := (others => 'X');
end if;
-- pragma translate_on
return(res(i));
end;
-- vector XOR
function xorv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in d'range loop tmp := tmp xor d(i); end loop; --'
return(tmp);
end;
-- vector OR
function orv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
tmp := '0';
for i in d'range loop tmp := tmp or d(i); end loop; --'
return(tmp);
end;
end;
|
architecture RTL of ENTITY1 is
begin
-- This should pass
LABEL1 : process is
begin
end process LABEL1;
-- This should fail
process is
begin
end process;
-- This should fail
process is
begin
end process;
-- This should pass
LABEL1 : process is
begin
end process LABEL1;
-- This should fail
process is
begin
end process;
-- This should fail
process is
begin
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1694.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01694ent IS
END c09s02b00x00p03n01i01694ent;
ARCHITECTURE c09s02b00x00p03n01i01694arch OF c09s02b00x00p03n01i01694ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Configuration specification.
for all : TEST use entity TEST( TEST_BEHAVIOR );
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01694 - Configuration specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01694arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1694.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01694ent IS
END c09s02b00x00p03n01i01694ent;
ARCHITECTURE c09s02b00x00p03n01i01694arch OF c09s02b00x00p03n01i01694ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Configuration specification.
for all : TEST use entity TEST( TEST_BEHAVIOR );
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01694 - Configuration specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01694arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1694.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01694ent IS
END c09s02b00x00p03n01i01694ent;
ARCHITECTURE c09s02b00x00p03n01i01694arch OF c09s02b00x00p03n01i01694ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Configuration specification.
for all : TEST use entity TEST( TEST_BEHAVIOR );
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01694 - Configuration specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01694arch;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_9_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_9_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_9_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_9_e
--
entity inst_shadow_9_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_9_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_9_e
end inst_shadow_9_e;
--
-- End of Generated Entity inst_shadow_9_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1352.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01352ent IS
END c08s05b00x00p02n01i01352ent;
ARCHITECTURE c08s05b00x00p02n01i01352arch OF c08s05b00x00p02n01i01352ent IS
BEGIN
TESTING: PROCESS
BEGIN
(0, 0, 0) := (0, 0, 0);
assert FALSE
report "***FAILED TEST: c08s05b00x00p02n01i01352 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01352arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1352.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01352ent IS
END c08s05b00x00p02n01i01352ent;
ARCHITECTURE c08s05b00x00p02n01i01352arch OF c08s05b00x00p02n01i01352ent IS
BEGIN
TESTING: PROCESS
BEGIN
(0, 0, 0) := (0, 0, 0);
assert FALSE
report "***FAILED TEST: c08s05b00x00p02n01i01352 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01352arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1352.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01352ent IS
END c08s05b00x00p02n01i01352ent;
ARCHITECTURE c08s05b00x00p02n01i01352arch OF c08s05b00x00p02n01i01352ent IS
BEGIN
TESTING: PROCESS
BEGIN
(0, 0, 0) := (0, 0, 0);
assert FALSE
report "***FAILED TEST: c08s05b00x00p02n01i01352 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01352arch;
|
-------------------------------------------------------------------------------
--
-- Title : ctrl_led8x8_heart
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : kapitanov@insys.ru
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Controller for LED Matrix
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ctrl_led8x8_heart is
port (
clk : in std_logic; --! clock
rst : in std_logic; --! reset
rst_reg : in std_logic; --! count reset
ch_freq : in std_logic; --! change frequency
led_y : out std_logic_vector(7 downto 0); --! LED Y
led_x : out std_logic_vector(7 downto 0) --! LED X
);
end ctrl_led8x8_heart;
architecture ctr_led8x8 of ctrl_led8x8_heart is
constant Nled : integer:=12; -- 12
signal cnt_led : std_logic_vector(Nled downto 0);
signal cnt_cmd : std_logic_vector(2 downto 0);
signal led_cmd : std_logic_vector(3 downto 0);
signal data_led : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(7 downto 0);
signal ch_freqz : std_logic;
signal ch_freqx : std_logic;
signal case_cnt : std_logic_vector(1 downto 0);
begin
ch_freqz <= ch_freq after 1 ns when rising_edge(clk);
ch_freqx <= ch_freq and not ch_freqz when rising_edge(clk);
led_y <= data_led;
led_x <= en_xhdl;
pr_case: process(clk, rst) is
begin
if rst = '0' then
case_cnt <= (others => '0');
elsif rising_edge(clk) then
-- if rst_reg = '0' then
-- case_cnt <= (others => '0');
-- elsif ch_freqx = '1' then
-- case_cnt <= case_cnt + '1';
-- else
-- null;
-- end if;
if ch_freqx = '1' then
case_cnt <= case_cnt + '1';
else
null;
end if;
end if;
end process;
pr_cnt: process(clk, rst) is
begin
if rst = '0' then
cnt_led <= (others => '0');
elsif rising_edge(clk) then
if rst_reg = '0' then
cnt_led <= (others => '0');
else
case case_cnt is
when "00" => cnt_led <= cnt_led + '1';
when "01" => cnt_led <= cnt_led + "10";
when "10" => cnt_led <= cnt_led + "11";
when others => cnt_led <= cnt_led + "100";
end case;
end if;
end if;
end process;
cnt_cmd <= cnt_led(Nled downto Nled-2);
pr_3x8: process(cnt_cmd) is
begin
case cnt_cmd is
when "000" => en_xhdl <= "11111110";
when "001" => en_xhdl <= "11111101";
when "010" => en_xhdl <= "11111011";
when "011" => en_xhdl <= "11110111";
when "100" => en_xhdl <= "11101111";
when "101" => en_xhdl <= "11011111";
when "110" => en_xhdl <= "10111111";
when "111" => en_xhdl <= "01111111";
when others => en_xhdl <= "11111110";
end case;
end process;
pr_8x4: process(en_xhdl) is
begin
case en_xhdl is
when "11111110" => led_cmd <= "0000";
when "11111101" => led_cmd <= "0001";
when "11111011" => led_cmd <= "0010";
when "11110111" => led_cmd <= "0011";
when "11101111" => led_cmd <= "0100";
when "11011111" => led_cmd <= "0101";
when "10111111" => led_cmd <= "0110";
when "01111111" => led_cmd <= "0111";
when others => led_cmd <= "1000";
end case;
end process;
pr_4x8: process(led_cmd) is
begin
case led_cmd is
when "0000" =>
data_led <= "11111111";
when "0001" =>
data_led <= "11100111";
when "0010" =>
data_led <= "11011011";
when "0011" =>
data_led <= "10111101";
when "0100" =>
data_led <= "01111110";
when "0101" =>
data_led <= "01100110";
when "0110" =>
data_led <= "10011001";
when "0111" =>
data_led <= "11111111";
when others =>
data_led <= "11111111";
end case;
end process;
end ctr_led8x8; |
-- quadrature_decoder - quadrature decoder with synchronizing clock input
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
-- prior debouncing of rotary input is unnecessary
entity quadrature_decoder is
port (
clock : in std_logic;
rotary : in std_logic_vector (1 downto 0);
direction : out std_logic;
pulse : out std_logic
);
end quadrature_decoder;
architecture rtl of quadrature_decoder is
signal a, b, c : std_logic;
signal pul, dir : std_logic;
begin
a <= rotary(0);
b <= rotary(1);
c <= a xor b;
dir <= b when rising_edge(clock) and c = '1' else dir;
pul <= a when rising_edge(clock) and c = '0' else pul;
pulse <= pul;
direction <= dir;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1577.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01577ent IS
END c08s10b00x00p04n01i01577ent;
ARCHITECTURE c08s10b00x00p04n01i01577arch OF c08s10b00x00p04n01i01577ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
next when 5.0;
end loop;
assert FALSE
report "***FAILED TEST: c08s10b00x00p04n01i01577 - The condition in a next statement has to be of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01577arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1577.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01577ent IS
END c08s10b00x00p04n01i01577ent;
ARCHITECTURE c08s10b00x00p04n01i01577arch OF c08s10b00x00p04n01i01577ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
next when 5.0;
end loop;
assert FALSE
report "***FAILED TEST: c08s10b00x00p04n01i01577 - The condition in a next statement has to be of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01577arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1577.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01577ent IS
END c08s10b00x00p04n01i01577ent;
ARCHITECTURE c08s10b00x00p04n01i01577arch OF c08s10b00x00p04n01i01577ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
next when 5.0;
end loop;
assert FALSE
report "***FAILED TEST: c08s10b00x00p04n01i01577 - The condition in a next statement has to be of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01577arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: test_image_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY test_image_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE test_image_synth_ARCH OF test_image_synth IS
COMPONENT test_image_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: test_image_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
Library ieee;
use ieee.std_logic_1164.all;
entity seconda is
port(
A: buffer std_logic;
B: buffer std_logic;
C: buffer std_logic;
CLK: IN std_logic
);
end seconda;
architecture impl of seconda is
signal buf: std_logic_vector(2 downto 0);
begin
Task:process(CLK)
begin
if rising_edge(CLK) then
A <= not(A and not (not B and not C));
B <= not(not(B and not C) and not(A and not C));
C <= not(not(not A and C) and not(not A and B) and not(B and C));
--(A, B, C) <= buf;
end if;
end process Task;
end impl; |
---------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : simple filebased model for GP-In, Switches & Pushbuttons
-- Last update : 27.04.2015
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity io_model is
generic(
-- file containing static bit-settings for io's
FILE_NAME_SET : string := "io.txt"
);
port(
-- io's
gpio : inout std_logic_vector(15 downto 0);
switch : out std_ulogic_vector(17 downto 0);
key : out std_ulogic_vector(2 downto 0)
);
end io_model;
architecture sim of io_model is
-- file containing static bit-settings for io's
-- order of bits: gp_in(0) ... gp_in(15), switch(0) ... switch(17), key_n(0) ... key_n(2)
file file_set : text open read_mode is FILE_NAME_SET;
begin
process
variable active_line : line;
variable neol : boolean := false;
variable char_value : character := '0';
variable cnt : natural := 0;
begin
-- preset io's
switch <= (others => 'U');
key <= (others => 'U');
-- read bit-settings file
while not endfile(file_set) loop
-- read line
readline(file_set, active_line);
-- loop until end of line
loop
-- read integer from line
read(active_line, char_value, neol);
-- exit when line has ended
exit when not neol;
-- chancel when enough data is read
exit when cnt = 16 + 18 + 3;
-- write data to output
if cnt < 16 then
-- gpio
if char_value = '1' then
gpio(cnt) <= '1';
elsif char_value = '0' then
gpio(cnt) <= '0';
elsif char_value = 'Z' then
gpio(cnt) <= 'Z';
else
gpio(cnt) <= 'U';
end if;
elsif cnt < 16 + 18 then
-- switch
if char_value = '1' then
switch(cnt-16) <= '1';
elsif char_value = '0' then
switch(cnt-16) <= '0';
else
switch(cnt-16) <= 'U';
end if;
else
-- key
if char_value = '1' then
key(cnt-16-18) <= '1';
elsif char_value = '0' then
key(cnt-16-18) <= '0';
else
key(cnt-16-18) <= 'U';
end if;
end if;
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_set);
wait;
end process;
end sim;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_command_send_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_command_send_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pcie_command_send_fifo_top_wrapper;
architecture xilinx of pcie_command_send_fifo_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_command_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pcie_command_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:03:31 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
s_splice_1 : out std_ulogic_vector(3 downto 0);
s_splice_2 : out std_ulogic_vector(2 downto 0);
s_splice_3 : out std_ulogic_vector(15 downto 0);
s_splice_4 : out std_ulogic_vector(15 downto 0);
s_splice_5 : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_splice_1 : in std_ulogic_vector(3 downto 0); -- Splice signal connector up 1, 1Splice signal connector up 1, 0Splice signal connector up 1, 2S...
p_splice_2 : in std_ulogic_vector(2 downto 0); -- Splice signal connector up 2, 1Splice signal connector up 2, 0Splice signal connector up 2, 2
p_splice_3 : in std_ulogic_vector(15 downto 0); -- Splice signal connector up 3, 14Splice signal connector up 3, 3Splice signal connector up 3, 6...
p_splice_4 : in std_ulogic_vector(15 downto 0); -- Splice signal connector up, joined 4, 0
p_splice_5 : in std_ulogic_vector(7 downto 0) -- Splice signal connector up, joined 5, 0
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_splice_e_s -- splice box
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_e_s
p_mix_s_splice_3_0_go : out std_ulogic;
p_mix_s_splice_3_10_go : out std_ulogic;
p_mix_s_splice_3_11_go : out std_ulogic;
p_mix_s_splice_3_12_go : out std_ulogic;
p_mix_s_splice_3_13_go : out std_ulogic;
p_mix_s_splice_3_14_go : out std_ulogic;
p_mix_s_splice_3_15_go : out std_ulogic;
p_mix_s_splice_3_1_go : out std_ulogic;
p_mix_s_splice_3_2_go : out std_ulogic;
p_mix_s_splice_3_3_go : out std_ulogic;
p_mix_s_splice_3_4_go : out std_ulogic;
p_mix_s_splice_3_5_go : out std_ulogic;
p_mix_s_splice_3_6_go : out std_ulogic;
p_mix_s_splice_3_7_go : out std_ulogic;
p_mix_s_splice_3_8_go : out std_ulogic;
p_mix_s_splice_3_9_go : out std_ulogic;
p_mix_s_splice_3_gi : in std_ulogic_vector(15 downto 0);
p_mix_s_splice_4_gi : in std_ulogic_vector(15 downto 0);
p_mix_s_splice_5_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_splice_join_4_go : out std_ulogic_vector(15 downto 0);
p_mix_s_splice_join_5_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_splice_e_s
);
end component;
-- ---------
component inst_splice_1_0_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_0_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_0 : out std_ulogic -- Splice signal connector up 1, 0
-- End of Generated Port for Entity inst_splice_1_0_e_s
);
end component;
-- ---------
component inst_splice_1_1_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_1_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_1 : out std_ulogic -- Splice signal connector up 1, 1
-- End of Generated Port for Entity inst_splice_1_1_e_s
);
end component;
-- ---------
component inst_splice_1_2_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_2_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_2 : out std_ulogic -- Splice signal connector up 1, 2
-- End of Generated Port for Entity inst_splice_1_2_e_s
);
end component;
-- ---------
component inst_splice_1_3_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_3_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_3 : out std_ulogic -- Splice signal connector up 1, 3
-- End of Generated Port for Entity inst_splice_1_3_e_s
);
end component;
-- ---------
component inst_splice_2_0_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_2_0_e_s
s_splice_2 : in std_ulogic; -- Splice signal connector in: 2, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_2_0 : out std_ulogic -- Splice signal connector up 2, 0
-- End of Generated Port for Entity inst_splice_2_0_e_s
);
end component;
-- ---------
component inst_splice_2_1_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_2_1_e_s
s_splice_2 : in std_ulogic; -- Splice signal connector in: 2, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_2_1 : out std_ulogic -- Splice signal connector up 2, 1
-- End of Generated Port for Entity inst_splice_2_1_e_s
);
end component;
-- ---------
component inst_splice_2_2_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_2_2_e_s
s_splice_2 : in std_ulogic; -- Splice signal connector in: 2, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_2_2 : out std_ulogic -- Splice signal connector up 2, 2
-- End of Generated Port for Entity inst_splice_2_2_e_s
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_splice_1 : std_ulogic_vector(3 downto 0);
signal s_splice_1_0 : std_ulogic;
signal s_splice_1_1 : std_ulogic;
signal s_splice_1_2 : std_ulogic;
signal s_splice_1_3 : std_ulogic;
signal s_splice_2 : std_ulogic_vector(2 downto 0);
signal s_splice_2_0 : std_ulogic;
signal s_splice_2_1 : std_ulogic;
signal s_splice_2_2 : std_ulogic;
signal s_splice_3 : std_ulogic_vector(15 downto 0);
signal s_splice_3_0 : std_ulogic;
signal s_splice_3_1 : std_ulogic;
signal s_splice_3_10 : std_ulogic;
signal s_splice_3_11 : std_ulogic;
signal s_splice_3_12 : std_ulogic;
signal s_splice_3_13 : std_ulogic;
signal s_splice_3_14 : std_ulogic;
signal s_splice_3_15 : std_ulogic;
signal s_splice_3_2 : std_ulogic;
signal s_splice_3_3 : std_ulogic;
signal s_splice_3_4 : std_ulogic;
signal s_splice_3_5 : std_ulogic;
signal s_splice_3_6 : std_ulogic;
signal s_splice_3_7 : std_ulogic;
signal s_splice_3_8 : std_ulogic;
signal s_splice_3_9 : std_ulogic;
signal s_splice_4 : std_ulogic_vector(15 downto 0);
signal s_splice_5 : std_ulogic_vector(7 downto 0);
signal s_splice_join_4 : std_ulogic_vector(15 downto 0);
signal s_splice_join_5 : std_ulogic_vector(7 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
s_splice_1 => s_splice_1, -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_2 => s_splice_2, -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_3 => s_splice_3, -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_4 => s_splice_4, -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
s_splice_5 => s_splice_5 -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
p_splice_1(0) => s_splice_1_0, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 0
p_splice_1(1) => s_splice_1_1, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 1
p_splice_1(2) => s_splice_1_2, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 2
p_splice_1(3) => s_splice_1_3, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 3
p_splice_2(0) => s_splice_2_0, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 2, 0
p_splice_2(1) => s_splice_2_1, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 2, 1
p_splice_2(2) => s_splice_2_2, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 2, 2
p_splice_3(0) => s_splice_3_0, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 0
p_splice_3(1) => s_splice_3_1, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 1
p_splice_3(10) => s_splice_3_10, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 10
p_splice_3(11) => s_splice_3_11, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 11
p_splice_3(12) => s_splice_3_12, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 12
p_splice_3(13) => s_splice_3_13, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 13
p_splice_3(14) => s_splice_3_14, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 14
p_splice_3(15) => s_splice_3_15, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 15
p_splice_3(2) => s_splice_3_2, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 2
p_splice_3(3) => s_splice_3_3, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 3
p_splice_3(4) => s_splice_3_4, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 4
p_splice_3(5) => s_splice_3_5, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 5
p_splice_3(6) => s_splice_3_6, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 6
p_splice_3(7) => s_splice_3_7, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 7
p_splice_3(8) => s_splice_3_8, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 8
p_splice_3(9) => s_splice_3_9, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 9
p_splice_4 => s_splice_join_4, -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
p_splice_5 => s_splice_join_5 -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_splice
inst_splice: inst_splice_e_s -- splice box
port map (
p_mix_s_splice_3_0_go => s_splice_3_0, -- Splice signal connector up 3, 0
p_mix_s_splice_3_10_go => s_splice_3_10, -- Splice signal connector up 3, 10
p_mix_s_splice_3_11_go => s_splice_3_11, -- Splice signal connector up 3, 11
p_mix_s_splice_3_12_go => s_splice_3_12, -- Splice signal connector up 3, 12
p_mix_s_splice_3_13_go => s_splice_3_13, -- Splice signal connector up 3, 13
p_mix_s_splice_3_14_go => s_splice_3_14, -- Splice signal connector up 3, 14
p_mix_s_splice_3_15_go => s_splice_3_15, -- Splice signal connector up 3, 15
p_mix_s_splice_3_1_go => s_splice_3_1, -- Splice signal connector up 3, 1
p_mix_s_splice_3_2_go => s_splice_3_2, -- Splice signal connector up 3, 2
p_mix_s_splice_3_3_go => s_splice_3_3, -- Splice signal connector up 3, 3
p_mix_s_splice_3_4_go => s_splice_3_4, -- Splice signal connector up 3, 4
p_mix_s_splice_3_5_go => s_splice_3_5, -- Splice signal connector up 3, 5
p_mix_s_splice_3_6_go => s_splice_3_6, -- Splice signal connector up 3, 6
p_mix_s_splice_3_7_go => s_splice_3_7, -- Splice signal connector up 3, 7
p_mix_s_splice_3_8_go => s_splice_3_8, -- Splice signal connector up 3, 8
p_mix_s_splice_3_9_go => s_splice_3_9, -- Splice signal connector up 3, 9
p_mix_s_splice_3_gi => s_splice_3, -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
p_mix_s_splice_4_gi => s_splice_4, -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
p_mix_s_splice_5_gi => s_splice_5, -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
p_mix_s_splice_join_4_go => s_splice_join_4, -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
p_mix_s_splice_join_5_go => s_splice_join_5 -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
);
-- End of Generated Instance Port Map for inst_splice
-- Generated Instance Port Map for inst_splice_1_0
inst_splice_1_0: inst_splice_1_0_e_s
port map (
s_splice_1 => s_splice_1(0), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_0 => s_splice_1_0 -- Splice signal connector up 1, 0
);
-- End of Generated Instance Port Map for inst_splice_1_0
-- Generated Instance Port Map for inst_splice_1_1
inst_splice_1_1: inst_splice_1_1_e_s
port map (
s_splice_1 => s_splice_1(1), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_1 => s_splice_1_1 -- Splice signal connector up 1, 1
);
-- End of Generated Instance Port Map for inst_splice_1_1
-- Generated Instance Port Map for inst_splice_1_2
inst_splice_1_2: inst_splice_1_2_e_s
port map (
s_splice_1 => s_splice_1(2), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_2 => s_splice_1_2 -- Splice signal connector up 1, 2
);
-- End of Generated Instance Port Map for inst_splice_1_2
-- Generated Instance Port Map for inst_splice_1_3
inst_splice_1_3: inst_splice_1_3_e_s
port map (
s_splice_1 => s_splice_1(3), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_3 => s_splice_1_3 -- Splice signal connector up 1, 3
);
-- End of Generated Instance Port Map for inst_splice_1_3
-- Generated Instance Port Map for inst_splice_2_0
inst_splice_2_0: inst_splice_2_0_e_s
port map (
s_splice_2 => s_splice_2(0), -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_2_0 => s_splice_2_0 -- Splice signal connector up 2, 0
);
-- End of Generated Instance Port Map for inst_splice_2_0
-- Generated Instance Port Map for inst_splice_2_1
inst_splice_2_1: inst_splice_2_1_e_s
port map (
s_splice_2 => s_splice_2(1), -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_2_1 => s_splice_2_1 -- Splice signal connector up 2, 1
);
-- End of Generated Instance Port Map for inst_splice_2_1
-- Generated Instance Port Map for inst_splice_2_2
inst_splice_2_2: inst_splice_2_2_e_s
port map (
s_splice_2 => s_splice_2(2), -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_2_2 => s_splice_2_2 -- Splice signal connector up 2, 2
);
-- End of Generated Instance Port Map for inst_splice_2_2
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
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