content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------------------------
-- Testbench for the tstfir4 function of the zunit
--
-- Project :
-- File : tb_tstfir4.vhd
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created ... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_PCSOURCE_tb IS
END MUX_PCSOURCE_tb;
ARCHITECTURE behavior OF MUX_PCSOURCE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_PCSOURCE
PORT(
PCdisp30 : IN std_logic_vector(31 downto 0);
PCSE... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ddrv4
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-con... |
-------------------------------------------------------------------------------
-- mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_lo... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:56)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
... |
-- Enum literals should be made implicitly visible here
use work.pkg.alias_t;
package pkg2 is
-- Fails with no declaration for "alpha"
constant c : alias_t := alpha;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gr is
port(clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(31 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(31 downto 0);
GR0_Vie... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
library plb_hwti_v1_00_a;
---------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tmp is end entity;
architecture arch of tmp is
subtype nat2 is natural range 0 to 3;
signal b : bit;
begin
with 2 select b <=
'0' when 0 to 2,
'1' when 2 to 3;
end architecture;
|
entity tmp is end entity;
architecture arch of tmp is
subtype nat2 is natural range 0 to 3;
signal b : bit;
begin
with 2 select b <=
'0' when 0 to 2,
'1' when 2 to 3;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Altera
--
--... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Altera
--
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------
--------------ENTITY---------------
-----------------------------------
entity audiostp is
port (
sclk, fsync, sdata : in std_logic; -- Eingänge definieren
left, right : out signed (17 downto 0); ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
--
-- $Id: t400_pack-p.vhd,v 1.4 2008-05-01 19:51:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
l... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPo... |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPo... |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPo... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_credit_based_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY STD;
USE STD.textio.ALL;
USE ieee.numeric_std.ALL;
-- 16-bit Adder
ENTITY Adder IS
PORT (
A, B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
flag : OUT STD_LOGIC
);
END Adder;
ARCHITECTU... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
generic(
BITS : positive;
ZEROS : unsigned(BITS - 1 downto 0) := (others => '0'));
port(
min : in u_unsigned(BITS - 1 downto 0) := ZEROS);
end entity;
architecture rtl of test is
begin
process
variable sum : ... |
-------------------------------------------------------------------------------
--
-- Title : IF_ID_Register
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogen... |
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_TB IS --entity of the testbench is always empty
END ALU_TB;
ARCHITECTURE testbench OF ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
component ALU is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : in STD_LOGIC... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_1x4 is
Port ( Selector : in STD_LOGIC;
input_A, input_B: in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end Multiplexer_1x4;
architecture skeleton of Multiplexer_1x4 is
begin
with Selector sele... |
--
-- File Name: ScoreBoardGenericPkg.vhd
-- Design Unit Name: ScoreBoardGenericPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis email: jim@synthworks.com
--
--
-- Description:
-- Defines types a... |
-- Twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at y... |
library verilog;
use verilog.vl_types.all;
entity controller_vlg_sample_tst is
port(
clk : in vl_logic;
coin_Detected : in vl_logic;
comp_equal_in : in vl_logic;
comp_greater_in : in vl_logic;
comp_smaller_in : in vl_logic;
reset ... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a cha... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a cha... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a cha... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a cha... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_arbitrator is
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- activ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_arbitrator is
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- activ... |
library ieee;
use ieee.std_logic_1164.all;
entity FAM_tb is
end FAM_tb;
architecture tb of FAM_tb is
component FAM is
port( X, Y, B, Cin : in std_logic;
Sout, Cout : out std_logic);
end component;
signal X, Y, B, Cin, Sout, Cout : std_logic;
begin
mapping: FAM port map(X, Y, B, Cin, S... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.processor_functions.all;
ENTITY ram_infer IS
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (wordlen-1 DOWNTO 0);
write_address: IN integer RANGE 0 to 2**(n-oplen-1);
read_address: IN integer RANGE 0 to 2**(n-oplen-1);
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- basic array declarations
entity test is
end entity test;
architecture test_arch of test is
constant size : integer := 10;
type vector is array (0 to size-1) of integer;
constant c1 : integer := 1;
constant c2 : integer := 2;
constant c3 : integer := 3;
signal x1 : vector := (c1... |
library ieee;
use ieee.std_logic_1164.all;
entity record_test is
port (
o : out integer
);
end record_test;
architecture rtl of record_test is
type t_record is record
int : integer;
end record t_record;
function get_constants(choice : std_logic) return t_record is
variable v_const : t_record... |
library ieee;
use ieee.std_logic_1164.all;
package dbe_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
port
(
clk_i ... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C3 is
port (A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
F: out std_logic_vector(7 downto 0)
);
end C3;
architecture circuito of C3 is
begin
F <= A xor B;
end circuito; |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity Mult is
generic (
wordLengthA : natural := 8;
wordLengthB : natural := 8;
fractionalBitsA : natural := 7;
fractionalBitsB : natural := 7;
wordLengthP : natural := 16;
fractionalBitsP : natural := 7
);
port (
a : in std_l... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
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