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------------------------------------------------------------------------------
-- Testbench for the tstfir4 function of the zunit
--
-- Project :
-- File : tb_tstfir4.vhd
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/15
-- $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
-- $Id: tb_tstfir4.vhd 217 2005-01-13 16:52:03Z plessl $
------------------------------------------------------------------------------
-- This testbench tests the tstfir4 function of the zunit.
--
-- The primary goals of this testbench are:
-- test extension of cell to support 3 inputs (operands)
-- test ternary operators (mux is a ternary operator)
-- test the alu_mux function
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-28 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTFIR4.all;
entity tb_tstfir4 is
end tb_tstfir4;
architecture arch of tb_tstfir4 is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- test vector and expected response
constant COEFS : coeff4array := (1,2,3,1);
constant NDATA : integer := 20; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type fifo_array is array (0 to NDATA-1) of natural;
constant TESTV : fifo_array :=
(1,0,0,1,2,0,0,2,3,0,0,3,1,0,0,1,0,0,0,0);
-- (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
constant EXPRESP : fifo_array :=
(1,2,3,2,4,7,7,4,7,12,11,6,7,11,6,2,2,3,1,0);
-- (1,2,3,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
-- configuration stuff
signal Cfg : engineConfigRec := tstfir4cfg(COEFS);
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstfir4_cfg.h";
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(DATAWIDTH-1 downto 0) <= std_logic_vector(to_unsigned(TESTV(i), DATAWIDTH));
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := std_logic_vector(to_unsigned(EXPRESP(i),DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity note;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Counts a pulse signal using a gate signal that might be asynchronous. Counting
-- is done using a gated counter that runs in the clock domain of the pulse
-- signal. The gate signal is synchronized to the pulse signal. The outputs also
-- belong to the pulse signal´s clock domain.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity SynchronizedGatedCounter is
generic
(
-- The width of the measured frequency or period value.
counter_width: natural := 32
);
port
(
-- The signal to measure the frequency or the period from.
pulse_signal: in std_logic;
-- The gate signal used control the counter. Both edges of this signal
-- are treated as gate events.
toggled_gate_signal: in std_logic;
-- '0' to hold output values, '1' to update them.
update_output: in std_logic;
-- The counted value.
value: out unsigned (counter_width-1 downto 0);
-- '1' if an overflow has occurred in the current counting period.
overflow: out std_logic;
-- Toggles each time a gate event has been successfully detected which
-- indicates that there are proper gate and pulse signals.
toggled_gate_detected: out std_logic
);
end entity;
architecture stdarch of SynchronizedGatedCounter is
-- Internal and registered output values.
type output_reg_type is record
value: unsigned (counter_width-1 downto 0);
overflow: std_logic;
end record;
signal output_state, next_output_state: output_reg_type :=
(
value => (others => '0'),
overflow => '0'
);
-- Miscellaneous control signals.
signal toggled_gate_signal_synced_to_pulse, gate_edge: std_logic := '0';
signal update_output_synced_to_pulse: std_logic := '0';
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- Synchronizes the toggled counter gate signal to the counter pulse signal.
gate_synchronizer: entity Common.Synchronizer
generic map
(
pulse_stretcher => false,
nr_of_stages => 2
)
port map
(
clk => pulse_signal,
in_async => toggled_gate_signal,
out_sync => toggled_gate_signal_synced_to_pulse
);
-- Detects both edges of the toggled gate signal to reconstruct a real gate
-- signal for the counter.
toggling_gate_edge_detector: entity Common.EdgeDetector
generic map
(
detect_rising_edges => true,
detect_falling_edges => true
)
port map
(
clk => pulse_signal,
sigin => toggled_gate_signal_synced_to_pulse,
edge => gate_edge
);
-- Counts a pulse signal with respect to the gate signal. This counter runs in
-- the clock domain of the pulse signal, all in- and output signals belong to
-- the corresponding clock domain.
counter: entity work.GatedCounter
generic map
(
counter_width => counter_width
)
port map
(
pulse_signal => pulse_signal,
gate_signal => gate_edge,
value => next_output_state.value,
overflow => next_output_state.overflow
);
-- Synchronizes the update output signal to the counter pulse signal.
update_output_synchronizer: entity Common.Synchronizer
generic map
(
pulse_stretcher => true,
nr_of_stages => 2
)
port map
(
clk => pulse_signal,
in_async => update_output,
out_sync => update_output_synced_to_pulse
);
--------------------------------------------------------------------------------
-- State and data register.
--------------------------------------------------------------------------------
pulse_state_register: process is
begin
wait until rising_edge(pulse_signal);
if (update_output_synced_to_pulse = '1') then
output_state <= next_output_state;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
value <= output_state.value;
overflow <= output_state.overflow;
toggled_gate_detected <= toggled_gate_signal_synced_to_pulse;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_PCSOURCE_tb IS
END MUX_PCSOURCE_tb;
ARCHITECTURE behavior OF MUX_PCSOURCE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_PCSOURCE
PORT(
PCdisp30 : IN std_logic_vector(31 downto 0);
PCSEUdisp22 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
PCSOURCE : IN std_logic_vector(1 downto 0);
nPC : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal PCdisp30 : std_logic_vector(31 downto 0) := (others => '0');
signal PCSEUdisp22 : std_logic_vector(31 downto 0) := (others => '0');
signal ALURESULT : std_logic_vector(31 downto 0) := (others => '0');
signal PC : std_logic_vector(31 downto 0) := (others => '0');
signal PCSOURCE : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal nPC : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX_PCSOURCE PORT MAP (
PCdisp30 => PCdisp30,
PCSEUdisp22 => PCSEUdisp22,
ALURESULT => ALURESULT,
PC => PC,
PCSOURCE => PCSOURCE,
nPC => nPC
);
-- Stimulus process
stim_proc: process
begin
PCdisp30<="11111111111111111111111111111001";
PCSEUdisp22<="00000000000000000000000000000110";
ALURESULT<="00000000000000000000000000001010";
PC<="00000000000000000000000000001000";
wait for 20 ns;
PCSOURCE<="01";
wait for 20 ns;
PCSOURCE<="10";
wait for 20 ns;
PCSOURCE<="11";
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ddrv4
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-conf-c.vhd,v 1.1 2004/04/06 10:44:19 wig Exp $
-- $Date: 2004/04/06 10:44:19 $
-- $Log: ddrv4-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:44:19 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ddrv4_rtl_conf / ddrv4
--
configuration ddrv4_rtl_conf of ddrv4 is
for rtl
-- Generated Configuration
for d_ls_hr : ddrv
use configuration work.d_ls_hr_RTL_CONF;
end for;
for d_ls_min : ddrv
use configuration work.d_ls_min_RTL_CONF;
end for;
for d_ms_hr : ddrv
use configuration work.d_ms_hr_RTL_CONF;
end for;
for d_ms_min : ddrv
use configuration work.d_ms_min_RTL_CONF;
end for;
for u_and_f : and_f
use configuration work.u_and_f_RTL_CONF;
end for;
end for;
end ddrv4_rtl_conf;
--
-- End of Generated Configuration ddrv4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 4);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 7);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 63);
Sl_addrAck : in std_logic_vector(0 to 4);
Sl_MRdErr : in std_logic_vector(0 to 9);
Sl_MWrErr : in std_logic_vector(0 to 9);
Sl_MBusy : in std_logic_vector(0 to 9);
Sl_rdBTerm : in std_logic_vector(0 to 4);
Sl_rdComp : in std_logic_vector(0 to 4);
Sl_rdDAck : in std_logic_vector(0 to 4);
Sl_rdDBus : in std_logic_vector(0 to 159);
Sl_rdWdAddr : in std_logic_vector(0 to 19);
Sl_rearbitrate : in std_logic_vector(0 to 4);
Sl_SSize : in std_logic_vector(0 to 9);
Sl_wait : in std_logic_vector(0 to 4);
Sl_wrBTerm : in std_logic_vector(0 to 4);
Sl_wrComp : in std_logic_vector(0 to 4);
Sl_wrDAck : in std_logic_vector(0 to 4);
Sl_MIRQ : in std_logic_vector(0 to 9);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 3);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 63);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 4);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 31);
PLB_wrPrim : out std_logic_vector(0 to 4);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 31);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of mb_plb_wrapper : entity is "plb_v46_v1_05_a";
end mb_plb_wrapper;
architecture STRUCTURE of mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 2,
C_PLBV46_NUM_SLAVES => 5,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 32,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "spartan6",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of swled is
-- Flags for display on the 7-seg decimal points
signal flags : std_logic_vector(3 downto 0);
-- Registers implementing the channels
signal checksum, checksum_next : std_logic_vector(15 downto 0) := (others => '0');
signal reg0, reg0_next : std_logic_vector(7 downto 0) := (others => '0');
begin --BEGIN_SNIPPET(registers)
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
reg0 <= (others => '0');
checksum <= (others => '0');
else
reg0 <= reg0_next;
checksum <= checksum_next;
end if;
end if;
end process;
-- Drive register inputs for each channel when the host is writing
reg0_next <=
h2fData_in when chanAddr_in = "0000000" and h2fValid_in = '1'
else reg0;
checksum_next <=
std_logic_vector(unsigned(checksum) + unsigned(h2fData_in))
when chanAddr_in = "0000000" and h2fValid_in = '1'
else h2fData_in & checksum(7 downto 0)
when chanAddr_in = "0000001" and h2fValid_in = '1'
else checksum(15 downto 8) & h2fData_in
when chanAddr_in = "0000010" and h2fValid_in = '1'
else checksum;
-- Select values to return for each channel when the host is reading
with chanAddr_in select f2hData_out <=
sw_in when "0000000",
checksum(15 downto 8) when "0000001",
checksum(7 downto 0) when "0000010",
x"00" when others;
-- Assert that there's always data for reading, and always room for writing
f2hValid_out <= '1';
h2fReady_out <= '1'; --END_SNIPPET(registers)
-- LEDs and 7-seg display
led_out <= reg0;
flags <= "00" & f2hReady_in & reset_in;
seven_seg : entity work.seven_seg
port map(
clk_in => clk_in,
data_in => checksum,
dots_in => flags,
segs_out => sseg_out,
anodes_out => anode_out
);
end architecture;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
package variable_Caos is
constant numBit : integer :=32;
constant Val_init: real:= 0.5;
constant UNO: real:= 1.0;
constant Param: real:= 1.8;
--constant Param: real:= 0.125;
constant Nint: integer := 2;
constant scalamento:integer := numBit-Nint;
function convtosigned (val : real) return std_logic_vector ;
function mult(k : signed;
x : signed
) return integer;
end variable_Caos;
package body variable_Caos is
function convtosigned (val : real) return std_logic_vector is
variable temp : integer;
variable uscita : std_logic_vector(numBit-1 downto 0) := (others=>'0');
begin
temp:=integer(val * real(2**(scalamento)));
if temp = 0 then
for i in 0 to numBit-1 loop
uscita(i) := '0' ;
end loop;
else
for i in 0 to (scalamento) loop
if( (temp -(2**((scalamento)- i))) > 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
elsif( (temp -(2**((scalamento)- i))) = 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
else
uscita((scalamento)- i) := '0' ;
end if;
end loop;
end if;
return uscita;
end function;
function mult(k : signed;
x : signed
) return integer is
variable res: integer;
variable res1: integer;
begin
--if (k(scalamento)= '1') then
-- sott := conv_signed(2**((scalamento)+1),numBit)- k;
-- res := ((2**(scalamento+1)) * conv_integer(x))/(2**(scalamento));
--else
-- sott := conv_signed(2**((scalamento)),numBit)- k;
-- res := ((2**(scalamento)) * conv_integer(x))/(2**(scalamento));
--
--end if;
-- for i in 1 to scalamento loop
-- if(sott((scalamento)-i) = '1')then
-- res := res - ((2**(scalamento-i)) * conv_integer(x))/(2**(scalamento));
-- end if;
-- end loop;
--return res;
--res := (conv_integer(x)/(2**(numBit/2)))*(conv_integer(k)/(2**(numBit/2)));
res := ((2**(numBit-2))/(2**(numBit/2)))* (conv_integer(x)/(2**(numBit/2)));
res1 := (2 * (2**(numBit - Nint - 3)))/( (2**(numBit/2)) ) * (conv_integer(x)/(2**(numBit/2)));
res :=2*res-res1/2;
res := (2**Nint) * res;
--res := (((2**numBit-1)/(2**(numBit/2))) * (conv_integer(x)/(2**(numBit/2))))-(((conv_integer(1/8 * 2**(numBit-1))/(2**(numBit/2))))*(conv_integer(x)/(2**(numBit/2))));
--res := (2**Nint) * res;
--res := res/4;
--res :=(conv_integer(x)*conv_integer(k))/(2**(scalamento));
return res;
end function;
end variable_Caos;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtrace is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TIMEBITS-1 downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
begin
ctrl : process(rst, ahbmi, ahbsi, r, tbo)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable bufdata : std_logic_vector(127 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
bufdata := tbo.data;
hirq := (others => '0'); hirq(irq) := r.bhit;
-- trace buffer index and delay counters
if r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (ahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.haddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.hwrite) or (r.tbreg1.write and r.hwrite)) = '1'))
or ((((r.tbreg2.addr xor r.haddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.hwrite) or (r.tbreg2.write and r.hwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1';
else bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "0000";
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := r.timer;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := r.hwrite;
vabufi.data(78 downto 77) := r.htrans;
vabufi.data(76 downto 74) := r.hsize;
vabufi.data(73 downto 71) := r.hburst;
vabufi.data(70 downto 67) := r.hmaster;
vabufi.data(66) := r.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if r.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi.hwdata;
else
vabufi.data(63 downto 32) := ahbmi.hrdata;
end if;
vabufi.data(31 downto 0) := r.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi.hwdata & ahbsi.hwdata &
ahbsi.hwdata & ahbsi.hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and ahbsi.hready) = '1' then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- save AHB transfer parameters
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr; v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
v.hsize := ahbsi.hsize; v.hburst := ahbsi.hburst;
v.hmaster := ahbsi.hmaster; v.hmastlock := ahbsi.hmastlock;
end if;
if r.hsel = '1' then v.hwdata := ahbsi.hwdata; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex);
v.ahbactive := ahbsi.htrans(1);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.haddr(16) = '0' then -- registers
v.hready := '1';
case r.haddr(4 downto 2) is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd((TIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hwdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
bufdata := tbo.data;
case r.haddr(3 downto 2) is
when "00" =>
v.hwdata := bufdata(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "01" =>
v.hwdata := bufdata(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "10" =>
v.hwdata := bufdata(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when others =>
v.hwdata := bufdata(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
end if;
tbi <= vabufi;
rin <= v;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hrdata <= r.hwdata;
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- mem0 : tbufmem
-- generic map (tech => tech, tbuf => kbytes) port map (clk, tbi, tbo);
enable <= tbi.enable & tbi.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtrace is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TIMEBITS-1 downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
begin
ctrl : process(rst, ahbmi, ahbsi, r, tbo)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable bufdata : std_logic_vector(127 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
bufdata := tbo.data;
hirq := (others => '0'); hirq(irq) := r.bhit;
-- trace buffer index and delay counters
if r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (ahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.haddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.hwrite) or (r.tbreg1.write and r.hwrite)) = '1'))
or ((((r.tbreg2.addr xor r.haddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.hwrite) or (r.tbreg2.write and r.hwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1';
else bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "0000";
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := r.timer;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := r.hwrite;
vabufi.data(78 downto 77) := r.htrans;
vabufi.data(76 downto 74) := r.hsize;
vabufi.data(73 downto 71) := r.hburst;
vabufi.data(70 downto 67) := r.hmaster;
vabufi.data(66) := r.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if r.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi.hwdata;
else
vabufi.data(63 downto 32) := ahbmi.hrdata;
end if;
vabufi.data(31 downto 0) := r.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi.hwdata & ahbsi.hwdata &
ahbsi.hwdata & ahbsi.hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and ahbsi.hready) = '1' then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- save AHB transfer parameters
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr; v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
v.hsize := ahbsi.hsize; v.hburst := ahbsi.hburst;
v.hmaster := ahbsi.hmaster; v.hmastlock := ahbsi.hmastlock;
end if;
if r.hsel = '1' then v.hwdata := ahbsi.hwdata; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex);
v.ahbactive := ahbsi.htrans(1);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.haddr(16) = '0' then -- registers
v.hready := '1';
case r.haddr(4 downto 2) is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd((TIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hwdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
bufdata := tbo.data;
case r.haddr(3 downto 2) is
when "00" =>
v.hwdata := bufdata(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "01" =>
v.hwdata := bufdata(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "10" =>
v.hwdata := bufdata(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when others =>
v.hwdata := bufdata(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
end if;
tbi <= vabufi;
rin <= v;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hrdata <= r.hwdata;
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- mem0 : tbufmem
-- generic map (tech => tech, tbuf => kbytes) port map (clk, tbi, tbo);
enable <= tbi.enable & tbi.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_BIT_VECTOR
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Delayed bidirectional wire
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay_wire is
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end delay_wire;
architecture rtl of delay_wire is
signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
function errinj(a,b: std_logic_vector) return std_logic_vector is
variable r: std_logic_vector(a'length-1 downto 0);
begin
r := a;
for k in a'length-1 downto 0 loop
if (a(k)='0' or a(k)='1') and b(k)='1' then
r(k) := not a(k);
end if;
end loop;
return r;
end;
begin
process(a)
begin
if a'event then
if b_dly = zvector then
a_dly <= transport a after delay_atob*1 ns;
else
a_dly <= (others => 'Z');
end if;
end if;
end process;
process(b)
begin
if b'event then
if a_dly = zvector then
b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
else
b_dly <= (others => 'Z');
end if;
end if;
end process;
a <= b_dly; b <= a_dly;
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
input_V : IN STD_LOGIC_VECTOR (17 downto 0);
res_V : OUT STD_LOGIC_VECTOR (17 downto 0);
res_V_ap_vld : OUT STD_LOGIC );
end;
architecture behav of fir_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir_hw,hls_ip_2015_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc6slx9tqg144-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.490000,HLS_SYN_LAT=770,HLS_SYN_TPT=none,HLS_SYN_MEM=2,HLS_SYN_DSP=0,HLS_SYN_FF=100,HLS_SYN_LUT=259}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv39_0 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
constant ap_const_lv18_1FFFF : STD_LOGIC_VECTOR (17 downto 0) := "011111111111111111";
constant ap_const_lv18_20001 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_25 : BOOLEAN;
signal smpl_V_address0 : STD_LOGIC_VECTOR (6 downto 0);
signal smpl_V_ce0 : STD_LOGIC;
signal smpl_V_we0 : STD_LOGIC;
signal smpl_V_d0 : STD_LOGIC_VECTOR (17 downto 0);
signal smpl_V_q0 : STD_LOGIC_VECTOR (17 downto 0);
signal coeff_hw_V_address0 : STD_LOGIC_VECTOR (6 downto 0);
signal coeff_hw_V_ce0 : STD_LOGIC;
signal coeff_hw_V_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal i_1_fu_183_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_1_reg_525 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_59 : BOOLEAN;
signal exitcond1_fu_177_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_205_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_2_reg_538 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_74 : BOOLEAN;
signal exitcond_fu_199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal qb_assign_1_fu_249_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal qb_assign_1_reg_553 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_94 : BOOLEAN;
signal accu_V_fu_273_p2 : STD_LOGIC_VECTOR (38 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_105 : BOOLEAN;
signal p_Val2_2_fu_300_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal p_Val2_2_reg_573 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal p_38_i_fu_400_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_reg_579 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_reg_584 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_440_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_589 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_142 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_133 : BOOLEAN;
signal p_Val2_s_reg_154 : STD_LOGIC_VECTOR (38 downto 0);
signal i1_reg_166 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_fu_189_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_fu_194_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_1_fu_211_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_154 : BOOLEAN;
signal tmp_14_fu_225_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_fu_235_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal r_fu_229_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_i_i_fu_243_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal qbit_fu_217_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_263_p0 : STD_LOGIC_VECTOR (17 downto 0);
signal grp_fu_263_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_263_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_9_cast_fu_269_p1 : STD_LOGIC_VECTOR (38 downto 0);
signal p_Val2_1_fu_279_p4 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_s_fu_297_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal newsignbit_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_289_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_314_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_334_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_4_fu_350_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal carry_fu_320_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_fu_366_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_326_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal Range2_all_ones_fu_344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_380_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_41_i_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_fu_372_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not_i_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_ones_fu_392_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge40_demorgan_i_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_430_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_5_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge40_i_fu_424_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_fu_446_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_459_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_fu_475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_fu_465_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_2_not_fu_487_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_fu_481_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_fu_493_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_5_mux_fu_499_p3 : STD_LOGIC_VECTOR (17 downto 0);
signal p_Val2_5_fu_506_p3 : STD_LOGIC_VECTOR (17 downto 0);
signal grp_fu_263_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);
component fir_hw_mul_18s_15s_33_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (17 downto 0);
din1 : IN STD_LOGIC_VECTOR (14 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (32 downto 0) );
end component;
component fir_hw_smpl_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (6 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (17 downto 0);
q0 : OUT STD_LOGIC_VECTOR (17 downto 0) );
end component;
component fir_hw_coeff_hw_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (6 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
begin
smpl_V_U : component fir_hw_smpl_V
generic map (
DataWidth => 18,
AddressRange => 128,
AddressWidth => 7)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => smpl_V_address0,
ce0 => smpl_V_ce0,
we0 => smpl_V_we0,
d0 => smpl_V_d0,
q0 => smpl_V_q0);
coeff_hw_V_U : component fir_hw_coeff_hw_V
generic map (
DataWidth => 15,
AddressRange => 128,
AddressWidth => 7)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => coeff_hw_V_address0,
ce0 => coeff_hw_V_ce0,
q0 => coeff_hw_V_q0);
fir_hw_mul_18s_15s_33_3_U0 : component fir_hw_mul_18s_15s_33_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 18,
din1_WIDTH => 15,
dout_WIDTH => 33)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_263_p0,
din1 => grp_fu_263_p1,
ce => grp_fu_263_ce,
dout => grp_fu_263_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i1_reg_166 assign process. --
i1_reg_166_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
i1_reg_166 <= i_2_reg_538;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
i1_reg_166 <= ap_const_lv8_0;
end if;
end if;
end process;
-- i_reg_142 assign process. --
i_reg_142_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
i_reg_142 <= i_1_reg_525;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
i_reg_142 <= ap_const_lv7_0;
end if;
end if;
end process;
-- p_Val2_s_reg_154 assign process. --
p_Val2_s_reg_154_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
p_Val2_s_reg_154 <= accu_V_fu_273_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
p_Val2_s_reg_154 <= ap_const_lv39_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
brmerge_i_reg_584 <= brmerge_i_fu_412_p2;
p_38_i_reg_579 <= p_38_i_fu_400_p2;
p_Val2_2_reg_573 <= p_Val2_2_fu_300_p2;
tmp_10_reg_589 <= tmp_10_fu_440_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_1_reg_525 <= i_1_fu_183_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_2_reg_538 <= i_2_fu_205_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = exitcond_fu_199_p2)))) then
qb_assign_1_reg_553 <= qb_assign_1_fu_249_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond1_fu_177_p2, exitcond_fu_199_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond1_fu_177_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st4_fsm_3 =>
if (not((ap_const_lv1_0 = exitcond_fu_199_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXX";
end case;
end process;
Range1_all_ones_fu_360_p2 <= "1" when (tmp_4_fu_350_p4 = ap_const_lv4_F) else "0";
Range1_all_zeros_fu_366_p2 <= "1" when (tmp_4_fu_350_p4 = ap_const_lv4_0) else "0";
Range2_all_ones_fu_344_p2 <= "1" when (tmp_9_fu_334_p4 = ap_const_lv3_7) else "0";
accu_V_fu_273_p2 <= std_logic_vector(unsigned(p_Val2_s_reg_154) + unsigned(tmp_9_cast_fu_269_p1));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_105 assign process. --
ap_sig_bdd_105_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_133 assign process. --
ap_sig_bdd_133_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_133 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_154 assign process. --
ap_sig_bdd_154_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_154 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_25 assign process. --
ap_sig_bdd_25_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_25 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_59 assign process. --
ap_sig_bdd_59_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_59 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_74 assign process. --
ap_sig_bdd_74_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_94 assign process. --
ap_sig_bdd_94_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_94 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_25)
begin
if (ap_sig_bdd_25) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_59)
begin
if (ap_sig_bdd_59) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_133)
begin
if (ap_sig_bdd_133) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_94)
begin
if (ap_sig_bdd_94) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_105)
begin
if (ap_sig_bdd_105) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_154)
begin
if (ap_sig_bdd_154) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
brmerge40_demorgan_i_fu_418_p2 <= (newsignbit_fu_306_p3 and deleted_ones_fu_392_p3);
brmerge40_i_fu_424_p2 <= (brmerge40_demorgan_i_fu_418_p2 xor ap_const_lv1_1);
brmerge_fu_493_p2 <= (overflow_fu_465_p2 or underflow_2_not_fu_487_p2);
brmerge_i_fu_412_p2 <= (newsignbit_fu_306_p3 or p_not_i_fu_406_p2);
brmerge_i_i_fu_481_p2 <= (underflow_fu_475_p2 or overflow_fu_465_p2);
carry_fu_320_p2 <= (tmp_15_fu_289_p3 and tmp_6_fu_314_p2);
coeff_hw_V_address0 <= tmp_1_fu_211_p1(7 - 1 downto 0);
-- coeff_hw_V_ce0 assign process. --
coeff_hw_V_ce0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
coeff_hw_V_ce0 <= ap_const_logic_1;
else
coeff_hw_V_ce0 <= ap_const_logic_0;
end if;
end process;
deleted_ones_fu_392_p3 <=
p_41_i_fu_386_p2 when (carry_fu_320_p2(0) = '1') else
Range1_all_ones_fu_360_p2;
deleted_zeros_fu_372_p3 <=
Range1_all_ones_fu_360_p2 when (carry_fu_320_p2(0) = '1') else
Range1_all_zeros_fu_366_p2;
exitcond1_fu_177_p2 <= "1" when (i_reg_142 = ap_const_lv7_7F) else "0";
exitcond_fu_199_p2 <= "1" when (i1_reg_166 = ap_const_lv8_80) else "0";
grp_fu_263_ce <= ap_const_logic_1;
grp_fu_263_p0 <= smpl_V_q0;
grp_fu_263_p1 <= coeff_hw_V_q0;
i_1_fu_183_p2 <= std_logic_vector(unsigned(i_reg_142) + unsigned(ap_const_lv7_1));
i_2_fu_205_p2 <= std_logic_vector(unsigned(i1_reg_166) + unsigned(ap_const_lv8_1));
newsignbit_fu_306_p3 <= p_Val2_2_fu_300_p2(17 downto 17);
overflow_fu_465_p2 <= (brmerge_i_reg_584 and tmp_3_fu_459_p2);
p_38_i_fu_400_p2 <= (carry_fu_320_p2 and Range1_all_ones_fu_360_p2);
p_41_i_fu_386_p2 <= (Range2_all_ones_fu_344_p2 and tmp_7_fu_380_p2);
p_Val2_1_fu_279_p4 <= p_Val2_s_reg_154(34 downto 17);
p_Val2_2_fu_300_p2 <= std_logic_vector(unsigned(p_Val2_1_fu_279_p4) + unsigned(tmp_s_fu_297_p1));
p_Val2_5_fu_506_p3 <=
ap_const_lv18_20001 when (underflow_fu_475_p2(0) = '1') else
p_Val2_2_reg_573;
p_Val2_5_mux_fu_499_p3 <=
ap_const_lv18_1FFFF when (brmerge_i_i_fu_481_p2(0) = '1') else
p_Val2_2_reg_573;
p_not_i_fu_406_p2 <= (deleted_zeros_fu_372_p3 xor ap_const_lv1_1);
qb_assign_1_fu_249_p2 <= (r_i_i_fu_243_p2 and qbit_fu_217_p3);
qbit_fu_217_p3 <= p_Val2_s_reg_154(16 downto 16);
r_fu_229_p2 <= "0" when (tmp_14_fu_225_p1 = ap_const_lv16_0) else "1";
r_i_i_fu_243_p2 <= (tmp_16_fu_235_p3 or r_fu_229_p2);
res_V <=
p_Val2_5_mux_fu_499_p3 when (brmerge_fu_493_p2(0) = '1') else
p_Val2_5_fu_506_p3;
-- res_V_ap_vld assign process. --
res_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
res_V_ap_vld <= ap_const_logic_1;
else
res_V_ap_vld <= ap_const_logic_0;
end if;
end process;
signbit_fu_446_p3 <= p_Val2_s_reg_154(38 downto 38);
-- smpl_V_address0 assign process. --
smpl_V_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, tmp_2_fu_189_p1, tmp_fu_194_p1, tmp_1_fu_211_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
smpl_V_address0 <= tmp_fu_194_p1(7 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
smpl_V_address0 <= ap_const_lv7_7F;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
smpl_V_address0 <= tmp_1_fu_211_p1(7 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond1_fu_177_p2 = ap_const_lv1_0))) then
smpl_V_address0 <= tmp_2_fu_189_p1(7 - 1 downto 0);
else
smpl_V_address0 <= "XXXXXXX";
end if;
end process;
-- smpl_V_ce0 assign process. --
smpl_V_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond1_fu_177_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0))))) then
smpl_V_ce0 <= ap_const_logic_1;
else
smpl_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- smpl_V_d0 assign process. --
smpl_V_d0_assign_proc : process(input_V, smpl_V_q0, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st3_fsm_2)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
smpl_V_d0 <= smpl_V_q0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0)))) then
smpl_V_d0 <= input_V;
else
smpl_V_d0 <= "XXXXXXXXXXXXXXXXXX";
end if;
end process;
-- smpl_V_we0 assign process. --
smpl_V_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_177_p2, ap_sig_cseq_ST_st3_fsm_2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_fu_177_p2 = ap_const_lv1_0))))) then
smpl_V_we0 <= ap_const_logic_1;
else
smpl_V_we0 <= ap_const_logic_0;
end if;
end process;
tmp2_fu_470_p2 <= (tmp_10_reg_589 and tmp_8_fu_454_p2);
tmp_10_fu_440_p2 <= (tmp_5_fu_434_p2 or brmerge40_i_fu_424_p2);
tmp_14_fu_225_p1 <= p_Val2_s_reg_154(16 - 1 downto 0);
tmp_15_fu_289_p3 <= p_Val2_s_reg_154(34 downto 34);
tmp_16_fu_235_p3 <= p_Val2_s_reg_154(17 downto 17);
tmp_18_fu_326_p3 <= p_Val2_s_reg_154(35 downto 35);
tmp_19_fu_430_p1 <= p_Val2_2_fu_300_p2(17 - 1 downto 0);
tmp_1_fu_211_p1 <= std_logic_vector(resize(unsigned(i1_reg_166),64));
tmp_2_fu_189_p1 <= std_logic_vector(resize(unsigned(i_1_fu_183_p2),64));
tmp_3_fu_459_p2 <= (signbit_fu_446_p3 xor ap_const_lv1_1);
tmp_4_fu_350_p4 <= p_Val2_s_reg_154(38 downto 35);
tmp_5_fu_434_p2 <= "1" when (tmp_19_fu_430_p1 = ap_const_lv17_0) else "0";
tmp_6_fu_314_p2 <= (newsignbit_fu_306_p3 xor ap_const_lv1_1);
tmp_7_fu_380_p2 <= (tmp_18_fu_326_p3 xor ap_const_lv1_1);
tmp_8_fu_454_p2 <= (p_38_i_reg_579 xor ap_const_lv1_1);
tmp_9_cast_fu_269_p1 <= std_logic_vector(resize(signed(grp_fu_263_p2),39));
tmp_9_fu_334_p4 <= p_Val2_s_reg_154(38 downto 36);
tmp_fu_194_p1 <= std_logic_vector(resize(unsigned(i_reg_142),64));
tmp_s_fu_297_p1 <= std_logic_vector(resize(unsigned(qb_assign_1_reg_553),18));
underflow_2_not_fu_487_p2 <= (underflow_fu_475_p2 xor ap_const_lv1_1);
underflow_fu_475_p2 <= (tmp2_fu_470_p2 and signbit_fu_446_p3);
end behav;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:56)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_hype_entity;
ARCHITECTURE mesahb_hype_description OF mesahb_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "0000000000000000000000000000000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
output1 <= input1 + 1;
register1 := input2 * 2;
WHEN "00000010" =>
register2 := input3 * 3;
register1 := register1 + 5;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + 9;
WHEN "00000100" =>
register2 := register2 * 11;
WHEN "00000101" =>
register3 := input4 * 12;
register2 := register2 + 14;
WHEN "00000110" =>
register2 := ((NOT register2) + 1) XOR register2;
register1 := register3 * register1;
WHEN "00000111" =>
register2 := register2 * 18;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := input5 * 19;
WHEN "00001001" =>
register2 := register2 + 21;
WHEN "00001010" =>
register2 := register2 * 23;
WHEN "00001011" =>
register2 := register2 + 25;
WHEN "00001100" =>
output2 <= register1(0 TO 14) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_hype_description; |
-- Enum literals should be made implicitly visible here
use work.pkg.alias_t;
package pkg2 is
-- Fails with no declaration for "alpha"
constant c : alias_t := alpha;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gr is
port(clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(31 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(31 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(31 downto 0));
end gr;
architecture BEHAVIOR of gr is
signal S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F, S_GR7_F,
S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F, S_GR14_F, S_GR15_F
: std_logic_vector(31 downto 0);
begin
GR0_View <= S_GR0_F; GR1_View <= S_GR1_F; GR2_View <= S_GR2_F; GR3_View <= S_GR3_F;
GR4_View <= S_GR4_F; GR5_View <= S_GR5_F; GR6_View <= S_GR6_F; GR7_View <= S_GR7_F;
GR8_View <= S_GR8_F; GR9_View <= S_GR9_F; GR10_View <= S_GR10_F; GR11_View <= S_GR11_F;
GR12_View <= S_GR12_F; GR13_View <= S_GR13_F; GR14_View <= S_GR14_F; GR15_View <= S_GR15_F;
process(clk) begin
if clk'event and (clk and S_GRlat) = '1' then
case S_ctl_c is
when "0000" => S_GR0_F <= S_BUS_C;
when "0001" => S_GR1_F <= S_BUS_C;
when "0010" => S_GR2_F <= S_BUS_C;
when "0011" => S_GR3_F <= S_BUS_C;
when "0100" => S_GR4_F <= S_BUS_C;
when "0101" => S_GR5_F <= S_BUS_C;
when "0110" => S_GR6_F <= S_BUS_C;
when "0111" => S_GR7_F <= S_BUS_C;
when "1000" => S_GR8_F <= S_BUS_C;
when "1001" => S_GR9_F <= S_BUS_C;
when "1010" => S_GR10_F <= S_BUS_C;
when "1011" => S_GR11_F <= S_BUS_C;
when "1100" => S_GR12_F <= S_BUS_C;
when "1101" => S_GR13_F <= S_BUS_C;
when "1110" => S_GR14_F <= S_BUS_C;
when "1111" => S_GR15_F <= S_BUS_C;
when others => null;
end case;
end if;
end process;
process(S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F,
S_GR7_F, S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F,
S_GR14_F, S_GR15_F, S_ctl_a, S_ctl_b) begin
case S_ctl_a is
when "0000" => S_BUS_A <= S_GR0_F;
when "0001" => S_BUS_A <= S_GR1_F;
when "0010" => S_BUS_A <= S_GR2_F;
when "0011" => S_BUS_A <= S_GR3_F;
when "0100" => S_BUS_A <= S_GR4_F;
when "0101" => S_BUS_A <= S_GR5_F;
when "0110" => S_BUS_A <= S_GR6_F;
when "0111" => S_BUS_A <= S_GR7_F;
when "1000" => S_BUS_A <= S_GR8_F;
when "1001" => S_BUS_A <= S_GR9_F;
when "1010" => S_BUS_A <= S_GR10_F;
when "1011" => S_BUS_A <= S_GR11_F;
when "1100" => S_BUS_A <= S_GR12_F;
when "1101" => S_BUS_A <= S_GR13_F;
when "1110" => S_BUS_A <= S_GR14_F;
when "1111" => S_BUS_A <= S_GR15_F;
when others => null;
end case;
case S_ctl_b is
when "0000" => S_BUS_B <= S_GR0_F;
when "0001" => S_BUS_B <= S_GR1_F;
when "0010" => S_BUS_B <= S_GR2_F;
when "0011" => S_BUS_B <= S_GR3_F;
when "0100" => S_BUS_B <= S_GR4_F;
when "0101" => S_BUS_B <= S_GR5_F;
when "0110" => S_BUS_B <= S_GR6_F;
when "0111" => S_BUS_B <= S_GR7_F;
when "1000" => S_BUS_B <= S_GR8_F;
when "1001" => S_BUS_B <= S_GR9_F;
when "1010" => S_BUS_B <= S_GR10_F;
when "1011" => S_BUS_B <= S_GR11_F;
when "1100" => S_BUS_B <= S_GR12_F;
when "1101" => S_BUS_B <= S_GR13_F;
when "1110" => S_BUS_B <= S_GR14_F;
when "1111" => S_BUS_B <= S_GR15_F;
when others => null;
end case;
end process;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
library plb_hwti_v1_00_a;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AWIDTH -- User logic address bus width
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstNum -- IP to Bus burst size indicator
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
------------------------------------------------------------------------------
entity user_logic is
generic
(
MTX_BITS : natural := 6;
TID_BITS : natural := 8;
CMD_BITS : natural := 3;
MTX_BASE : std_logic_vector := x"75000000";
CDV_BASE : std_logic_vector := x"74000000";
SCH_BASE : std_logic_vector := x"61000000";
MNG_BASE : std_logic_vector := x"60000000";
USR_BASE : std_logic_vector := x"30000000";
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64;
C_NUM_CE : integer := 8
);
port
(
FSL_S_READ : out std_logic;
FSL_S_DATA : in std_logic_vector(0 to 63);
FSL_S_CONTROL : in std_logic;
FSL_S_EXISTS : in std_logic;
FSL_M_WRITE : out std_logic;
FSL_M_DATA : out std_logic_vector(0 to 63);
FSL_M_CONTROL : out std_logic;
FSL_M_FULL : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity user_logic;
architecture behavioral of user_logic is
constant BUS_ADDR : std_logic_vector(0 to C_AWIDTH-1) := USR_BASE(0 to 23) & x"18";
signal tid_data : std_logic_vector(0 to 31);
--signal bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal sta_data : std_logic_vector(0 to 31);
--signal cmd_data : std_logic_vector(0 to C_DWIDTH-1);
signal arg_data : std_logic_vector(0 to 31);
signal res_data : std_logic_vector(0 to 31);
signal mux_data : std_logic_vector(0 to 31);
signal mem_rd : std_logic;
signal mem_wr : std_logic;
signal mem_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mem_res : std_logic_vector(0 to C_DWIDTH-1);
signal mem_ack : std_logic;
signal mem_last : std_logic;
signal mem_err : std_logic;
signal mem_data : std_logic_vector(0 to C_DWIDTH-1);
signal mem_length : std_logic_vector(0 to 23);
signal cmd_wr : std_logic;
signal sta_wr : std_logic;
signal res_wr : std_logic;
signal tid_rdack : std_logic;
signal bus_rdack : std_logic;
signal sta_rdack : std_logic;
--signal cmd_rdack : std_logic;
signal arg_rdack : std_logic;
signal res_rdack : std_logic;
signal tid_wrack : std_logic;
signal bus_wrack : std_logic;
signal sta_wrack : std_logic;
--signal cmd_wrack : std_logic;
signal arg_wrack : std_logic;
--signal res_wrack : std_logic;
signal tid_value : std_logic_vector(0 to 7);
--signal bus_value : std_logic_vector(0 to C_DWIDTH-1);
signal sta_value : std_logic_vector(0 to 7);
--signal cmd_value : std_logic_vector(0 to 3);
signal arg_value : std_logic_vector(0 to 31);
signal res_value : std_logic_vector(0 to 31);
--signal cmd_iwr : std_logic;
--signal sta_iwr : std_logic;
--signal sta_idata : std_logic_vector(0 to C_DWIDTH-1);
--signal cmd_idata : std_logic_vector(0 to C_DWIDTH-1);
signal sta_wdata : std_logic_vector(0 to 31);
signal res_wdata : std_logic_vector(0 to 31);
--signal cmd_wdata : std_logic_vector(0 to C_DWIDTH-1);
alias tid_read : std_logic is Bus2IP_RdCE(0);
alias tmr_read : std_logic is Bus2IP_RdCE(1);
alias sta_read : std_logic is Bus2IP_RdCE(2);
alias cmd_read : std_logic is Bus2IP_RdCE(3);
alias arg_read : std_logic is Bus2IP_RdCE(4);
alias res_read : std_logic is Bus2IP_RdCE(5);
alias bus_read : std_logic is Bus2IP_RdCE(6);
alias tid_write : std_logic is Bus2IP_WrCE(0);
alias tmr_write : std_logic is Bus2IP_WrCE(1);
alias sta_write : std_logic is Bus2IP_WrCE(2);
alias cmd_write : std_logic is Bus2IP_WrCE(3);
alias arg_write : std_logic is Bus2IP_WrCE(4);
alias res_write : std_logic is Bus2IP_WrCE(5);
alias bus_write : std_logic is Bus2IP_WrCE(6);
begin
mux_data <= tid_data or sta_data or arg_data or res_data;
IP2Bus_Data <= (mux_data & x"00000000") or mem_data
when Bus2IP_RdReq='1' else (others => '0');
IP2Bus_WrAck <= tid_wrack or sta_wrack or arg_wrack or res_write or
bus_wrack or cmd_write;
IP2Bus_RdAck <= tid_rdack or sta_rdack or arg_rdack or res_rdack or
bus_rdack or cmd_read;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= Bus2IP_RdReq or Bus2IP_WrReq;
-- Instantiate the Thread ID register as a read/write register
tidreg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => TID_BITS,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => tid_read,
wr => tid_write,
data => Bus2IP_Data(0 to 31),
rdack => tid_rdack,
wrack => tid_wrack,
value => tid_value,
output => tid_data
);
-- Instantiate the Timer register as a read/write register
--busreg : entity hwti_common_v1_00_a.hwtireg
--generic map
--(
-- REG_WIDTH => C_DWIDTH,
-- C_AWIDTH => C_AWIDTH,
-- C_DWIDTH => C_DWIDTH
--)
--port map
--(
-- clk => Bus2IP_Clk,
-- rst => Bus2IP_Reset,
-- rd => bus_read,
-- wr => bus_write,
-- data => Bus2IP_Data,
-- rdack => bus_rdack,
-- wrack => bus_wrack,
-- value => bus_value,
-- output => bus_data
--);
-- Instantiate the Status register as a read/write register
stareg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => 8,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => sta_read,
wr => sta_wr,
data => sta_wdata,
rdack => sta_rdack,
wrack => sta_wrack,
value => sta_value,
output => sta_data
);
-- Make a mux for the command register data and status register data
--cmd_idata <= Bus2IP_Data when cmd_write = '1' else cmd_wdata;
--cmd_iwr <= cmd_wr or cmd_write;
--sta_idata <= Bus2IP_Data when sta_write = '1' else sta_wdata;
--sta_iwr <= sta_wr or sta_write;
-- Instantiate the Command register as a read/write register
--cmdreg : entity hwti_common_v1_00_a.hwtireg
--generic map
--(
-- REG_WIDTH => 4,
-- C_AWIDTH => C_AWIDTH,
-- C_DWIDTH => C_DWIDTH
--)
--port map
--(
-- clk => Bus2IP_Clk,
-- rst => Bus2IP_Reset,
-- rd => cmd_read,
-- wr => cmd_iwr,
-- data => cmd_idata,
-- rdack => cmd_rdack,
-- wrack => cmd_wrack,
-- value => cmd_value,
-- output => cmd_data
--);
-- Instantiate the Argument register as a read/write register
argreg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => 32,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => arg_read,
wr => arg_write,
data => Bus2IP_Data(0 to 31),
rdack => arg_rdack,
wrack => arg_wrack,
value => arg_value,
output => arg_data
);
-- Instantiate the Result register as a read/write register
resreg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => 32,
USE_HIGH => true,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => res_read,
wr => res_wr,
data => res_wdata,
rdack => res_rdack,
wrack => open,
value => res_value,
output => res_data
);
-- Instantiate the memory read/write state machine
imemory : entity plb_hwti_v1_00_a.memory
generic map
(
MEM_ADDR => BUS_ADDR,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => mem_rd,
wr => mem_wr,
addr => mem_addr,
length => mem_length,
ack => mem_ack,
last => mem_last,
Bus2IP_MstError => Bus2IP_MstError,
Bus2IP_MstLastAck => Bus2IP_MstLastAck,
Bus2IP_MstRdAck => Bus2IP_MstRdAck,
Bus2IP_MstWrAck => Bus2IP_MstWrAck,
Bus2IP_MstRetry => Bus2IP_MstRetry,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut,
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
IP2Bus_MstNum => IP2Bus_MstNum,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2IP_Addr => IP2IP_Addr
);
-- Instantiate the command processing state machine
icommand : entity hwti_common_v1_00_a.command
generic map
(
MTX_BITS => MTX_BITS,
TID_BITS => TID_BITS,
CMD_BITS => CMD_BITS,
MTX_BASE => MTX_BASE,
CDV_BASE => CDV_BASE,
SCH_BASE => SCH_BASE,
MNG_BASE => MNG_BASE,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
tid => tid_value,
arg => arg_value,
opcode_read => FSL_S_READ,
opcode_data => FSL_S_DATA,
opcode_control => FSL_S_CONTROL,
opcode_exists => FSL_S_EXISTS,
result_write => FSL_M_WRITE,
result_data => FSL_M_DATA,
result_control => FSL_M_CONTROL,
result_full => FSL_M_FULL,
command => Bus2IP_Data(C_DWIDTH-4 to C_DWIDTH-1),
status => sta_value,
setsta => sta_wr,
outsta => sta_wdata,
setres => res_wr,
outres => res_wdata,
memrd => bus_read,
memwr => bus_write,
memrdack => bus_rdack,
memwrack => bus_wrack,
rd => mem_rd,
wr => mem_wr,
addr => mem_addr,
data => mem_data,
bytes => mem_length,
ack => mem_ack,
last => mem_last,
err => '0',
results => Bus2IP_Data
);
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3154.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03154ent IS
END c05s03b00x00p01n01i03154ent;
ARCHITECTURE c05s03b00x00p01n01i03154arch OF c05s03b00x00p01n01i03154ent IS
-- Define res function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03154"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03154 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03154arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3154.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03154ent IS
END c05s03b00x00p01n01i03154ent;
ARCHITECTURE c05s03b00x00p01n01i03154arch OF c05s03b00x00p01n01i03154ent IS
-- Define res function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03154"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03154 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03154arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3154.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03154ent IS
END c05s03b00x00p01n01i03154ent;
ARCHITECTURE c05s03b00x00p01n01i03154arch OF c05s03b00x00p01n01i03154ent IS
-- Define res function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03154"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03154 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03154arch;
|
entity tmp is end entity;
architecture arch of tmp is
subtype nat2 is natural range 0 to 3;
signal b : bit;
begin
with 2 select b <=
'0' when 0 to 2,
'1' when 2 to 3;
end architecture;
|
entity tmp is end entity;
architecture arch of tmp is
subtype nat2 is natural range 0 to 3;
signal b : bit;
begin
with 2 select b <=
'0' when 0 to 2,
'1' when 2 to 3;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "zed_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_vga_0_0_arch : ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_vga,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "zed_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_vga_0_0_arch : ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_vga,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <kubakici@wp.pl>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Input debouncer and stabilisation circuit
-- use to make sure inputs from buttons don't jump around
entity debouncer is
port (Clk : in std_logic;
Input : in std_logic;
Output : out std_logic);
end debouncer;
-- Operation:
-- There are two stages of input flop-flops followed by a counter
-- signal must stay high for 128 cycles of @Clk to make @Output
-- go high as well.
-- Output goes low as soon as output of second stage (@Input after
-- two clock cycles) goes low.
architecture Behavioral of debouncer is
signal stage_1, stage_2 : std_logic;
signal counter : std_logic_vector(7 downto 0);
begin
Output <= counter(7);
stage_1 <= Input when RISING_EDGE(Clk);
stage_2 <= stage_1 when RISING_EDGE(Clk);
cnt : process (Clk)
begin
if RISING_EDGE(Clk) then
if stage_2 = '1' and counter(7) = '0' then
counter <= counter + 1;
end if;
if stage_2 = '0' then
counter <= ( others => '0' );
end if;
end if;
end process;
end Behavioral;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <kubakici@wp.pl>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Input debouncer and stabilisation circuit
-- use to make sure inputs from buttons don't jump around
entity debouncer is
port (Clk : in std_logic;
Input : in std_logic;
Output : out std_logic);
end debouncer;
-- Operation:
-- There are two stages of input flop-flops followed by a counter
-- signal must stay high for 128 cycles of @Clk to make @Output
-- go high as well.
-- Output goes low as soon as output of second stage (@Input after
-- two clock cycles) goes low.
architecture Behavioral of debouncer is
signal stage_1, stage_2 : std_logic;
signal counter : std_logic_vector(7 downto 0);
begin
Output <= counter(7);
stage_1 <= Input when RISING_EDGE(Clk);
stage_2 <= stage_1 when RISING_EDGE(Clk);
cnt : process (Clk)
begin
if RISING_EDGE(Clk) then
if stage_2 = '1' and counter(7) = '0' then
counter <= counter + 1;
end if;
if stage_2 = '0' then
counter <= ( others => '0' );
end if;
end if;
end process;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Altera
--
-- Description:
-- ------------------------------------
-- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs.
-- It generates 2 flip flops per input bit and notifies Quartus II, that these
-- flip flops are synchronizer flip flops. If you need a platform independent
-- version of this synchronizer, please use 'PoC.misc.sync.sync_Flag', which
-- internally instantiates this module if a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for long time stable signals (flags).
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Bits_Altera is
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits
);
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data
);
end entity;
architecture rtl of sync_Bits_Altera is
attribute PRESERVE : BOOLEAN;
attribute ALTERA_ATTRIBUTE : STRING;
-- Apply a SDC constraint to meta stable flip flop
attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """;
begin
gen : for i in 0 to BITS - 1 generate
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := INIT(i);
signal Data_sync : STD_LOGIC := INIT(i);
-- preserve both registers (no optimization, shift register extraction, ...)
attribute PRESERVE of Data_meta : signal is TRUE;
attribute PRESERVE of Data_sync : signal is TRUE;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute ALTERA_ATTRIBUTE of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
begin
Data_async <= Input(i);
process(Clock)
begin
if rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output(i) <= Data_sync;
end generate;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Altera
--
-- Description:
-- ------------------------------------
-- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs.
-- It generates 2 flip flops per input bit and notifies Quartus II, that these
-- flip flops are synchronizer flip flops. If you need a platform independent
-- version of this synchronizer, please use 'PoC.misc.sync.sync_Flag', which
-- internally instantiates this module if a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for long time stable signals (flags).
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Bits_Altera is
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits
);
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data
);
end entity;
architecture rtl of sync_Bits_Altera is
attribute PRESERVE : BOOLEAN;
attribute ALTERA_ATTRIBUTE : STRING;
-- Apply a SDC constraint to meta stable flip flop
attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """;
begin
gen : for i in 0 to BITS - 1 generate
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := INIT(i);
signal Data_sync : STD_LOGIC := INIT(i);
-- preserve both registers (no optimization, shift register extraction, ...)
attribute PRESERVE of Data_meta : signal is TRUE;
attribute PRESERVE of Data_sync : signal is TRUE;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute ALTERA_ATTRIBUTE of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
begin
Data_async <= Input(i);
process(Clock)
begin
if rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output(i) <= Data_sync;
end generate;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc472.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY vests22 IS
END vests22;
ARCHITECTURE c03s02b01x01p19n01i00472arch OF vests22 IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C66 : array_rec_cons (0 to 7) := (others => C51);
function complex_scalar(s : array_rec_cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_cons(0 to 7);
signal S2 : array_rec_cons(0 to 7);
signal S3 : array_rec_cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00472"
severity NOTE;
assert s1 = c66;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00472 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00472arch;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------
--------------ENTITY---------------
-----------------------------------
entity audiostp is
port (
sclk, fsync, sdata : in std_logic; -- Eingänge definieren
left, right : out signed (17 downto 0); -- 18 Bit Ausgabewerte
flag : out std_logic -- 1 Bit Ausgabeflag
);
end audiostp;
-------------ENTITY END------------
-----------------------------------
-----------ARCHITECTURE------------
-----------------------------------
architecture converter of audiostp is
-----------------------------------
---------SIGNAL DEFINITION---------
-----------------------------------
signal ileft, iright : signed (17 downto 0) := "000000000000000000"; -- interne Zwischenspeicherung der seriellen Daten
signal iflag : unsigned (0 downto 0) := "0"; -- internes Flag um zu speichern, ob sowohl left, als auch
-- right eingelesen wurden und zur Ausgabe bereit sind
signal hflag : unsigned (0 downto 0) := "0"; -- internes Hilfsflag
signal counter : unsigned(4 downto 0) := "10001"; -- Zähler um serielle Daten in Vektor einzufügen
signal rightold : signed ( 17 downto 0 ) := "000000000000000000"; -- Hilfsvariable weil right output nicht gelesen werden kann
signal leftold : signed ( 17 downto 0 ) := "000000000000000000"; -- Hilfsvariable weil left output nicht gelesen werden kann
--------SIGNAL DEFINITION END------
begin -- Architecture begin
-----------------------------------
--------------SPLIT----------------
-----------------------------------
process (fsync, sclk) -- nur wenn sclk sich ändert, wird process betreten
begin
if falling_edge(fsync) or rising_edge(fsync) then -- Wenn fsync sich ändert wird counter zurückgesetzt
counter <= "10001";
elsif falling_edge (sclk) then -- wenn es sich um eine fallende Kante von sclk handelt
case fsync is -- Je nach aktuellem Wert von fsync wird ...
when '1' => ileft (to_integer(unsigned(counter))) <= sdata; -- ... sdata in den 'linken' Vektor an Stelle 'counter' eingefügt
when others => iright (to_integer(unsigned(counter))) <= sdata; -- ... oder in den 'rechten' Vektor eingefügt
end case;
if counter > 0 then
counter <= counter - 1 ; -- nach dem Einfügen wird counter um 1 dekrementiert
end if;
if counter = 0 then -- wenn counter = 0,
iflag <= iflag + 1; -- wird i_flag invertiert (markiert, dass left bzw.
-- right nun vollständig ist)
end if;
end if;
end process;
-------------SPLIT END-------------
-----------------------------------
--------------OUTPUT---------------
-----------------------------------
hflag <= "1" when iflag = "0" -- Wenn i_flag auf 0 gesetzt ist, wird h_flag auf 1 gesetzt.
-- Da dies in einem Concurrent Statement geschieht, wird die
-- Aenderung des h_flags erst beim nächsten Durchlauf für
-- die anderen Statements sichtbar, was ermöglich, dass
-- das Ausgabeflag im nächsten Takt wieder auf 0 gesetzt wird.
-- wenn i_flag auf 1 gesetzt ist, wird h_flag auf wieder auf 0 gesetzt
else "0";
rightold <= iright when iflag = "0" and hflag = "0" -- erst wenn i_flag wieder auf 0 gesetzt wurde (also nach
-- einem kompletten left-right Zyklus) und das Hilfsflag
-- auf 0 steht (siehe h_flag), wird dem Ausgang 'right' der
-- neue Wert von i_right zugewiesen
else rightold; -- ansonsten bleibt der Wert von right beibehalten.
leftold <= ileft when iflag = "0" and hflag = "0" -- analog zur Zuweisung von right
else leftold;
left <= leftold;
right <= rightold;
flag <= '1' when iflag = "0" and hflag = "0" -- Ausgabeflag wird für einen Takt auf 1 gesetzt wenn i_flag
-- auf 0 steht (also nach einem kompletten left-right Zyklus)
-- und h_flag auch auf 0 steht.
else '0'; -- Da h_flag im nächsten Durchlauf bereits auf 1 steht (siehe h_flag)
-- wird Ausgabeflag im nächsten Durchlauf wieder auf 0 gesetzt.
-------------OUTPUT END------------
end converter;
----------ARCHITECTURE END---------
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_config_TVALID : IN STD_LOGIC;
P_config_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_netOut_TVALID : OUT STD_LOGIC;
P_netOut_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=42,HLS_SYN_FF=8905,HLS_SYN_LUT=12500}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (153 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (153 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (153 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (153 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (153 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (153 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (153 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (153 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (153 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (153 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_7C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111100";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_96 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010110";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv37_0 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000000";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv38_23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100011";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv39_23 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000100011";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv37_23 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100011";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_550 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_253 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal ap_sig_cseq_ST_st125_fsm_124 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal reg_557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_285 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_294 : BOOLEAN;
signal grp_fu_498_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_563 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_311 : BOOLEAN;
signal grp_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_328 : BOOLEAN;
signal reg_574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_337 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_344 : BOOLEAN;
signal grp_fu_512_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_354 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_361 : BOOLEAN;
signal grp_fu_529_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_371 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_378 : BOOLEAN;
signal grp_fu_509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_388 : BOOLEAN;
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_395 : BOOLEAN;
signal P_mode_read_reg_1443 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_408 : BOOLEAN;
signal tmp_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_load_reg_1452 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1461 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_0_load_reg_1465 : STD_LOGIC_VECTOR (31 downto 0);
signal P_config_read_reg_1470 : STD_LOGIC_VECTOR (31 downto 0);
signal i_8_fu_627_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_432 : BOOLEAN;
signal tmp_7_fu_622_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_439 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_449 : BOOLEAN;
signal tmp_9_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_672_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_52_reg_1496 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_31_fu_682_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_reg_1501 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_467 : BOOLEAN;
signal tmp_40_fu_686_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_40_reg_1506 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_651_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_24_reg_1511 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_478 : BOOLEAN;
signal tmp_27_fu_690_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_reg_1516 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_33_fu_694_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_reg_1521 : STD_LOGIC_VECTOR (8 downto 0);
signal j_5_fu_718_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_491 : BOOLEAN;
signal tmp_26_fu_724_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_reg_1534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_71_fu_775_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_reg_1540 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_2_reg_1546 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_781_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_fu_796_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_reg_1559 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_513 : BOOLEAN;
signal tmp_28_fu_791_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_519_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_37_reg_1579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_533 : BOOLEAN;
signal grp_fu_524_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_reg_1584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_542 : BOOLEAN;
signal tmp_53_fu_863_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_reg_1589 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_551 : BOOLEAN;
signal tmp_58_fu_867_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_58_reg_1594 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_46_fu_871_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_reg_1599 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_562 : BOOLEAN;
signal tmp_51_fu_875_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_51_reg_1606 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_56_fu_879_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_56_reg_1611 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_fu_884_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_1616 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_575 : BOOLEAN;
signal i_12_fu_903_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1625 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_909_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_1630 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_75_fu_960_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_75_reg_1636 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_4_reg_1642 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_975_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_6_reg_1650 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_596 : BOOLEAN;
signal tmp_29_fu_970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_615 : BOOLEAN;
signal i_11_fu_1031_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_11_reg_1678 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_624 : BOOLEAN;
signal p_uOut_addr_5_reg_1683 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_30_fu_1026_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_fu_1051_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_reg_1688 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_504_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_1692 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_642 : BOOLEAN;
signal p_netOut_2_cast_fu_1056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_cast_reg_1697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_651 : BOOLEAN;
signal tmp_50_fu_1060_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_TREADY : STD_LOGIC;
signal i_15_fu_1093_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_15_reg_1715 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_90_fu_1099_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_90_reg_1720 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1103_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal next_mul_reg_1725 : STD_LOGIC_VECTOR (36 downto 0);
signal i_14_fu_1118_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_14_reg_1733 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_91_fu_1124_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_91_reg_1738 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_49_fu_1113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_reg_1743 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_1205_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_65_reg_1749 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_701 : BOOLEAN;
signal p_netOut_1_fu_1211_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_710 : BOOLEAN;
signal j_7_fu_1236_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_7_reg_1762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_719 : BOOLEAN;
signal tmp_55_fu_1230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_1260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1772 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_734 : BOOLEAN;
signal grp_fu_1269_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_8_reg_1781 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st151_fsm_150 : STD_LOGIC;
signal ap_sig_bdd_748 : BOOLEAN;
signal tmp_10_fu_1275_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_10_reg_1786 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_fu_1279_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_reg_1791 : STD_LOGIC_VECTOR (1 downto 0);
signal j_4_fu_1304_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_4_reg_1799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st152_fsm_151 : STD_LOGIC;
signal ap_sig_bdd_761 : BOOLEAN;
signal tmp_23_fu_1343_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_reg_1804 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_s_fu_1298_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1349_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_2_fu_1380_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st153_fsm_152 : STD_LOGIC;
signal ap_sig_bdd_779 : BOOLEAN;
signal tmp_17_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_786 : BOOLEAN;
signal tmp_2_fu_1404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_1822 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_796 : BOOLEAN;
signal ap_sig_bdd_801 : BOOLEAN;
signal i_7_fu_1409_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_275 : STD_LOGIC_VECTOR (30 downto 0);
signal i_3_reg_286 : STD_LOGIC_VECTOR (30 downto 0);
signal j_1_reg_298 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_832 : BOOLEAN;
signal sum_reg_309 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_321 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_332 : STD_LOGIC_VECTOR (31 downto 0);
signal i_4_reg_344 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_355 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_367 : STD_LOGIC_VECTOR (30 downto 0);
signal i_5_reg_378 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_853 : BOOLEAN;
signal p_netOut_reg_389 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_reg_402 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_413 : STD_LOGIC_VECTOR (30 downto 0);
signal phi_mul_reg_424 : STD_LOGIC_VECTOR (36 downto 0);
signal j_3_reg_435 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_879 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_446 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_458 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_469 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_480 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_3_fu_633_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_746_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_838_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_931_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_994_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1017_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1046_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1074_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_94_cast_fu_1088_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_95_cast_fu_1251_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_1395_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_1415_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_997 : BOOLEAN;
signal grp_fu_491_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_1021 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_1028 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_1036 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_1043 : BOOLEAN;
signal grp_fu_509_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_512_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_fu_853_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_cast_fu_618_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_cast_fu_638_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_651_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_651_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_13_fu_657_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_11_fu_676_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_22_fu_699_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_cast_fu_737_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_68_fu_741_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_69_fu_751_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_763_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_755_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_767_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal k_1_cast_fu_787_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_806_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_fu_810_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_802_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_fu_820_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_82_fu_830_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_83_fu_833_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_34_to_int_fu_843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_neg_fu_847_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_858_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p2 : STD_LOGIC_VECTOR (38 downto 0);
signal tmp_27_cast_fu_922_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_72_fu_926_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_73_fu_936_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_fu_948_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_940_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_952_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal j_2_cast_fu_966_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_985_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_86_fu_989_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_84_fu_981_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_999_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_88_fu_1009_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1012_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_5_cast_fu_1022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_1037_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1041_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_92_fu_1065_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_fu_1069_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_96_fu_1079_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_94_fu_1083_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_6_cast_fu_1109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_3_to_int_fu_1128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_to_int_fu_1146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_1132_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_fu_1142_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_1169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_1149_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_98_fu_1159_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_1187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_1175_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_1193_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_63_fu_1199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_515_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_1217_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_1242_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_95_fu_1246_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_1_cast_fu_1256_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1269_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_1269_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_1285_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_cast_fu_1310_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_12_fu_1314_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_14_fu_1319_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1331_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl_cast_fu_1323_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_1335_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_fu_1355_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_1368_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_1386_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_67_fu_1390_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_cast_fu_1400_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_ce : STD_LOGIC;
signal grp_fu_498_ce : STD_LOGIC;
signal grp_fu_504_ce : STD_LOGIC;
signal tmp_64_fu_515_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_519_ce : STD_LOGIC;
signal grp_fu_524_ce : STD_LOGIC;
signal grp_fu_529_ce : STD_LOGIC;
signal grp_fu_651_ce : STD_LOGIC;
signal grp_fu_666_ce : STD_LOGIC;
signal grp_fu_1269_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (153 downto 0);
signal grp_fu_1269_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal grp_fu_651_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_bdd_976 : BOOLEAN;
component feedforward_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mul_7ns_31ns_38_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (30 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (37 downto 0) );
end component;
component feedforward_mul_7ns_32s_39_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (38 downto 0) );
end component;
component feedforward_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode => P_mode);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 32,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0 : component feedforward_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_491_p0,
din1 => grp_fu_491_p1,
ce => grp_fu_491_ce,
dout => grp_fu_491_p2);
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1 : component feedforward_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => p_uOut_q0,
din1 => ST_WandB_q0,
ce => grp_fu_498_ce,
dout => grp_fu_498_p2);
feedforward_fdiv_32ns_32ns_32_16_U2 : component feedforward_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_550,
din1 => sumsoft_reg_332,
ce => grp_fu_504_ce,
dout => grp_fu_504_p2);
feedforward_fptrunc_64ns_32_1_U3 : component feedforward_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_509_p0,
dout => grp_fu_509_p1);
feedforward_fpext_32ns_64_1_U4 : component feedforward_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_512_p0,
dout => grp_fu_512_p1);
feedforward_fcmp_32ns_32ns_1_1_U5 : component feedforward_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_550,
din1 => p_uOut_load_4_reg_1743,
opcode => tmp_64_fu_515_opcode,
dout => tmp_64_fu_515_p2);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_584,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_519_ce,
dout => grp_fu_519_p2);
feedforward_ddiv_64ns_64ns_64_31_U7 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_37_reg_1579,
ce => grp_fu_524_ce,
dout => grp_fu_524_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_579,
ce => grp_fu_529_ce,
dout => grp_fu_529_p2);
feedforward_mul_7ns_31ns_38_3_U9 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_651_p0,
din1 => grp_fu_651_p1,
ce => grp_fu_651_ce,
dout => grp_fu_651_p2);
feedforward_mul_7ns_32s_39_3_U10 : component feedforward_mul_7ns_32s_39_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 32,
dout_WIDTH => 39)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_666_p0,
din1 => tmp_13_fu_657_p2,
ce => grp_fu_666_ce,
dout => grp_fu_666_p2);
feedforward_mux_4to1_sel2_32_1_U11 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_27_reg_1516,
dout => tmp_22_fu_699_p6);
feedforward_mux_4to1_sel2_32_1_U12 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_40_reg_1506,
dout => tmp_26_fu_724_p6);
feedforward_mux_4to1_sel2_32_1_U13 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_52_reg_1496,
dout => tmp_25_fu_884_p6);
feedforward_mux_4to1_sel2_32_1_U14 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_58_reg_1594,
dout => tmp_54_fu_909_p6);
feedforward_mux_4to1_sel2_32_1_U15 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_91_reg_1738,
dout => tmp_66_fu_1217_p6);
feedforward_mul_7ns_31ns_38_3_U16 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1269_p0,
din1 => grp_fu_1269_p1,
ce => grp_fu_1269_ce,
dout => grp_fu_1269_p2);
feedforward_mux_4to1_sel2_32_1_U17 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_10_reg_1786,
dout => tmp_5_fu_1285_p6);
feedforward_mux_4to1_sel2_32_1_U18 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_9_t_reg_1791,
dout => tmp_21_fu_1355_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_TREADY assign process. --
ap_reg_ioackin_P_netOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_976) then
if (not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_TREADY)) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_446 assign process. --
i_1_reg_446_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
i_1_reg_446 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and (ap_const_lv1_0 = tmp_s_fu_1298_p2))) then
i_1_reg_446 <= i_9_fu_1349_p2;
end if;
end if;
end process;
-- i_2_reg_275 assign process. --
i_2_reg_275_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
i_2_reg_275 <= ap_const_lv31_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
i_2_reg_275 <= i_8_fu_627_p2;
end if;
end if;
end process;
-- i_3_reg_286 assign process. --
i_3_reg_286_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
i_3_reg_286 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_18_fu_712_p2))) then
i_3_reg_286 <= i_10_fu_781_p2;
end if;
end if;
end process;
-- i_4_reg_344 assign process. --
i_4_reg_344_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
i_4_reg_344 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
i_4_reg_344 <= i_12_reg_1625;
end if;
end if;
end process;
-- i_5_reg_378 assign process. --
i_5_reg_378_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_20_fu_897_p2))) then
i_5_reg_378 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
i_5_reg_378 <= i_11_reg_1678;
end if;
end if;
end process;
-- i_6_reg_413 assign process. --
i_6_reg_413_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
i_6_reg_413 <= i_14_reg_1733;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
i_6_reg_413 <= ap_const_lv31_0;
end if;
end if;
end process;
-- i_reg_480 assign process. --
i_reg_480_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
i_reg_480 <= i_7_fu_1409_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
i_reg_480 <= ap_const_lv31_0;
end if;
end if;
end process;
-- j_1_reg_298 assign process. --
j_1_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
j_1_reg_298 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
j_1_reg_298 <= j_5_reg_1529;
end if;
end if;
end process;
-- j_2_reg_367 assign process. --
j_2_reg_367_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
j_2_reg_367 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
j_2_reg_367 <= j_6_reg_1650;
end if;
end if;
end process;
-- j_3_reg_435 assign process. --
j_3_reg_435_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
j_3_reg_435 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_435 <= j_7_reg_1762;
end if;
end if;
end process;
-- j_reg_458 assign process. --
j_reg_458_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and (ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
j_reg_458 <= j_4_reg_1799;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
j_reg_458 <= ap_const_lv32_0;
end if;
end if;
end process;
-- k_1_reg_321 assign process. --
k_1_reg_321_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
k_1_reg_321 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
k_1_reg_321 <= k_3_reg_1559;
end if;
end if;
end process;
-- k_reg_469 assign process. --
k_reg_469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
k_reg_469 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
k_reg_469 <= k_2_fu_1380_p2;
end if;
end if;
end process;
-- p_netOut_2_reg_402 assign process. --
p_netOut_2_reg_402_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_2_reg_402 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_2_reg_402 <= i_15_reg_1715;
end if;
end if;
end process;
-- p_netOut_reg_389 assign process. --
p_netOut_reg_389_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_reg_389 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_reg_389 <= p_netOut_1_fu_1211_p3;
end if;
end if;
end process;
-- phi_mul_reg_424 assign process. --
phi_mul_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
phi_mul_reg_424 <= next_mul_reg_1725;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
phi_mul_reg_424 <= ap_const_lv37_0;
end if;
end if;
end process;
-- sum_1_reg_355 assign process. --
sum_1_reg_355_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
sum_1_reg_355 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
sum_1_reg_355 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sum_reg_309 assign process. --
sum_reg_309_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
sum_reg_309 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
sum_reg_309 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sumsoft_reg_332 assign process. --
sumsoft_reg_332_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
sumsoft_reg_332 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
sumsoft_reg_332 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
P_config_read_reg_1470 <= P_config_TDATA;
ST_numLayer <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_408))) then
P_mode_read_reg_1443 <= P_mode;
ST_numLayer_load_reg_1452 <= ST_numLayer;
tmp_reg_1448 <= tmp_fu_596_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ST_layerSize_0_load_reg_1465 <= ST_layerSize_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and not((tmp_4_fu_1415_p1 = ap_const_lv2_2)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_1)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
i_11_reg_1678 <= i_11_fu_1031_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
i_12_reg_1625 <= i_12_fu_903_p2;
tmp_25_reg_1616 <= tmp_25_fu_884_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)))) then
i_14_reg_1733 <= i_14_fu_1118_p2;
next_mul_reg_1725 <= next_mul_fu_1103_p2;
tmp_90_reg_1720 <= tmp_90_fu_1099_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
i_15_reg_1715 <= i_15_fu_1093_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) then
j_4_reg_1799 <= j_4_fu_1304_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
j_5_reg_1529 <= j_5_fu_718_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
j_6_reg_1650 <= j_6_fu_975_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
j_7_reg_1762 <= j_7_fu_1236_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
k_3_reg_1559 <= k_3_fu_796_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))))) then
p_netOut_2_cast_reg_1697(30 downto 0) <= p_netOut_2_cast_fu_1056_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
p_uOut_addr_2_reg_1546 <= tmp_77_cast_fu_746_p1(8 - 1 downto 0);
tmp_26_reg_1534 <= tmp_26_fu_724_p6;
tmp_71_reg_1540(13 downto 2) <= tmp_71_fu_775_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
p_uOut_addr_4_reg_1642 <= tmp_81_cast_fu_931_p1(8 - 1 downto 0);
tmp_54_reg_1630 <= tmp_54_fu_909_p6;
tmp_75_reg_1636(13 downto 2) <= tmp_75_fu_960_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and not((ap_const_lv1_0 = tmp_30_fu_1026_p2)))) then
p_uOut_addr_5_reg_1683 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) then
p_uOut_load_4_reg_1743 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124) or (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143))) then
reg_550 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
reg_557 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
reg_563 <= grp_fu_498_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_574 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
reg_579 <= grp_fu_512_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
reg_584 <= grp_fu_529_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
reg_590 <= grp_fu_509_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
tmp_10_reg_1786 <= tmp_10_fu_1275_p1;
tmp_8_reg_1781 <= grp_fu_1269_p2;
tmp_9_t_reg_1791 <= tmp_9_t_fu_1279_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408))) then
tmp_1_reg_1461 <= tmp_1_fu_606_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
tmp_23_reg_1804(13 downto 2) <= tmp_23_fu_1343_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_24_reg_1511 <= grp_fu_651_p2;
tmp_27_reg_1516 <= tmp_27_fu_690_p1;
tmp_33_reg_1521 <= tmp_33_fu_694_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not(ap_sig_bdd_801))) then
tmp_2_reg_1822 <= tmp_2_fu_1404_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_31_reg_1501 <= tmp_31_fu_682_p1;
tmp_40_reg_1506 <= tmp_40_fu_686_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) then
tmp_37_reg_1579 <= grp_fu_519_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
tmp_38_reg_1584 <= grp_fu_524_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
tmp_46_reg_1599 <= tmp_46_fu_871_p1;
tmp_51_reg_1606 <= tmp_51_fu_875_p1;
tmp_56_reg_1611 <= tmp_56_fu_879_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
tmp_47_reg_1692 <= grp_fu_504_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2))) then
tmp_48_reg_1688 <= tmp_48_fu_1051_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_9_fu_642_p2))) then
tmp_52_reg_1496 <= tmp_52_fu_672_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
tmp_53_reg_1589 <= tmp_53_fu_863_p1;
tmp_58_reg_1594 <= tmp_58_fu_867_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) then
tmp_65_reg_1749 <= tmp_65_fu_1205_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) then
tmp_6_reg_1772 <= tmp_6_fu_1260_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
tmp_91_reg_1738 <= tmp_91_fu_1124_p1;
end if;
end if;
end process;
tmp_71_reg_1540(1 downto 0) <= "00";
tmp_75_reg_1636(1 downto 0) <= "00";
p_netOut_2_cast_reg_1697(31) <= '0';
tmp_23_reg_1804(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_596_p2, ap_sig_bdd_408, tmp_reg_1448, tmp_1_fu_606_p2, tmp_1_reg_1461, tmp_7_fu_622_p2, ap_sig_bdd_439, tmp_9_fu_642_p2, tmp_18_fu_712_p2, tmp_28_fu_791_p2, tmp_20_fu_897_p2, tmp_29_fu_970_p2, tmp_30_fu_1026_p2, tmp_48_reg_1688, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_55_fu_1230_p2, tmp_6_fu_1260_p2, tmp_6_reg_1772, tmp_s_fu_1298_p2, tmp_17_fu_1374_p2, ap_sig_bdd_786, tmp_2_fu_1404_p2, tmp_2_reg_1822, ap_sig_bdd_801, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_9_fu_642_p2)) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = tmp_18_fu_712_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_28_fu_791_p2)) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
if (not((ap_const_lv1_0 = tmp_20_fu_897_p2))) then
ap_NS_fsm <= ap_ST_st83_fsm_82;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st83_fsm_82 =>
if ((ap_const_lv1_0 = tmp_29_fu_970_p2)) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st84_fsm_83;
end if;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st124_fsm_123 =>
if ((ap_const_lv1_0 = tmp_30_fu_1026_p2)) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st125_fsm_124;
end if;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st143_fsm_142 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st147_fsm_146 =>
if (not((ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st148_fsm_147 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (not((ap_const_lv1_0 = tmp_6_fu_1260_p2))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st151_fsm_150;
when ap_ST_st151_fsm_150 =>
ap_NS_fsm <= ap_ST_st152_fsm_151;
when ap_ST_st152_fsm_151 =>
if ((ap_const_lv1_0 = tmp_s_fu_1298_p2)) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st153_fsm_152 =>
if ((not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st153_fsm_152;
elsif (((ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st152_fsm_151;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st154_fsm_153 =>
if ((not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((ap_const_lv1_0 = tmp_2_fu_1404_p2) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st154_fsm_153;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_TREADY assign process. --
P_config_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_596_p2, ap_sig_bdd_408, tmp_2_fu_1404_p2, ap_sig_cseq_ST_st154_fsm_153, ap_sig_bdd_801)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801)))) then
P_config_TREADY <= ap_const_logic_1;
else
P_config_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_TDATA <= p_netOut_reg_389;
-- P_netOut_TVALID assign process. --
P_netOut_TVALID_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_reg_ioackin_P_netOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY))) then
P_netOut_TVALID <= ap_const_logic_1;
else
P_netOut_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, tmp_85_cast_fu_815_p1, tmp_87_cast_fu_838_p1, tmp_88_cast_fu_994_p1, tmp_90_cast_fu_1017_p1, tmp_76_cast_fu_1395_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) then
ST_WandB_address0 <= tmp_76_cast_fu_1395_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2))) then
ST_WandB_address0 <= tmp_90_cast_fu_1017_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_994_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2))) then
ST_WandB_address0 <= tmp_87_cast_fu_838_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2)))) then
ST_WandB_address0 <= tmp_85_cast_fu_815_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not(ap_sig_bdd_786)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1021 assign process. --
ap_sig_bdd_1021_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1021 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_1028 assign process. --
ap_sig_bdd_1028_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1028 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_1036 assign process. --
ap_sig_bdd_1036_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1036 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_1043 assign process. --
ap_sig_bdd_1043_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1043 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_172 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_253 assign process. --
ap_sig_bdd_253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_253 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(124 downto 124));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_285 assign process. --
ap_sig_bdd_285_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_285 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_294 assign process. --
ap_sig_bdd_294_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_294 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_304 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_311 assign process. --
ap_sig_bdd_311_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_311 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_321 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_328 assign process. --
ap_sig_bdd_328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_328 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_337 assign process. --
ap_sig_bdd_337_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_337 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_344 assign process. --
ap_sig_bdd_344_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_344 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_354 assign process. --
ap_sig_bdd_354_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_354 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_361 assign process. --
ap_sig_bdd_361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_361 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_371 assign process. --
ap_sig_bdd_371_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_371 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_378 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_388 assign process. --
ap_sig_bdd_388_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_388 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_395 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_408 assign process. --
ap_sig_bdd_408_assign_proc : process(ap_start, P_config_TVALID, tmp_fu_596_p2)
begin
ap_sig_bdd_408 <= (((P_config_TVALID = ap_const_logic_0) and not((tmp_fu_596_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_432 assign process. --
ap_sig_bdd_432_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_432 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_439 assign process. --
ap_sig_bdd_439_assign_proc : process(P_netIn_TVALID, tmp_7_fu_622_p2)
begin
ap_sig_bdd_439 <= ((P_netIn_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)));
end process;
-- ap_sig_bdd_449 assign process. --
ap_sig_bdd_449_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_449 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_467 assign process. --
ap_sig_bdd_467_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_467 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_478 assign process. --
ap_sig_bdd_478_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_478 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_491 assign process. --
ap_sig_bdd_491_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_491 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_513 assign process. --
ap_sig_bdd_513_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_513 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_533 assign process. --
ap_sig_bdd_533_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_533 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_542 assign process. --
ap_sig_bdd_542_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_542 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_551 assign process. --
ap_sig_bdd_551_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_551 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_562 assign process. --
ap_sig_bdd_562_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_562 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_575 assign process. --
ap_sig_bdd_575_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_575 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_596 assign process. --
ap_sig_bdd_596_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_596 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_615 assign process. --
ap_sig_bdd_615_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_615 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_624 assign process. --
ap_sig_bdd_624_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_624 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_642 assign process. --
ap_sig_bdd_642_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_642 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_651 assign process. --
ap_sig_bdd_651_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_651 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_701 assign process. --
ap_sig_bdd_701_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_701 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_710 assign process. --
ap_sig_bdd_710_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_710 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_719 assign process. --
ap_sig_bdd_719_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_719 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_734 assign process. --
ap_sig_bdd_734_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_734 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_748 assign process. --
ap_sig_bdd_748_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_748 <= (ap_const_lv1_1 = ap_CS_fsm(150 downto 150));
end process;
-- ap_sig_bdd_761 assign process. --
ap_sig_bdd_761_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_761 <= (ap_const_lv1_1 = ap_CS_fsm(151 downto 151));
end process;
-- ap_sig_bdd_779 assign process. --
ap_sig_bdd_779_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_779 <= (ap_const_lv1_1 = ap_CS_fsm(152 downto 152));
end process;
-- ap_sig_bdd_786 assign process. --
ap_sig_bdd_786_assign_proc : process(P_WandB_TVALID, tmp_17_fu_1374_p2)
begin
ap_sig_bdd_786 <= ((P_WandB_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)));
end process;
-- ap_sig_bdd_796 assign process. --
ap_sig_bdd_796_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_796 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_801 assign process. --
ap_sig_bdd_801_assign_proc : process(P_config_TVALID, tmp_2_fu_1404_p2)
begin
ap_sig_bdd_801 <= ((P_config_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)));
end process;
-- ap_sig_bdd_832 assign process. --
ap_sig_bdd_832_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_832 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_853 assign process. --
ap_sig_bdd_853_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_853 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_879 assign process. --
ap_sig_bdd_879_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_879 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_976 assign process. --
ap_sig_bdd_976_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2)
begin
ap_sig_bdd_976 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2));
end process;
-- ap_sig_bdd_997 assign process. --
ap_sig_bdd_997_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_997 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_378)
begin
if (ap_sig_bdd_378) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_395)
begin
if (ap_sig_bdd_395) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_997)
begin
if (ap_sig_bdd_997) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_304)
begin
if (ap_sig_bdd_304) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_615)
begin
if (ap_sig_bdd_615) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_624)
begin
if (ap_sig_bdd_624) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st125_fsm_124 assign process. --
ap_sig_cseq_ST_st125_fsm_124_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_1021)
begin
if (ap_sig_bdd_1021) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_642)
begin
if (ap_sig_bdd_642) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_853)
begin
if (ap_sig_bdd_853) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_651)
begin
if (ap_sig_bdd_651) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_701)
begin
if (ap_sig_bdd_701) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_710)
begin
if (ap_sig_bdd_710) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_719)
begin
if (ap_sig_bdd_719) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_879)
begin
if (ap_sig_bdd_879) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st151_fsm_150 assign process. --
ap_sig_cseq_ST_st151_fsm_150_assign_proc : process(ap_sig_bdd_748)
begin
if (ap_sig_bdd_748) then
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st152_fsm_151 assign process. --
ap_sig_cseq_ST_st152_fsm_151_assign_proc : process(ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) then
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st153_fsm_152 assign process. --
ap_sig_cseq_ST_st153_fsm_152_assign_proc : process(ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) then
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_796)
begin
if (ap_sig_bdd_796) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_321)
begin
if (ap_sig_bdd_321) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_285)
begin
if (ap_sig_bdd_285) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_1028)
begin
if (ap_sig_bdd_1028) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_172)
begin
if (ap_sig_bdd_172) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_337)
begin
if (ap_sig_bdd_337) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_354)
begin
if (ap_sig_bdd_354) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_432)
begin
if (ap_sig_bdd_432) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_449)
begin
if (ap_sig_bdd_449) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_371)
begin
if (ap_sig_bdd_371) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_533)
begin
if (ap_sig_bdd_533) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_467)
begin
if (ap_sig_bdd_467) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_478)
begin
if (ap_sig_bdd_478) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_542)
begin
if (ap_sig_bdd_542) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_388)
begin
if (ap_sig_bdd_388) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_832)
begin
if (ap_sig_bdd_832) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_513)
begin
if (ap_sig_bdd_513) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_551)
begin
if (ap_sig_bdd_551) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_562)
begin
if (ap_sig_bdd_562) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_575)
begin
if (ap_sig_bdd_575) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_596)
begin
if (ap_sig_bdd_596) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_311)
begin
if (ap_sig_bdd_311) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_1036)
begin
if (ap_sig_bdd_1036) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_328)
begin
if (ap_sig_bdd_328) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_294)
begin
if (ap_sig_bdd_294) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_1043)
begin
if (ap_sig_bdd_1043) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_344)
begin
if (ap_sig_bdd_344) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_361)
begin
if (ap_sig_bdd_361) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_TREADY assign process. --
ap_sig_ioackin_P_netOut_TREADY_assign_proc : process(P_netOut_TREADY, ap_reg_ioackin_P_netOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY)) then
ap_sig_ioackin_P_netOut_TREADY <= P_netOut_TREADY;
else
ap_sig_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_1269_ce <= ap_const_logic_1;
grp_fu_1269_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_1269_p1 <= grp_fu_1269_p10(31 - 1 downto 0);
grp_fu_1269_p10 <= std_logic_vector(resize(unsigned(i_1_reg_446),38));
grp_fu_491_ce <= ap_const_logic_1;
-- grp_fu_491_p0 assign process. --
grp_fu_491_p0_assign_proc : process(sum_reg_309, sumsoft_reg_332, sum_1_reg_355, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p0 <= sumsoft_reg_332;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p0 <= sum_1_reg_355;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
grp_fu_491_p0 <= sum_reg_309;
else
grp_fu_491_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_491_p1 assign process. --
grp_fu_491_p1_assign_proc : process(reg_557, reg_563, reg_590, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p1 <= reg_590;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p1 <= reg_557;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
grp_fu_491_p1 <= reg_563;
else
grp_fu_491_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_498_ce <= ap_const_logic_1;
grp_fu_504_ce <= ap_const_logic_1;
-- grp_fu_509_p0 assign process. --
grp_fu_509_p0_assign_proc : process(reg_584, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st118_fsm_117, tmp_38_reg_1584)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_509_p0 <= reg_584;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
grp_fu_509_p0 <= tmp_38_reg_1584;
else
grp_fu_509_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_512_p0 assign process. --
grp_fu_512_p0_assign_proc : process(reg_574, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st99_fsm_98, tmp_34_fu_853_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) then
grp_fu_512_p0 <= reg_574;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
grp_fu_512_p0 <= tmp_34_fu_853_p1;
else
grp_fu_512_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_519_ce <= ap_const_logic_1;
grp_fu_524_ce <= ap_const_logic_1;
grp_fu_529_ce <= ap_const_logic_1;
grp_fu_651_ce <= ap_const_logic_1;
grp_fu_651_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_651_p1 <= grp_fu_651_p10(31 - 1 downto 0);
grp_fu_651_p10 <= std_logic_vector(resize(unsigned(i_3_reg_286),38));
grp_fu_666_ce <= ap_const_logic_1;
grp_fu_666_p0 <= ap_const_lv39_23(7 - 1 downto 0);
i_10_fu_781_p2 <= std_logic_vector(unsigned(i_3_reg_286) + unsigned(ap_const_lv31_1));
i_11_fu_1031_p2 <= std_logic_vector(unsigned(i_5_reg_378) + unsigned(ap_const_lv31_1));
i_12_fu_903_p2 <= std_logic_vector(unsigned(i_4_reg_344) + unsigned(ap_const_lv32_1));
i_14_fu_1118_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(i_6_reg_413));
i_15_fu_1093_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(p_netOut_2_reg_402));
i_1_cast_fu_1256_p1 <= std_logic_vector(resize(unsigned(i_1_reg_446),32));
i_2_cast_fu_618_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),32));
i_3_cast_fu_638_p1 <= std_logic_vector(resize(unsigned(i_3_reg_286),32));
i_5_cast_fu_1022_p1 <= std_logic_vector(resize(unsigned(i_5_reg_378),32));
i_6_cast_fu_1109_p1 <= std_logic_vector(resize(unsigned(i_6_reg_413),32));
i_7_fu_1409_p2 <= std_logic_vector(unsigned(i_reg_480) + unsigned(ap_const_lv31_1));
i_8_fu_627_p2 <= std_logic_vector(unsigned(i_2_reg_275) + unsigned(ap_const_lv31_1));
i_9_fu_1349_p2 <= std_logic_vector(unsigned(i_1_reg_446) + unsigned(ap_const_lv31_1));
i_cast_fu_1400_p1 <= std_logic_vector(resize(unsigned(i_reg_480),32));
j_2_cast_fu_966_p1 <= std_logic_vector(resize(unsigned(j_2_reg_367),32));
j_4_fu_1304_p2 <= std_logic_vector(unsigned(j_reg_458) + unsigned(ap_const_lv32_1));
j_5_fu_718_p2 <= std_logic_vector(unsigned(j_1_reg_298) + unsigned(ap_const_lv32_1));
j_6_fu_975_p2 <= std_logic_vector(unsigned(j_2_reg_367) + unsigned(ap_const_lv31_1));
j_7_fu_1236_p2 <= std_logic_vector(unsigned(j_3_reg_435) + unsigned(ap_const_lv32_1));
k_1_cast_fu_787_p1 <= std_logic_vector(resize(unsigned(k_1_reg_321),32));
k_2_fu_1380_p2 <= std_logic_vector(unsigned(k_reg_469) + unsigned(ap_const_lv32_1));
k_3_fu_796_p2 <= std_logic_vector(unsigned(k_1_reg_321) + unsigned(ap_const_lv31_1));
next_mul_fu_1103_p2 <= std_logic_vector(unsigned(ap_const_lv37_23) + unsigned(phi_mul_reg_424));
notlhs1_fu_1181_p2 <= "0" when (tmp_59_fu_1149_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_1163_p2 <= "0" when (tmp_57_fu_1132_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_1187_p2 <= "1" when (tmp_98_fu_1159_p1 = ap_const_lv23_0) else "0";
notrhs_fu_1169_p2 <= "1" when (tmp_97_fu_1142_p1 = ap_const_lv23_0) else "0";
p_netOut_1_fu_1211_p3 <=
p_netOut_2_cast_reg_1697 when (tmp_65_reg_1749(0) = '1') else
p_netOut_reg_389;
p_netOut_2_cast_fu_1056_p1 <= std_logic_vector(resize(unsigned(p_netOut_2_reg_402),32));
p_shl1_cast_fu_1335_p3 <= (tmp_19_fu_1331_p1 & ap_const_lv2_0);
p_shl2_cast_fu_755_p3 <= (tmp_69_fu_751_p1 & ap_const_lv5_0);
p_shl3_cast_fu_767_p3 <= (tmp_70_fu_763_p1 & ap_const_lv2_0);
p_shl4_cast_fu_940_p3 <= (tmp_73_fu_936_p1 & ap_const_lv5_0);
p_shl5_cast_fu_952_p3 <= (tmp_74_fu_948_p1 & ap_const_lv2_0);
p_shl_cast_fu_1323_p3 <= (tmp_14_fu_1319_p1 & ap_const_lv5_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_2_reg_1546, ap_sig_cseq_ST_st7_fsm_6, p_uOut_addr_4_reg_1642, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, p_uOut_addr_5_reg_1683, ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, tmp_3_fu_633_p1, tmp_86_cast_fu_825_p1, tmp_89_cast_fu_1004_p1, tmp_91_cast_fu_1046_p1, tmp_93_cast_fu_1074_p1, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1683;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
p_uOut_address0 <= p_uOut_addr_4_reg_1642;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
p_uOut_address0 <= p_uOut_addr_2_reg_1546;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_3_fu_633_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address0 <= tmp_93_cast_fu_1074_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
p_uOut_address0 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
p_uOut_address0 <= tmp_89_cast_fu_1004_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
p_uOut_address0 <= tmp_86_cast_fu_825_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st147_fsm_146, tmp_94_cast_fu_1088_p1, tmp_95_cast_fu_1251_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
p_uOut_address1 <= tmp_95_cast_fu_1251_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address1 <= tmp_94_cast_fu_1088_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_439, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) or ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st147_fsm_146)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_590, ap_sig_cseq_ST_st2_fsm_1, tmp_47_reg_1692, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_d0 <= tmp_47_reg_1692;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_d0 <= reg_590;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1128_p1 <= reg_550;
p_uOut_load_4_to_int_fu_1146_p1 <= p_uOut_load_4_reg_1743;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_1275_p1 <= i_1_reg_446(2 - 1 downto 0);
tmp_11_fu_676_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_3_reg_286));
tmp_12_fu_1314_p2 <= std_logic_vector(signed(tmp_4_cast_fu_1310_p1) + signed(tmp_8_reg_1781));
tmp_13_fu_657_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(ST_numLayer_load_reg_1452));
tmp_14_fu_1319_p1 <= tmp_12_fu_1314_p2(9 - 1 downto 0);
tmp_15_fu_858_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1452));
tmp_16_fu_1368_p2 <= std_logic_vector(unsigned(tmp_21_fu_1355_p6) + unsigned(ap_const_lv32_1));
tmp_17_fu_1374_p2 <= "1" when (signed(k_reg_469) < signed(tmp_16_fu_1368_p2)) else "0";
tmp_18_fu_712_p2 <= "1" when (signed(j_1_reg_298) < signed(tmp_22_fu_699_p6)) else "0";
tmp_19_fu_1331_p1 <= tmp_12_fu_1314_p2(12 - 1 downto 0);
tmp_1_fu_606_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_20_fu_897_p2 <= "1" when (signed(i_4_reg_344) < signed(tmp_25_fu_884_p6)) else "0";
tmp_23_fu_1343_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1323_p3) + unsigned(p_shl1_cast_fu_1335_p3));
tmp_24_cast_fu_737_p1 <= std_logic_vector(resize(signed(j_1_reg_298),38));
tmp_27_cast_fu_922_p1 <= std_logic_vector(resize(signed(i_4_reg_344),38));
tmp_27_fu_690_p1 <= i_3_reg_286(2 - 1 downto 0);
tmp_28_fu_791_p2 <= "1" when (signed(k_1_cast_fu_787_p1) < signed(tmp_26_reg_1534)) else "0";
tmp_29_fu_970_p2 <= "1" when (signed(j_2_cast_fu_966_p1) < signed(tmp_54_reg_1630)) else "0";
tmp_2_fu_1404_p2 <= "1" when (signed(i_cast_fu_1400_p1) < signed(P_config_read_reg_1470)) else "0";
tmp_30_fu_1026_p2 <= "1" when (signed(i_5_cast_fu_1022_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_31_fu_682_p1 <= tmp_11_fu_676_p2(9 - 1 downto 0);
tmp_33_fu_694_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_31_reg_1501))), 9));
tmp_34_fu_853_p1 <= tmp_34_neg_fu_847_p2;
tmp_34_neg_fu_847_p2 <= (tmp_34_to_int_fu_843_p1 xor ap_const_lv32_80000000);
tmp_34_to_int_fu_843_p1 <= reg_574;
tmp_3_fu_633_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),64));
tmp_40_fu_686_p1 <= tmp_11_fu_676_p2(2 - 1 downto 0);
tmp_46_fu_871_p1 <= grp_fu_666_p2(9 - 1 downto 0);
tmp_48_fu_1051_p2 <= "1" when (P_mode_read_reg_1443 = ap_const_lv32_3) else "0";
tmp_49_fu_1113_p2 <= "1" when (signed(i_6_cast_fu_1109_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_4_cast_fu_1310_p1 <= std_logic_vector(resize(signed(j_reg_458),38));
tmp_4_fu_1415_p1 <= i_reg_480(2 - 1 downto 0);
tmp_50_fu_1060_p2 <= "1" when (signed(p_netOut_2_cast_fu_1056_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_51_fu_875_p1 <= grp_fu_666_p2(38 - 1 downto 0);
tmp_52_fu_672_p1 <= tmp_13_fu_657_p2(2 - 1 downto 0);
tmp_53_fu_863_p1 <= tmp_15_fu_858_p2(9 - 1 downto 0);
tmp_55_fu_1230_p2 <= "1" when (signed(j_3_reg_435) < signed(tmp_66_fu_1217_p6)) else "0";
tmp_56_fu_879_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_53_reg_1589))), 9));
tmp_57_fu_1132_p4 <= p_uOut_load_3_to_int_fu_1128_p1(30 downto 23);
tmp_58_fu_867_p1 <= tmp_15_fu_858_p2(2 - 1 downto 0);
tmp_59_fu_1149_p4 <= p_uOut_load_4_to_int_fu_1146_p1(30 downto 23);
tmp_60_fu_1386_p1 <= k_reg_469(14 - 1 downto 0);
tmp_61_fu_1175_p2 <= (notrhs_fu_1169_p2 or notlhs_fu_1163_p2);
tmp_62_fu_1193_p2 <= (notrhs2_fu_1187_p2 or notlhs1_fu_1181_p2);
tmp_63_fu_1199_p2 <= (tmp_61_fu_1175_p2 and tmp_62_fu_1193_p2);
tmp_64_fu_515_opcode <= ap_const_lv5_2;
tmp_65_fu_1205_p2 <= (tmp_63_fu_1199_p2 and tmp_64_fu_515_p2);
tmp_67_fu_1390_p2 <= std_logic_vector(unsigned(tmp_23_reg_1804) + unsigned(tmp_60_fu_1386_p1));
tmp_68_fu_741_p2 <= std_logic_vector(signed(tmp_24_cast_fu_737_p1) + signed(tmp_24_reg_1511));
tmp_69_fu_751_p1 <= tmp_68_fu_741_p2(9 - 1 downto 0);
tmp_6_fu_1260_p2 <= "1" when (signed(i_1_cast_fu_1256_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_70_fu_763_p1 <= tmp_68_fu_741_p2(12 - 1 downto 0);
tmp_71_fu_775_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_755_p3) + unsigned(p_shl3_cast_fu_767_p3));
tmp_72_fu_926_p2 <= std_logic_vector(signed(tmp_27_cast_fu_922_p1) + signed(tmp_51_reg_1606));
tmp_73_fu_936_p1 <= tmp_72_fu_926_p2(9 - 1 downto 0);
tmp_74_fu_948_p1 <= tmp_72_fu_926_p2(12 - 1 downto 0);
tmp_75_fu_960_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_940_p3) + unsigned(p_shl5_cast_fu_952_p3));
tmp_76_cast_fu_1395_p1 <= std_logic_vector(resize(unsigned(tmp_67_fu_1390_p2),64));
tmp_76_fu_1037_p1 <= i_5_reg_378(9 - 1 downto 0);
tmp_77_cast_fu_746_p1 <= std_logic_vector(resize(signed(tmp_68_fu_741_p2),64));
tmp_77_fu_1041_p2 <= std_logic_vector(unsigned(tmp_46_reg_1599) + unsigned(tmp_76_fu_1037_p1));
tmp_78_fu_802_p1 <= k_1_reg_321(9 - 1 downto 0);
tmp_79_fu_806_p1 <= k_1_reg_321(14 - 1 downto 0);
tmp_7_fu_622_p2 <= "1" when (signed(i_2_cast_fu_618_p1) < signed(ST_layerSize_0_load_reg_1465)) else "0";
tmp_80_fu_810_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_79_fu_806_p1));
tmp_81_cast_fu_931_p1 <= std_logic_vector(resize(signed(tmp_72_fu_926_p2),64));
tmp_81_fu_820_p2 <= std_logic_vector(unsigned(tmp_33_reg_1521) + unsigned(tmp_78_fu_802_p1));
tmp_82_fu_830_p1 <= tmp_26_reg_1534(14 - 1 downto 0);
tmp_83_fu_833_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_82_fu_830_p1));
tmp_84_fu_981_p1 <= j_2_reg_367(9 - 1 downto 0);
tmp_85_cast_fu_815_p1 <= std_logic_vector(resize(unsigned(tmp_80_fu_810_p2),64));
tmp_85_fu_985_p1 <= j_2_reg_367(14 - 1 downto 0);
tmp_86_cast_fu_825_p1 <= std_logic_vector(resize(signed(tmp_81_fu_820_p2),64));
tmp_86_fu_989_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_85_fu_985_p1));
tmp_87_cast_fu_838_p1 <= std_logic_vector(resize(unsigned(tmp_83_fu_833_p2),64));
tmp_87_fu_999_p2 <= std_logic_vector(unsigned(tmp_56_reg_1611) + unsigned(tmp_84_fu_981_p1));
tmp_88_cast_fu_994_p1 <= std_logic_vector(resize(unsigned(tmp_86_fu_989_p2),64));
tmp_88_fu_1009_p1 <= tmp_54_reg_1630(14 - 1 downto 0);
tmp_89_cast_fu_1004_p1 <= std_logic_vector(resize(signed(tmp_87_fu_999_p2),64));
tmp_89_fu_1012_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_88_fu_1009_p1));
tmp_90_cast_fu_1017_p1 <= std_logic_vector(resize(unsigned(tmp_89_fu_1012_p2),64));
tmp_90_fu_1099_p1 <= phi_mul_reg_424(9 - 1 downto 0);
tmp_91_cast_fu_1046_p1 <= std_logic_vector(resize(signed(tmp_77_fu_1041_p2),64));
tmp_91_fu_1124_p1 <= i_6_reg_413(2 - 1 downto 0);
tmp_92_fu_1065_p1 <= p_netOut_2_reg_402(9 - 1 downto 0);
tmp_93_cast_fu_1074_p1 <= std_logic_vector(resize(signed(tmp_93_fu_1069_p2),64));
tmp_93_fu_1069_p2 <= std_logic_vector(unsigned(tmp_92_fu_1065_p1) + unsigned(tmp_46_reg_1599));
tmp_94_cast_fu_1088_p1 <= std_logic_vector(resize(signed(tmp_94_fu_1083_p2),64));
tmp_94_fu_1083_p2 <= std_logic_vector(unsigned(tmp_96_fu_1079_p1) + unsigned(tmp_46_reg_1599));
tmp_95_cast_fu_1251_p1 <= std_logic_vector(resize(unsigned(tmp_95_fu_1246_p2),64));
tmp_95_fu_1246_p2 <= std_logic_vector(unsigned(tmp_90_reg_1720) + unsigned(tmp_99_fu_1242_p1));
tmp_96_fu_1079_p1 <= p_netOut_reg_389(9 - 1 downto 0);
tmp_97_fu_1142_p1 <= p_uOut_load_3_to_int_fu_1128_p1(23 - 1 downto 0);
tmp_98_fu_1159_p1 <= p_uOut_load_4_to_int_fu_1146_p1(23 - 1 downto 0);
tmp_99_fu_1242_p1 <= j_3_reg_435(9 - 1 downto 0);
tmp_9_fu_642_p2 <= "1" when (signed(i_3_cast_fu_638_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_9_t_fu_1279_p2 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_10_fu_1275_p1));
tmp_fu_596_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_s_fu_1298_p2 <= "1" when (signed(j_reg_458) < signed(tmp_5_fu_1285_p6)) else "0";
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_config_TVALID : IN STD_LOGIC;
P_config_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_netOut_TVALID : OUT STD_LOGIC;
P_netOut_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=42,HLS_SYN_FF=8905,HLS_SYN_LUT=12500}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (153 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (153 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (153 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (153 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (153 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (153 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (153 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (153 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (153 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (153 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_7C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111100";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_96 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010110";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv37_0 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000000";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv38_23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100011";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv39_23 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000100011";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv37_23 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100011";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_550 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_253 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal ap_sig_cseq_ST_st125_fsm_124 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal reg_557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_285 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_294 : BOOLEAN;
signal grp_fu_498_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_563 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_311 : BOOLEAN;
signal grp_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_328 : BOOLEAN;
signal reg_574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_337 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_344 : BOOLEAN;
signal grp_fu_512_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_354 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_361 : BOOLEAN;
signal grp_fu_529_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_371 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_378 : BOOLEAN;
signal grp_fu_509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_388 : BOOLEAN;
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_395 : BOOLEAN;
signal P_mode_read_reg_1443 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_408 : BOOLEAN;
signal tmp_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_load_reg_1452 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1461 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_0_load_reg_1465 : STD_LOGIC_VECTOR (31 downto 0);
signal P_config_read_reg_1470 : STD_LOGIC_VECTOR (31 downto 0);
signal i_8_fu_627_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_432 : BOOLEAN;
signal tmp_7_fu_622_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_439 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_449 : BOOLEAN;
signal tmp_9_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_672_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_52_reg_1496 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_31_fu_682_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_reg_1501 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_467 : BOOLEAN;
signal tmp_40_fu_686_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_40_reg_1506 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_651_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_24_reg_1511 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_478 : BOOLEAN;
signal tmp_27_fu_690_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_reg_1516 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_33_fu_694_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_reg_1521 : STD_LOGIC_VECTOR (8 downto 0);
signal j_5_fu_718_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_491 : BOOLEAN;
signal tmp_26_fu_724_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_reg_1534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_71_fu_775_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_reg_1540 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_2_reg_1546 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_781_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_fu_796_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_reg_1559 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_513 : BOOLEAN;
signal tmp_28_fu_791_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_519_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_37_reg_1579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_533 : BOOLEAN;
signal grp_fu_524_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_reg_1584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_542 : BOOLEAN;
signal tmp_53_fu_863_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_reg_1589 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_551 : BOOLEAN;
signal tmp_58_fu_867_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_58_reg_1594 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_46_fu_871_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_reg_1599 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_562 : BOOLEAN;
signal tmp_51_fu_875_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_51_reg_1606 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_56_fu_879_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_56_reg_1611 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_fu_884_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_1616 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_575 : BOOLEAN;
signal i_12_fu_903_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1625 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_909_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_1630 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_75_fu_960_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_75_reg_1636 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_4_reg_1642 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_975_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_6_reg_1650 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_596 : BOOLEAN;
signal tmp_29_fu_970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_615 : BOOLEAN;
signal i_11_fu_1031_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_11_reg_1678 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_624 : BOOLEAN;
signal p_uOut_addr_5_reg_1683 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_30_fu_1026_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_fu_1051_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_reg_1688 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_504_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_1692 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_642 : BOOLEAN;
signal p_netOut_2_cast_fu_1056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_cast_reg_1697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_651 : BOOLEAN;
signal tmp_50_fu_1060_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_TREADY : STD_LOGIC;
signal i_15_fu_1093_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_15_reg_1715 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_90_fu_1099_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_90_reg_1720 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1103_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal next_mul_reg_1725 : STD_LOGIC_VECTOR (36 downto 0);
signal i_14_fu_1118_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_14_reg_1733 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_91_fu_1124_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_91_reg_1738 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_49_fu_1113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_reg_1743 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_1205_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_65_reg_1749 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_701 : BOOLEAN;
signal p_netOut_1_fu_1211_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_710 : BOOLEAN;
signal j_7_fu_1236_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_7_reg_1762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_719 : BOOLEAN;
signal tmp_55_fu_1230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_1260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1772 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_734 : BOOLEAN;
signal grp_fu_1269_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_8_reg_1781 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st151_fsm_150 : STD_LOGIC;
signal ap_sig_bdd_748 : BOOLEAN;
signal tmp_10_fu_1275_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_10_reg_1786 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_fu_1279_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_reg_1791 : STD_LOGIC_VECTOR (1 downto 0);
signal j_4_fu_1304_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_4_reg_1799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st152_fsm_151 : STD_LOGIC;
signal ap_sig_bdd_761 : BOOLEAN;
signal tmp_23_fu_1343_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_reg_1804 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_s_fu_1298_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1349_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_2_fu_1380_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st153_fsm_152 : STD_LOGIC;
signal ap_sig_bdd_779 : BOOLEAN;
signal tmp_17_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_786 : BOOLEAN;
signal tmp_2_fu_1404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_1822 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_796 : BOOLEAN;
signal ap_sig_bdd_801 : BOOLEAN;
signal i_7_fu_1409_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_275 : STD_LOGIC_VECTOR (30 downto 0);
signal i_3_reg_286 : STD_LOGIC_VECTOR (30 downto 0);
signal j_1_reg_298 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_832 : BOOLEAN;
signal sum_reg_309 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_321 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_332 : STD_LOGIC_VECTOR (31 downto 0);
signal i_4_reg_344 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_355 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_367 : STD_LOGIC_VECTOR (30 downto 0);
signal i_5_reg_378 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_853 : BOOLEAN;
signal p_netOut_reg_389 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_reg_402 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_413 : STD_LOGIC_VECTOR (30 downto 0);
signal phi_mul_reg_424 : STD_LOGIC_VECTOR (36 downto 0);
signal j_3_reg_435 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_879 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_446 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_458 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_469 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_480 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_3_fu_633_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_746_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_838_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_931_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_994_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1017_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1046_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1074_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_94_cast_fu_1088_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_95_cast_fu_1251_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_1395_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_1415_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_997 : BOOLEAN;
signal grp_fu_491_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_1021 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_1028 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_1036 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_1043 : BOOLEAN;
signal grp_fu_509_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_512_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_fu_853_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_cast_fu_618_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_cast_fu_638_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_651_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_651_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_13_fu_657_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_11_fu_676_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_22_fu_699_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_cast_fu_737_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_68_fu_741_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_69_fu_751_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_763_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_755_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_767_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal k_1_cast_fu_787_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_806_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_fu_810_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_802_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_fu_820_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_82_fu_830_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_83_fu_833_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_34_to_int_fu_843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_neg_fu_847_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_858_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p2 : STD_LOGIC_VECTOR (38 downto 0);
signal tmp_27_cast_fu_922_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_72_fu_926_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_73_fu_936_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_fu_948_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_940_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_952_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal j_2_cast_fu_966_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_985_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_86_fu_989_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_84_fu_981_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_999_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_88_fu_1009_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1012_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_5_cast_fu_1022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_1037_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1041_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_92_fu_1065_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_fu_1069_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_96_fu_1079_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_94_fu_1083_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_6_cast_fu_1109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_3_to_int_fu_1128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_to_int_fu_1146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_1132_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_fu_1142_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_1169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_1149_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_98_fu_1159_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_1187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_1175_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_1193_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_63_fu_1199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_515_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_1217_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_1242_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_95_fu_1246_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_1_cast_fu_1256_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1269_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_1269_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_1285_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_cast_fu_1310_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_12_fu_1314_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_14_fu_1319_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1331_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl_cast_fu_1323_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_1335_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_fu_1355_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_1368_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_1386_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_67_fu_1390_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_cast_fu_1400_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_ce : STD_LOGIC;
signal grp_fu_498_ce : STD_LOGIC;
signal grp_fu_504_ce : STD_LOGIC;
signal tmp_64_fu_515_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_519_ce : STD_LOGIC;
signal grp_fu_524_ce : STD_LOGIC;
signal grp_fu_529_ce : STD_LOGIC;
signal grp_fu_651_ce : STD_LOGIC;
signal grp_fu_666_ce : STD_LOGIC;
signal grp_fu_1269_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (153 downto 0);
signal grp_fu_1269_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal grp_fu_651_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_bdd_976 : BOOLEAN;
component feedforward_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mul_7ns_31ns_38_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (30 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (37 downto 0) );
end component;
component feedforward_mul_7ns_32s_39_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (38 downto 0) );
end component;
component feedforward_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode => P_mode);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 32,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0 : component feedforward_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_491_p0,
din1 => grp_fu_491_p1,
ce => grp_fu_491_ce,
dout => grp_fu_491_p2);
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1 : component feedforward_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => p_uOut_q0,
din1 => ST_WandB_q0,
ce => grp_fu_498_ce,
dout => grp_fu_498_p2);
feedforward_fdiv_32ns_32ns_32_16_U2 : component feedforward_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_550,
din1 => sumsoft_reg_332,
ce => grp_fu_504_ce,
dout => grp_fu_504_p2);
feedforward_fptrunc_64ns_32_1_U3 : component feedforward_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_509_p0,
dout => grp_fu_509_p1);
feedforward_fpext_32ns_64_1_U4 : component feedforward_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_512_p0,
dout => grp_fu_512_p1);
feedforward_fcmp_32ns_32ns_1_1_U5 : component feedforward_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_550,
din1 => p_uOut_load_4_reg_1743,
opcode => tmp_64_fu_515_opcode,
dout => tmp_64_fu_515_p2);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_584,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_519_ce,
dout => grp_fu_519_p2);
feedforward_ddiv_64ns_64ns_64_31_U7 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_37_reg_1579,
ce => grp_fu_524_ce,
dout => grp_fu_524_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_579,
ce => grp_fu_529_ce,
dout => grp_fu_529_p2);
feedforward_mul_7ns_31ns_38_3_U9 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_651_p0,
din1 => grp_fu_651_p1,
ce => grp_fu_651_ce,
dout => grp_fu_651_p2);
feedforward_mul_7ns_32s_39_3_U10 : component feedforward_mul_7ns_32s_39_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 32,
dout_WIDTH => 39)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_666_p0,
din1 => tmp_13_fu_657_p2,
ce => grp_fu_666_ce,
dout => grp_fu_666_p2);
feedforward_mux_4to1_sel2_32_1_U11 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_27_reg_1516,
dout => tmp_22_fu_699_p6);
feedforward_mux_4to1_sel2_32_1_U12 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_40_reg_1506,
dout => tmp_26_fu_724_p6);
feedforward_mux_4to1_sel2_32_1_U13 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_52_reg_1496,
dout => tmp_25_fu_884_p6);
feedforward_mux_4to1_sel2_32_1_U14 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_58_reg_1594,
dout => tmp_54_fu_909_p6);
feedforward_mux_4to1_sel2_32_1_U15 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_91_reg_1738,
dout => tmp_66_fu_1217_p6);
feedforward_mul_7ns_31ns_38_3_U16 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1269_p0,
din1 => grp_fu_1269_p1,
ce => grp_fu_1269_ce,
dout => grp_fu_1269_p2);
feedforward_mux_4to1_sel2_32_1_U17 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_10_reg_1786,
dout => tmp_5_fu_1285_p6);
feedforward_mux_4to1_sel2_32_1_U18 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_9_t_reg_1791,
dout => tmp_21_fu_1355_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_TREADY assign process. --
ap_reg_ioackin_P_netOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_976) then
if (not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_TREADY)) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_446 assign process. --
i_1_reg_446_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
i_1_reg_446 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and (ap_const_lv1_0 = tmp_s_fu_1298_p2))) then
i_1_reg_446 <= i_9_fu_1349_p2;
end if;
end if;
end process;
-- i_2_reg_275 assign process. --
i_2_reg_275_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
i_2_reg_275 <= ap_const_lv31_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
i_2_reg_275 <= i_8_fu_627_p2;
end if;
end if;
end process;
-- i_3_reg_286 assign process. --
i_3_reg_286_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
i_3_reg_286 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_18_fu_712_p2))) then
i_3_reg_286 <= i_10_fu_781_p2;
end if;
end if;
end process;
-- i_4_reg_344 assign process. --
i_4_reg_344_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
i_4_reg_344 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
i_4_reg_344 <= i_12_reg_1625;
end if;
end if;
end process;
-- i_5_reg_378 assign process. --
i_5_reg_378_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_20_fu_897_p2))) then
i_5_reg_378 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
i_5_reg_378 <= i_11_reg_1678;
end if;
end if;
end process;
-- i_6_reg_413 assign process. --
i_6_reg_413_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
i_6_reg_413 <= i_14_reg_1733;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
i_6_reg_413 <= ap_const_lv31_0;
end if;
end if;
end process;
-- i_reg_480 assign process. --
i_reg_480_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
i_reg_480 <= i_7_fu_1409_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
i_reg_480 <= ap_const_lv31_0;
end if;
end if;
end process;
-- j_1_reg_298 assign process. --
j_1_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
j_1_reg_298 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
j_1_reg_298 <= j_5_reg_1529;
end if;
end if;
end process;
-- j_2_reg_367 assign process. --
j_2_reg_367_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
j_2_reg_367 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
j_2_reg_367 <= j_6_reg_1650;
end if;
end if;
end process;
-- j_3_reg_435 assign process. --
j_3_reg_435_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
j_3_reg_435 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_435 <= j_7_reg_1762;
end if;
end if;
end process;
-- j_reg_458 assign process. --
j_reg_458_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and (ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
j_reg_458 <= j_4_reg_1799;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
j_reg_458 <= ap_const_lv32_0;
end if;
end if;
end process;
-- k_1_reg_321 assign process. --
k_1_reg_321_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
k_1_reg_321 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
k_1_reg_321 <= k_3_reg_1559;
end if;
end if;
end process;
-- k_reg_469 assign process. --
k_reg_469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
k_reg_469 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
k_reg_469 <= k_2_fu_1380_p2;
end if;
end if;
end process;
-- p_netOut_2_reg_402 assign process. --
p_netOut_2_reg_402_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_2_reg_402 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_2_reg_402 <= i_15_reg_1715;
end if;
end if;
end process;
-- p_netOut_reg_389 assign process. --
p_netOut_reg_389_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_reg_389 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_reg_389 <= p_netOut_1_fu_1211_p3;
end if;
end if;
end process;
-- phi_mul_reg_424 assign process. --
phi_mul_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
phi_mul_reg_424 <= next_mul_reg_1725;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
phi_mul_reg_424 <= ap_const_lv37_0;
end if;
end if;
end process;
-- sum_1_reg_355 assign process. --
sum_1_reg_355_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
sum_1_reg_355 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
sum_1_reg_355 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sum_reg_309 assign process. --
sum_reg_309_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
sum_reg_309 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
sum_reg_309 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sumsoft_reg_332 assign process. --
sumsoft_reg_332_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
sumsoft_reg_332 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
sumsoft_reg_332 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
P_config_read_reg_1470 <= P_config_TDATA;
ST_numLayer <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_408))) then
P_mode_read_reg_1443 <= P_mode;
ST_numLayer_load_reg_1452 <= ST_numLayer;
tmp_reg_1448 <= tmp_fu_596_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ST_layerSize_0_load_reg_1465 <= ST_layerSize_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and not((tmp_4_fu_1415_p1 = ap_const_lv2_2)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_1)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
i_11_reg_1678 <= i_11_fu_1031_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
i_12_reg_1625 <= i_12_fu_903_p2;
tmp_25_reg_1616 <= tmp_25_fu_884_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)))) then
i_14_reg_1733 <= i_14_fu_1118_p2;
next_mul_reg_1725 <= next_mul_fu_1103_p2;
tmp_90_reg_1720 <= tmp_90_fu_1099_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
i_15_reg_1715 <= i_15_fu_1093_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) then
j_4_reg_1799 <= j_4_fu_1304_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
j_5_reg_1529 <= j_5_fu_718_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
j_6_reg_1650 <= j_6_fu_975_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
j_7_reg_1762 <= j_7_fu_1236_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
k_3_reg_1559 <= k_3_fu_796_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))))) then
p_netOut_2_cast_reg_1697(30 downto 0) <= p_netOut_2_cast_fu_1056_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
p_uOut_addr_2_reg_1546 <= tmp_77_cast_fu_746_p1(8 - 1 downto 0);
tmp_26_reg_1534 <= tmp_26_fu_724_p6;
tmp_71_reg_1540(13 downto 2) <= tmp_71_fu_775_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
p_uOut_addr_4_reg_1642 <= tmp_81_cast_fu_931_p1(8 - 1 downto 0);
tmp_54_reg_1630 <= tmp_54_fu_909_p6;
tmp_75_reg_1636(13 downto 2) <= tmp_75_fu_960_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and not((ap_const_lv1_0 = tmp_30_fu_1026_p2)))) then
p_uOut_addr_5_reg_1683 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) then
p_uOut_load_4_reg_1743 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124) or (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143))) then
reg_550 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
reg_557 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
reg_563 <= grp_fu_498_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_574 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
reg_579 <= grp_fu_512_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
reg_584 <= grp_fu_529_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
reg_590 <= grp_fu_509_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
tmp_10_reg_1786 <= tmp_10_fu_1275_p1;
tmp_8_reg_1781 <= grp_fu_1269_p2;
tmp_9_t_reg_1791 <= tmp_9_t_fu_1279_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408))) then
tmp_1_reg_1461 <= tmp_1_fu_606_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
tmp_23_reg_1804(13 downto 2) <= tmp_23_fu_1343_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_24_reg_1511 <= grp_fu_651_p2;
tmp_27_reg_1516 <= tmp_27_fu_690_p1;
tmp_33_reg_1521 <= tmp_33_fu_694_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not(ap_sig_bdd_801))) then
tmp_2_reg_1822 <= tmp_2_fu_1404_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_31_reg_1501 <= tmp_31_fu_682_p1;
tmp_40_reg_1506 <= tmp_40_fu_686_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) then
tmp_37_reg_1579 <= grp_fu_519_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
tmp_38_reg_1584 <= grp_fu_524_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
tmp_46_reg_1599 <= tmp_46_fu_871_p1;
tmp_51_reg_1606 <= tmp_51_fu_875_p1;
tmp_56_reg_1611 <= tmp_56_fu_879_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
tmp_47_reg_1692 <= grp_fu_504_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2))) then
tmp_48_reg_1688 <= tmp_48_fu_1051_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_9_fu_642_p2))) then
tmp_52_reg_1496 <= tmp_52_fu_672_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
tmp_53_reg_1589 <= tmp_53_fu_863_p1;
tmp_58_reg_1594 <= tmp_58_fu_867_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) then
tmp_65_reg_1749 <= tmp_65_fu_1205_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) then
tmp_6_reg_1772 <= tmp_6_fu_1260_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
tmp_91_reg_1738 <= tmp_91_fu_1124_p1;
end if;
end if;
end process;
tmp_71_reg_1540(1 downto 0) <= "00";
tmp_75_reg_1636(1 downto 0) <= "00";
p_netOut_2_cast_reg_1697(31) <= '0';
tmp_23_reg_1804(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_596_p2, ap_sig_bdd_408, tmp_reg_1448, tmp_1_fu_606_p2, tmp_1_reg_1461, tmp_7_fu_622_p2, ap_sig_bdd_439, tmp_9_fu_642_p2, tmp_18_fu_712_p2, tmp_28_fu_791_p2, tmp_20_fu_897_p2, tmp_29_fu_970_p2, tmp_30_fu_1026_p2, tmp_48_reg_1688, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_55_fu_1230_p2, tmp_6_fu_1260_p2, tmp_6_reg_1772, tmp_s_fu_1298_p2, tmp_17_fu_1374_p2, ap_sig_bdd_786, tmp_2_fu_1404_p2, tmp_2_reg_1822, ap_sig_bdd_801, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_9_fu_642_p2)) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = tmp_18_fu_712_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_28_fu_791_p2)) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
if (not((ap_const_lv1_0 = tmp_20_fu_897_p2))) then
ap_NS_fsm <= ap_ST_st83_fsm_82;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st83_fsm_82 =>
if ((ap_const_lv1_0 = tmp_29_fu_970_p2)) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st84_fsm_83;
end if;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st124_fsm_123 =>
if ((ap_const_lv1_0 = tmp_30_fu_1026_p2)) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st125_fsm_124;
end if;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st143_fsm_142 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st147_fsm_146 =>
if (not((ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st148_fsm_147 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (not((ap_const_lv1_0 = tmp_6_fu_1260_p2))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st151_fsm_150;
when ap_ST_st151_fsm_150 =>
ap_NS_fsm <= ap_ST_st152_fsm_151;
when ap_ST_st152_fsm_151 =>
if ((ap_const_lv1_0 = tmp_s_fu_1298_p2)) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st153_fsm_152 =>
if ((not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st153_fsm_152;
elsif (((ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st152_fsm_151;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st154_fsm_153 =>
if ((not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((ap_const_lv1_0 = tmp_2_fu_1404_p2) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st154_fsm_153;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_TREADY assign process. --
P_config_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_596_p2, ap_sig_bdd_408, tmp_2_fu_1404_p2, ap_sig_cseq_ST_st154_fsm_153, ap_sig_bdd_801)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801)))) then
P_config_TREADY <= ap_const_logic_1;
else
P_config_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_TDATA <= p_netOut_reg_389;
-- P_netOut_TVALID assign process. --
P_netOut_TVALID_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_reg_ioackin_P_netOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY))) then
P_netOut_TVALID <= ap_const_logic_1;
else
P_netOut_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, tmp_85_cast_fu_815_p1, tmp_87_cast_fu_838_p1, tmp_88_cast_fu_994_p1, tmp_90_cast_fu_1017_p1, tmp_76_cast_fu_1395_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) then
ST_WandB_address0 <= tmp_76_cast_fu_1395_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2))) then
ST_WandB_address0 <= tmp_90_cast_fu_1017_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_994_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2))) then
ST_WandB_address0 <= tmp_87_cast_fu_838_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2)))) then
ST_WandB_address0 <= tmp_85_cast_fu_815_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not(ap_sig_bdd_786)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1021 assign process. --
ap_sig_bdd_1021_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1021 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_1028 assign process. --
ap_sig_bdd_1028_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1028 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_1036 assign process. --
ap_sig_bdd_1036_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1036 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_1043 assign process. --
ap_sig_bdd_1043_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1043 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_172 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_253 assign process. --
ap_sig_bdd_253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_253 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(124 downto 124));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_285 assign process. --
ap_sig_bdd_285_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_285 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_294 assign process. --
ap_sig_bdd_294_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_294 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_304 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_311 assign process. --
ap_sig_bdd_311_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_311 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_321 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_328 assign process. --
ap_sig_bdd_328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_328 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_337 assign process. --
ap_sig_bdd_337_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_337 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_344 assign process. --
ap_sig_bdd_344_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_344 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_354 assign process. --
ap_sig_bdd_354_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_354 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_361 assign process. --
ap_sig_bdd_361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_361 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_371 assign process. --
ap_sig_bdd_371_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_371 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_378 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_388 assign process. --
ap_sig_bdd_388_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_388 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_395 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_408 assign process. --
ap_sig_bdd_408_assign_proc : process(ap_start, P_config_TVALID, tmp_fu_596_p2)
begin
ap_sig_bdd_408 <= (((P_config_TVALID = ap_const_logic_0) and not((tmp_fu_596_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_432 assign process. --
ap_sig_bdd_432_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_432 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_439 assign process. --
ap_sig_bdd_439_assign_proc : process(P_netIn_TVALID, tmp_7_fu_622_p2)
begin
ap_sig_bdd_439 <= ((P_netIn_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)));
end process;
-- ap_sig_bdd_449 assign process. --
ap_sig_bdd_449_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_449 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_467 assign process. --
ap_sig_bdd_467_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_467 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_478 assign process. --
ap_sig_bdd_478_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_478 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_491 assign process. --
ap_sig_bdd_491_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_491 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_513 assign process. --
ap_sig_bdd_513_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_513 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_533 assign process. --
ap_sig_bdd_533_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_533 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_542 assign process. --
ap_sig_bdd_542_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_542 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_551 assign process. --
ap_sig_bdd_551_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_551 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_562 assign process. --
ap_sig_bdd_562_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_562 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_575 assign process. --
ap_sig_bdd_575_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_575 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_596 assign process. --
ap_sig_bdd_596_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_596 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_615 assign process. --
ap_sig_bdd_615_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_615 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_624 assign process. --
ap_sig_bdd_624_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_624 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_642 assign process. --
ap_sig_bdd_642_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_642 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_651 assign process. --
ap_sig_bdd_651_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_651 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_701 assign process. --
ap_sig_bdd_701_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_701 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_710 assign process. --
ap_sig_bdd_710_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_710 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_719 assign process. --
ap_sig_bdd_719_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_719 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_734 assign process. --
ap_sig_bdd_734_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_734 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_748 assign process. --
ap_sig_bdd_748_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_748 <= (ap_const_lv1_1 = ap_CS_fsm(150 downto 150));
end process;
-- ap_sig_bdd_761 assign process. --
ap_sig_bdd_761_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_761 <= (ap_const_lv1_1 = ap_CS_fsm(151 downto 151));
end process;
-- ap_sig_bdd_779 assign process. --
ap_sig_bdd_779_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_779 <= (ap_const_lv1_1 = ap_CS_fsm(152 downto 152));
end process;
-- ap_sig_bdd_786 assign process. --
ap_sig_bdd_786_assign_proc : process(P_WandB_TVALID, tmp_17_fu_1374_p2)
begin
ap_sig_bdd_786 <= ((P_WandB_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)));
end process;
-- ap_sig_bdd_796 assign process. --
ap_sig_bdd_796_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_796 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_801 assign process. --
ap_sig_bdd_801_assign_proc : process(P_config_TVALID, tmp_2_fu_1404_p2)
begin
ap_sig_bdd_801 <= ((P_config_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)));
end process;
-- ap_sig_bdd_832 assign process. --
ap_sig_bdd_832_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_832 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_853 assign process. --
ap_sig_bdd_853_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_853 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_879 assign process. --
ap_sig_bdd_879_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_879 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_976 assign process. --
ap_sig_bdd_976_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2)
begin
ap_sig_bdd_976 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2));
end process;
-- ap_sig_bdd_997 assign process. --
ap_sig_bdd_997_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_997 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_378)
begin
if (ap_sig_bdd_378) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_395)
begin
if (ap_sig_bdd_395) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_997)
begin
if (ap_sig_bdd_997) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_304)
begin
if (ap_sig_bdd_304) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_615)
begin
if (ap_sig_bdd_615) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_624)
begin
if (ap_sig_bdd_624) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st125_fsm_124 assign process. --
ap_sig_cseq_ST_st125_fsm_124_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_1021)
begin
if (ap_sig_bdd_1021) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_642)
begin
if (ap_sig_bdd_642) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_853)
begin
if (ap_sig_bdd_853) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_651)
begin
if (ap_sig_bdd_651) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_701)
begin
if (ap_sig_bdd_701) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_710)
begin
if (ap_sig_bdd_710) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_719)
begin
if (ap_sig_bdd_719) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_879)
begin
if (ap_sig_bdd_879) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st151_fsm_150 assign process. --
ap_sig_cseq_ST_st151_fsm_150_assign_proc : process(ap_sig_bdd_748)
begin
if (ap_sig_bdd_748) then
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st152_fsm_151 assign process. --
ap_sig_cseq_ST_st152_fsm_151_assign_proc : process(ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) then
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st153_fsm_152 assign process. --
ap_sig_cseq_ST_st153_fsm_152_assign_proc : process(ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) then
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_796)
begin
if (ap_sig_bdd_796) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_321)
begin
if (ap_sig_bdd_321) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_285)
begin
if (ap_sig_bdd_285) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_1028)
begin
if (ap_sig_bdd_1028) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_172)
begin
if (ap_sig_bdd_172) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_337)
begin
if (ap_sig_bdd_337) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_354)
begin
if (ap_sig_bdd_354) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_432)
begin
if (ap_sig_bdd_432) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_449)
begin
if (ap_sig_bdd_449) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_371)
begin
if (ap_sig_bdd_371) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_533)
begin
if (ap_sig_bdd_533) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_467)
begin
if (ap_sig_bdd_467) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_478)
begin
if (ap_sig_bdd_478) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_542)
begin
if (ap_sig_bdd_542) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_388)
begin
if (ap_sig_bdd_388) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_832)
begin
if (ap_sig_bdd_832) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_513)
begin
if (ap_sig_bdd_513) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_551)
begin
if (ap_sig_bdd_551) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_562)
begin
if (ap_sig_bdd_562) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_575)
begin
if (ap_sig_bdd_575) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_596)
begin
if (ap_sig_bdd_596) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_311)
begin
if (ap_sig_bdd_311) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_1036)
begin
if (ap_sig_bdd_1036) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_328)
begin
if (ap_sig_bdd_328) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_294)
begin
if (ap_sig_bdd_294) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_1043)
begin
if (ap_sig_bdd_1043) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_344)
begin
if (ap_sig_bdd_344) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_361)
begin
if (ap_sig_bdd_361) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_TREADY assign process. --
ap_sig_ioackin_P_netOut_TREADY_assign_proc : process(P_netOut_TREADY, ap_reg_ioackin_P_netOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY)) then
ap_sig_ioackin_P_netOut_TREADY <= P_netOut_TREADY;
else
ap_sig_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_1269_ce <= ap_const_logic_1;
grp_fu_1269_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_1269_p1 <= grp_fu_1269_p10(31 - 1 downto 0);
grp_fu_1269_p10 <= std_logic_vector(resize(unsigned(i_1_reg_446),38));
grp_fu_491_ce <= ap_const_logic_1;
-- grp_fu_491_p0 assign process. --
grp_fu_491_p0_assign_proc : process(sum_reg_309, sumsoft_reg_332, sum_1_reg_355, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p0 <= sumsoft_reg_332;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p0 <= sum_1_reg_355;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
grp_fu_491_p0 <= sum_reg_309;
else
grp_fu_491_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_491_p1 assign process. --
grp_fu_491_p1_assign_proc : process(reg_557, reg_563, reg_590, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p1 <= reg_590;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p1 <= reg_557;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
grp_fu_491_p1 <= reg_563;
else
grp_fu_491_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_498_ce <= ap_const_logic_1;
grp_fu_504_ce <= ap_const_logic_1;
-- grp_fu_509_p0 assign process. --
grp_fu_509_p0_assign_proc : process(reg_584, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st118_fsm_117, tmp_38_reg_1584)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_509_p0 <= reg_584;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
grp_fu_509_p0 <= tmp_38_reg_1584;
else
grp_fu_509_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_512_p0 assign process. --
grp_fu_512_p0_assign_proc : process(reg_574, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st99_fsm_98, tmp_34_fu_853_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) then
grp_fu_512_p0 <= reg_574;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
grp_fu_512_p0 <= tmp_34_fu_853_p1;
else
grp_fu_512_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_519_ce <= ap_const_logic_1;
grp_fu_524_ce <= ap_const_logic_1;
grp_fu_529_ce <= ap_const_logic_1;
grp_fu_651_ce <= ap_const_logic_1;
grp_fu_651_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_651_p1 <= grp_fu_651_p10(31 - 1 downto 0);
grp_fu_651_p10 <= std_logic_vector(resize(unsigned(i_3_reg_286),38));
grp_fu_666_ce <= ap_const_logic_1;
grp_fu_666_p0 <= ap_const_lv39_23(7 - 1 downto 0);
i_10_fu_781_p2 <= std_logic_vector(unsigned(i_3_reg_286) + unsigned(ap_const_lv31_1));
i_11_fu_1031_p2 <= std_logic_vector(unsigned(i_5_reg_378) + unsigned(ap_const_lv31_1));
i_12_fu_903_p2 <= std_logic_vector(unsigned(i_4_reg_344) + unsigned(ap_const_lv32_1));
i_14_fu_1118_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(i_6_reg_413));
i_15_fu_1093_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(p_netOut_2_reg_402));
i_1_cast_fu_1256_p1 <= std_logic_vector(resize(unsigned(i_1_reg_446),32));
i_2_cast_fu_618_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),32));
i_3_cast_fu_638_p1 <= std_logic_vector(resize(unsigned(i_3_reg_286),32));
i_5_cast_fu_1022_p1 <= std_logic_vector(resize(unsigned(i_5_reg_378),32));
i_6_cast_fu_1109_p1 <= std_logic_vector(resize(unsigned(i_6_reg_413),32));
i_7_fu_1409_p2 <= std_logic_vector(unsigned(i_reg_480) + unsigned(ap_const_lv31_1));
i_8_fu_627_p2 <= std_logic_vector(unsigned(i_2_reg_275) + unsigned(ap_const_lv31_1));
i_9_fu_1349_p2 <= std_logic_vector(unsigned(i_1_reg_446) + unsigned(ap_const_lv31_1));
i_cast_fu_1400_p1 <= std_logic_vector(resize(unsigned(i_reg_480),32));
j_2_cast_fu_966_p1 <= std_logic_vector(resize(unsigned(j_2_reg_367),32));
j_4_fu_1304_p2 <= std_logic_vector(unsigned(j_reg_458) + unsigned(ap_const_lv32_1));
j_5_fu_718_p2 <= std_logic_vector(unsigned(j_1_reg_298) + unsigned(ap_const_lv32_1));
j_6_fu_975_p2 <= std_logic_vector(unsigned(j_2_reg_367) + unsigned(ap_const_lv31_1));
j_7_fu_1236_p2 <= std_logic_vector(unsigned(j_3_reg_435) + unsigned(ap_const_lv32_1));
k_1_cast_fu_787_p1 <= std_logic_vector(resize(unsigned(k_1_reg_321),32));
k_2_fu_1380_p2 <= std_logic_vector(unsigned(k_reg_469) + unsigned(ap_const_lv32_1));
k_3_fu_796_p2 <= std_logic_vector(unsigned(k_1_reg_321) + unsigned(ap_const_lv31_1));
next_mul_fu_1103_p2 <= std_logic_vector(unsigned(ap_const_lv37_23) + unsigned(phi_mul_reg_424));
notlhs1_fu_1181_p2 <= "0" when (tmp_59_fu_1149_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_1163_p2 <= "0" when (tmp_57_fu_1132_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_1187_p2 <= "1" when (tmp_98_fu_1159_p1 = ap_const_lv23_0) else "0";
notrhs_fu_1169_p2 <= "1" when (tmp_97_fu_1142_p1 = ap_const_lv23_0) else "0";
p_netOut_1_fu_1211_p3 <=
p_netOut_2_cast_reg_1697 when (tmp_65_reg_1749(0) = '1') else
p_netOut_reg_389;
p_netOut_2_cast_fu_1056_p1 <= std_logic_vector(resize(unsigned(p_netOut_2_reg_402),32));
p_shl1_cast_fu_1335_p3 <= (tmp_19_fu_1331_p1 & ap_const_lv2_0);
p_shl2_cast_fu_755_p3 <= (tmp_69_fu_751_p1 & ap_const_lv5_0);
p_shl3_cast_fu_767_p3 <= (tmp_70_fu_763_p1 & ap_const_lv2_0);
p_shl4_cast_fu_940_p3 <= (tmp_73_fu_936_p1 & ap_const_lv5_0);
p_shl5_cast_fu_952_p3 <= (tmp_74_fu_948_p1 & ap_const_lv2_0);
p_shl_cast_fu_1323_p3 <= (tmp_14_fu_1319_p1 & ap_const_lv5_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_2_reg_1546, ap_sig_cseq_ST_st7_fsm_6, p_uOut_addr_4_reg_1642, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, p_uOut_addr_5_reg_1683, ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, tmp_3_fu_633_p1, tmp_86_cast_fu_825_p1, tmp_89_cast_fu_1004_p1, tmp_91_cast_fu_1046_p1, tmp_93_cast_fu_1074_p1, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1683;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
p_uOut_address0 <= p_uOut_addr_4_reg_1642;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
p_uOut_address0 <= p_uOut_addr_2_reg_1546;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_3_fu_633_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address0 <= tmp_93_cast_fu_1074_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
p_uOut_address0 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
p_uOut_address0 <= tmp_89_cast_fu_1004_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
p_uOut_address0 <= tmp_86_cast_fu_825_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st147_fsm_146, tmp_94_cast_fu_1088_p1, tmp_95_cast_fu_1251_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
p_uOut_address1 <= tmp_95_cast_fu_1251_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address1 <= tmp_94_cast_fu_1088_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_439, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) or ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st147_fsm_146)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_590, ap_sig_cseq_ST_st2_fsm_1, tmp_47_reg_1692, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_d0 <= tmp_47_reg_1692;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_d0 <= reg_590;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1128_p1 <= reg_550;
p_uOut_load_4_to_int_fu_1146_p1 <= p_uOut_load_4_reg_1743;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_1275_p1 <= i_1_reg_446(2 - 1 downto 0);
tmp_11_fu_676_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_3_reg_286));
tmp_12_fu_1314_p2 <= std_logic_vector(signed(tmp_4_cast_fu_1310_p1) + signed(tmp_8_reg_1781));
tmp_13_fu_657_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(ST_numLayer_load_reg_1452));
tmp_14_fu_1319_p1 <= tmp_12_fu_1314_p2(9 - 1 downto 0);
tmp_15_fu_858_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1452));
tmp_16_fu_1368_p2 <= std_logic_vector(unsigned(tmp_21_fu_1355_p6) + unsigned(ap_const_lv32_1));
tmp_17_fu_1374_p2 <= "1" when (signed(k_reg_469) < signed(tmp_16_fu_1368_p2)) else "0";
tmp_18_fu_712_p2 <= "1" when (signed(j_1_reg_298) < signed(tmp_22_fu_699_p6)) else "0";
tmp_19_fu_1331_p1 <= tmp_12_fu_1314_p2(12 - 1 downto 0);
tmp_1_fu_606_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_20_fu_897_p2 <= "1" when (signed(i_4_reg_344) < signed(tmp_25_fu_884_p6)) else "0";
tmp_23_fu_1343_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1323_p3) + unsigned(p_shl1_cast_fu_1335_p3));
tmp_24_cast_fu_737_p1 <= std_logic_vector(resize(signed(j_1_reg_298),38));
tmp_27_cast_fu_922_p1 <= std_logic_vector(resize(signed(i_4_reg_344),38));
tmp_27_fu_690_p1 <= i_3_reg_286(2 - 1 downto 0);
tmp_28_fu_791_p2 <= "1" when (signed(k_1_cast_fu_787_p1) < signed(tmp_26_reg_1534)) else "0";
tmp_29_fu_970_p2 <= "1" when (signed(j_2_cast_fu_966_p1) < signed(tmp_54_reg_1630)) else "0";
tmp_2_fu_1404_p2 <= "1" when (signed(i_cast_fu_1400_p1) < signed(P_config_read_reg_1470)) else "0";
tmp_30_fu_1026_p2 <= "1" when (signed(i_5_cast_fu_1022_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_31_fu_682_p1 <= tmp_11_fu_676_p2(9 - 1 downto 0);
tmp_33_fu_694_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_31_reg_1501))), 9));
tmp_34_fu_853_p1 <= tmp_34_neg_fu_847_p2;
tmp_34_neg_fu_847_p2 <= (tmp_34_to_int_fu_843_p1 xor ap_const_lv32_80000000);
tmp_34_to_int_fu_843_p1 <= reg_574;
tmp_3_fu_633_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),64));
tmp_40_fu_686_p1 <= tmp_11_fu_676_p2(2 - 1 downto 0);
tmp_46_fu_871_p1 <= grp_fu_666_p2(9 - 1 downto 0);
tmp_48_fu_1051_p2 <= "1" when (P_mode_read_reg_1443 = ap_const_lv32_3) else "0";
tmp_49_fu_1113_p2 <= "1" when (signed(i_6_cast_fu_1109_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_4_cast_fu_1310_p1 <= std_logic_vector(resize(signed(j_reg_458),38));
tmp_4_fu_1415_p1 <= i_reg_480(2 - 1 downto 0);
tmp_50_fu_1060_p2 <= "1" when (signed(p_netOut_2_cast_fu_1056_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_51_fu_875_p1 <= grp_fu_666_p2(38 - 1 downto 0);
tmp_52_fu_672_p1 <= tmp_13_fu_657_p2(2 - 1 downto 0);
tmp_53_fu_863_p1 <= tmp_15_fu_858_p2(9 - 1 downto 0);
tmp_55_fu_1230_p2 <= "1" when (signed(j_3_reg_435) < signed(tmp_66_fu_1217_p6)) else "0";
tmp_56_fu_879_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_53_reg_1589))), 9));
tmp_57_fu_1132_p4 <= p_uOut_load_3_to_int_fu_1128_p1(30 downto 23);
tmp_58_fu_867_p1 <= tmp_15_fu_858_p2(2 - 1 downto 0);
tmp_59_fu_1149_p4 <= p_uOut_load_4_to_int_fu_1146_p1(30 downto 23);
tmp_60_fu_1386_p1 <= k_reg_469(14 - 1 downto 0);
tmp_61_fu_1175_p2 <= (notrhs_fu_1169_p2 or notlhs_fu_1163_p2);
tmp_62_fu_1193_p2 <= (notrhs2_fu_1187_p2 or notlhs1_fu_1181_p2);
tmp_63_fu_1199_p2 <= (tmp_61_fu_1175_p2 and tmp_62_fu_1193_p2);
tmp_64_fu_515_opcode <= ap_const_lv5_2;
tmp_65_fu_1205_p2 <= (tmp_63_fu_1199_p2 and tmp_64_fu_515_p2);
tmp_67_fu_1390_p2 <= std_logic_vector(unsigned(tmp_23_reg_1804) + unsigned(tmp_60_fu_1386_p1));
tmp_68_fu_741_p2 <= std_logic_vector(signed(tmp_24_cast_fu_737_p1) + signed(tmp_24_reg_1511));
tmp_69_fu_751_p1 <= tmp_68_fu_741_p2(9 - 1 downto 0);
tmp_6_fu_1260_p2 <= "1" when (signed(i_1_cast_fu_1256_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_70_fu_763_p1 <= tmp_68_fu_741_p2(12 - 1 downto 0);
tmp_71_fu_775_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_755_p3) + unsigned(p_shl3_cast_fu_767_p3));
tmp_72_fu_926_p2 <= std_logic_vector(signed(tmp_27_cast_fu_922_p1) + signed(tmp_51_reg_1606));
tmp_73_fu_936_p1 <= tmp_72_fu_926_p2(9 - 1 downto 0);
tmp_74_fu_948_p1 <= tmp_72_fu_926_p2(12 - 1 downto 0);
tmp_75_fu_960_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_940_p3) + unsigned(p_shl5_cast_fu_952_p3));
tmp_76_cast_fu_1395_p1 <= std_logic_vector(resize(unsigned(tmp_67_fu_1390_p2),64));
tmp_76_fu_1037_p1 <= i_5_reg_378(9 - 1 downto 0);
tmp_77_cast_fu_746_p1 <= std_logic_vector(resize(signed(tmp_68_fu_741_p2),64));
tmp_77_fu_1041_p2 <= std_logic_vector(unsigned(tmp_46_reg_1599) + unsigned(tmp_76_fu_1037_p1));
tmp_78_fu_802_p1 <= k_1_reg_321(9 - 1 downto 0);
tmp_79_fu_806_p1 <= k_1_reg_321(14 - 1 downto 0);
tmp_7_fu_622_p2 <= "1" when (signed(i_2_cast_fu_618_p1) < signed(ST_layerSize_0_load_reg_1465)) else "0";
tmp_80_fu_810_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_79_fu_806_p1));
tmp_81_cast_fu_931_p1 <= std_logic_vector(resize(signed(tmp_72_fu_926_p2),64));
tmp_81_fu_820_p2 <= std_logic_vector(unsigned(tmp_33_reg_1521) + unsigned(tmp_78_fu_802_p1));
tmp_82_fu_830_p1 <= tmp_26_reg_1534(14 - 1 downto 0);
tmp_83_fu_833_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_82_fu_830_p1));
tmp_84_fu_981_p1 <= j_2_reg_367(9 - 1 downto 0);
tmp_85_cast_fu_815_p1 <= std_logic_vector(resize(unsigned(tmp_80_fu_810_p2),64));
tmp_85_fu_985_p1 <= j_2_reg_367(14 - 1 downto 0);
tmp_86_cast_fu_825_p1 <= std_logic_vector(resize(signed(tmp_81_fu_820_p2),64));
tmp_86_fu_989_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_85_fu_985_p1));
tmp_87_cast_fu_838_p1 <= std_logic_vector(resize(unsigned(tmp_83_fu_833_p2),64));
tmp_87_fu_999_p2 <= std_logic_vector(unsigned(tmp_56_reg_1611) + unsigned(tmp_84_fu_981_p1));
tmp_88_cast_fu_994_p1 <= std_logic_vector(resize(unsigned(tmp_86_fu_989_p2),64));
tmp_88_fu_1009_p1 <= tmp_54_reg_1630(14 - 1 downto 0);
tmp_89_cast_fu_1004_p1 <= std_logic_vector(resize(signed(tmp_87_fu_999_p2),64));
tmp_89_fu_1012_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_88_fu_1009_p1));
tmp_90_cast_fu_1017_p1 <= std_logic_vector(resize(unsigned(tmp_89_fu_1012_p2),64));
tmp_90_fu_1099_p1 <= phi_mul_reg_424(9 - 1 downto 0);
tmp_91_cast_fu_1046_p1 <= std_logic_vector(resize(signed(tmp_77_fu_1041_p2),64));
tmp_91_fu_1124_p1 <= i_6_reg_413(2 - 1 downto 0);
tmp_92_fu_1065_p1 <= p_netOut_2_reg_402(9 - 1 downto 0);
tmp_93_cast_fu_1074_p1 <= std_logic_vector(resize(signed(tmp_93_fu_1069_p2),64));
tmp_93_fu_1069_p2 <= std_logic_vector(unsigned(tmp_92_fu_1065_p1) + unsigned(tmp_46_reg_1599));
tmp_94_cast_fu_1088_p1 <= std_logic_vector(resize(signed(tmp_94_fu_1083_p2),64));
tmp_94_fu_1083_p2 <= std_logic_vector(unsigned(tmp_96_fu_1079_p1) + unsigned(tmp_46_reg_1599));
tmp_95_cast_fu_1251_p1 <= std_logic_vector(resize(unsigned(tmp_95_fu_1246_p2),64));
tmp_95_fu_1246_p2 <= std_logic_vector(unsigned(tmp_90_reg_1720) + unsigned(tmp_99_fu_1242_p1));
tmp_96_fu_1079_p1 <= p_netOut_reg_389(9 - 1 downto 0);
tmp_97_fu_1142_p1 <= p_uOut_load_3_to_int_fu_1128_p1(23 - 1 downto 0);
tmp_98_fu_1159_p1 <= p_uOut_load_4_to_int_fu_1146_p1(23 - 1 downto 0);
tmp_99_fu_1242_p1 <= j_3_reg_435(9 - 1 downto 0);
tmp_9_fu_642_p2 <= "1" when (signed(i_3_cast_fu_638_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_9_t_fu_1279_p2 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_10_fu_1275_p1));
tmp_fu_596_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_s_fu_1298_p2 <= "1" when (signed(j_reg_458) < signed(tmp_5_fu_1285_p6)) else "0";
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_config_TVALID : IN STD_LOGIC;
P_config_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_netOut_TVALID : OUT STD_LOGIC;
P_netOut_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=42,HLS_SYN_FF=8905,HLS_SYN_LUT=12500}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (153 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (153 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (153 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (153 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (153 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (153 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (153 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (153 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (153 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (153 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_7C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111100";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_96 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010110";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv37_0 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000000";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv38_23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100011";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv39_23 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000100011";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv37_23 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100011";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_550 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_253 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal ap_sig_cseq_ST_st125_fsm_124 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal reg_557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_285 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_294 : BOOLEAN;
signal grp_fu_498_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_563 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_311 : BOOLEAN;
signal grp_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_328 : BOOLEAN;
signal reg_574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_337 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_344 : BOOLEAN;
signal grp_fu_512_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_354 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_361 : BOOLEAN;
signal grp_fu_529_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_371 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_378 : BOOLEAN;
signal grp_fu_509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_388 : BOOLEAN;
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_395 : BOOLEAN;
signal P_mode_read_reg_1443 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_408 : BOOLEAN;
signal tmp_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_load_reg_1452 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1461 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_0_load_reg_1465 : STD_LOGIC_VECTOR (31 downto 0);
signal P_config_read_reg_1470 : STD_LOGIC_VECTOR (31 downto 0);
signal i_8_fu_627_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_432 : BOOLEAN;
signal tmp_7_fu_622_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_439 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_449 : BOOLEAN;
signal tmp_9_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_672_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_52_reg_1496 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_31_fu_682_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_reg_1501 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_467 : BOOLEAN;
signal tmp_40_fu_686_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_40_reg_1506 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_651_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_24_reg_1511 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_478 : BOOLEAN;
signal tmp_27_fu_690_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_reg_1516 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_33_fu_694_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_reg_1521 : STD_LOGIC_VECTOR (8 downto 0);
signal j_5_fu_718_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_491 : BOOLEAN;
signal tmp_26_fu_724_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_reg_1534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_71_fu_775_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_reg_1540 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_2_reg_1546 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_781_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_fu_796_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_reg_1559 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_513 : BOOLEAN;
signal tmp_28_fu_791_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_519_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_37_reg_1579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_533 : BOOLEAN;
signal grp_fu_524_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_reg_1584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_542 : BOOLEAN;
signal tmp_53_fu_863_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_reg_1589 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_551 : BOOLEAN;
signal tmp_58_fu_867_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_58_reg_1594 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_46_fu_871_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_reg_1599 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_562 : BOOLEAN;
signal tmp_51_fu_875_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_51_reg_1606 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_56_fu_879_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_56_reg_1611 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_fu_884_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_1616 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_575 : BOOLEAN;
signal i_12_fu_903_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1625 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_909_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_1630 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_75_fu_960_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_75_reg_1636 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_4_reg_1642 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_975_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_6_reg_1650 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_596 : BOOLEAN;
signal tmp_29_fu_970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_615 : BOOLEAN;
signal i_11_fu_1031_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_11_reg_1678 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_624 : BOOLEAN;
signal p_uOut_addr_5_reg_1683 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_30_fu_1026_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_fu_1051_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_reg_1688 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_504_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_1692 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_642 : BOOLEAN;
signal p_netOut_2_cast_fu_1056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_cast_reg_1697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_651 : BOOLEAN;
signal tmp_50_fu_1060_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_TREADY : STD_LOGIC;
signal i_15_fu_1093_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_15_reg_1715 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_90_fu_1099_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_90_reg_1720 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1103_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal next_mul_reg_1725 : STD_LOGIC_VECTOR (36 downto 0);
signal i_14_fu_1118_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_14_reg_1733 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_91_fu_1124_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_91_reg_1738 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_49_fu_1113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_reg_1743 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_1205_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_65_reg_1749 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_701 : BOOLEAN;
signal p_netOut_1_fu_1211_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_710 : BOOLEAN;
signal j_7_fu_1236_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_7_reg_1762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_719 : BOOLEAN;
signal tmp_55_fu_1230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_1260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1772 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_734 : BOOLEAN;
signal grp_fu_1269_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_8_reg_1781 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st151_fsm_150 : STD_LOGIC;
signal ap_sig_bdd_748 : BOOLEAN;
signal tmp_10_fu_1275_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_10_reg_1786 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_fu_1279_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_reg_1791 : STD_LOGIC_VECTOR (1 downto 0);
signal j_4_fu_1304_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_4_reg_1799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st152_fsm_151 : STD_LOGIC;
signal ap_sig_bdd_761 : BOOLEAN;
signal tmp_23_fu_1343_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_reg_1804 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_s_fu_1298_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1349_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_2_fu_1380_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st153_fsm_152 : STD_LOGIC;
signal ap_sig_bdd_779 : BOOLEAN;
signal tmp_17_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_786 : BOOLEAN;
signal tmp_2_fu_1404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_1822 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_796 : BOOLEAN;
signal ap_sig_bdd_801 : BOOLEAN;
signal i_7_fu_1409_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_275 : STD_LOGIC_VECTOR (30 downto 0);
signal i_3_reg_286 : STD_LOGIC_VECTOR (30 downto 0);
signal j_1_reg_298 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_832 : BOOLEAN;
signal sum_reg_309 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_321 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_332 : STD_LOGIC_VECTOR (31 downto 0);
signal i_4_reg_344 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_355 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_367 : STD_LOGIC_VECTOR (30 downto 0);
signal i_5_reg_378 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_853 : BOOLEAN;
signal p_netOut_reg_389 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_reg_402 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_413 : STD_LOGIC_VECTOR (30 downto 0);
signal phi_mul_reg_424 : STD_LOGIC_VECTOR (36 downto 0);
signal j_3_reg_435 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_879 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_446 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_458 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_469 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_480 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_3_fu_633_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_746_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_838_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_931_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_994_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1017_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1046_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1074_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_94_cast_fu_1088_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_95_cast_fu_1251_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_1395_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_1415_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_997 : BOOLEAN;
signal grp_fu_491_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_1021 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_1028 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_1036 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_1043 : BOOLEAN;
signal grp_fu_509_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_512_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_fu_853_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_cast_fu_618_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_cast_fu_638_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_651_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_651_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_13_fu_657_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_11_fu_676_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_22_fu_699_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_cast_fu_737_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_68_fu_741_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_69_fu_751_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_763_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_755_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_767_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal k_1_cast_fu_787_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_806_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_fu_810_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_802_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_fu_820_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_82_fu_830_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_83_fu_833_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_34_to_int_fu_843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_neg_fu_847_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_858_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p2 : STD_LOGIC_VECTOR (38 downto 0);
signal tmp_27_cast_fu_922_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_72_fu_926_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_73_fu_936_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_fu_948_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_940_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_952_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal j_2_cast_fu_966_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_985_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_86_fu_989_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_84_fu_981_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_999_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_88_fu_1009_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1012_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_5_cast_fu_1022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_1037_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1041_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_92_fu_1065_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_fu_1069_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_96_fu_1079_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_94_fu_1083_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_6_cast_fu_1109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_3_to_int_fu_1128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_to_int_fu_1146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_1132_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_fu_1142_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_1169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_1149_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_98_fu_1159_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_1187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_1175_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_1193_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_63_fu_1199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_515_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_1217_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_1242_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_95_fu_1246_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_1_cast_fu_1256_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1269_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_1269_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_1285_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_cast_fu_1310_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_12_fu_1314_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_14_fu_1319_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1331_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl_cast_fu_1323_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_1335_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_fu_1355_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_1368_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_1386_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_67_fu_1390_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_cast_fu_1400_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_ce : STD_LOGIC;
signal grp_fu_498_ce : STD_LOGIC;
signal grp_fu_504_ce : STD_LOGIC;
signal tmp_64_fu_515_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_519_ce : STD_LOGIC;
signal grp_fu_524_ce : STD_LOGIC;
signal grp_fu_529_ce : STD_LOGIC;
signal grp_fu_651_ce : STD_LOGIC;
signal grp_fu_666_ce : STD_LOGIC;
signal grp_fu_1269_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (153 downto 0);
signal grp_fu_1269_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal grp_fu_651_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_bdd_976 : BOOLEAN;
component feedforward_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mul_7ns_31ns_38_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (30 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (37 downto 0) );
end component;
component feedforward_mul_7ns_32s_39_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (38 downto 0) );
end component;
component feedforward_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode => P_mode);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 32,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0 : component feedforward_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_491_p0,
din1 => grp_fu_491_p1,
ce => grp_fu_491_ce,
dout => grp_fu_491_p2);
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1 : component feedforward_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => p_uOut_q0,
din1 => ST_WandB_q0,
ce => grp_fu_498_ce,
dout => grp_fu_498_p2);
feedforward_fdiv_32ns_32ns_32_16_U2 : component feedforward_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_550,
din1 => sumsoft_reg_332,
ce => grp_fu_504_ce,
dout => grp_fu_504_p2);
feedforward_fptrunc_64ns_32_1_U3 : component feedforward_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_509_p0,
dout => grp_fu_509_p1);
feedforward_fpext_32ns_64_1_U4 : component feedforward_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_512_p0,
dout => grp_fu_512_p1);
feedforward_fcmp_32ns_32ns_1_1_U5 : component feedforward_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_550,
din1 => p_uOut_load_4_reg_1743,
opcode => tmp_64_fu_515_opcode,
dout => tmp_64_fu_515_p2);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_584,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_519_ce,
dout => grp_fu_519_p2);
feedforward_ddiv_64ns_64ns_64_31_U7 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_37_reg_1579,
ce => grp_fu_524_ce,
dout => grp_fu_524_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_579,
ce => grp_fu_529_ce,
dout => grp_fu_529_p2);
feedforward_mul_7ns_31ns_38_3_U9 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_651_p0,
din1 => grp_fu_651_p1,
ce => grp_fu_651_ce,
dout => grp_fu_651_p2);
feedforward_mul_7ns_32s_39_3_U10 : component feedforward_mul_7ns_32s_39_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 32,
dout_WIDTH => 39)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_666_p0,
din1 => tmp_13_fu_657_p2,
ce => grp_fu_666_ce,
dout => grp_fu_666_p2);
feedforward_mux_4to1_sel2_32_1_U11 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_27_reg_1516,
dout => tmp_22_fu_699_p6);
feedforward_mux_4to1_sel2_32_1_U12 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_40_reg_1506,
dout => tmp_26_fu_724_p6);
feedforward_mux_4to1_sel2_32_1_U13 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_52_reg_1496,
dout => tmp_25_fu_884_p6);
feedforward_mux_4to1_sel2_32_1_U14 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_58_reg_1594,
dout => tmp_54_fu_909_p6);
feedforward_mux_4to1_sel2_32_1_U15 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_91_reg_1738,
dout => tmp_66_fu_1217_p6);
feedforward_mul_7ns_31ns_38_3_U16 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1269_p0,
din1 => grp_fu_1269_p1,
ce => grp_fu_1269_ce,
dout => grp_fu_1269_p2);
feedforward_mux_4to1_sel2_32_1_U17 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_10_reg_1786,
dout => tmp_5_fu_1285_p6);
feedforward_mux_4to1_sel2_32_1_U18 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_9_t_reg_1791,
dout => tmp_21_fu_1355_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_TREADY assign process. --
ap_reg_ioackin_P_netOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_976) then
if (not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_TREADY)) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_446 assign process. --
i_1_reg_446_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
i_1_reg_446 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and (ap_const_lv1_0 = tmp_s_fu_1298_p2))) then
i_1_reg_446 <= i_9_fu_1349_p2;
end if;
end if;
end process;
-- i_2_reg_275 assign process. --
i_2_reg_275_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
i_2_reg_275 <= ap_const_lv31_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
i_2_reg_275 <= i_8_fu_627_p2;
end if;
end if;
end process;
-- i_3_reg_286 assign process. --
i_3_reg_286_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
i_3_reg_286 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_18_fu_712_p2))) then
i_3_reg_286 <= i_10_fu_781_p2;
end if;
end if;
end process;
-- i_4_reg_344 assign process. --
i_4_reg_344_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
i_4_reg_344 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
i_4_reg_344 <= i_12_reg_1625;
end if;
end if;
end process;
-- i_5_reg_378 assign process. --
i_5_reg_378_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_20_fu_897_p2))) then
i_5_reg_378 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
i_5_reg_378 <= i_11_reg_1678;
end if;
end if;
end process;
-- i_6_reg_413 assign process. --
i_6_reg_413_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
i_6_reg_413 <= i_14_reg_1733;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
i_6_reg_413 <= ap_const_lv31_0;
end if;
end if;
end process;
-- i_reg_480 assign process. --
i_reg_480_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
i_reg_480 <= i_7_fu_1409_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
i_reg_480 <= ap_const_lv31_0;
end if;
end if;
end process;
-- j_1_reg_298 assign process. --
j_1_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
j_1_reg_298 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
j_1_reg_298 <= j_5_reg_1529;
end if;
end if;
end process;
-- j_2_reg_367 assign process. --
j_2_reg_367_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
j_2_reg_367 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
j_2_reg_367 <= j_6_reg_1650;
end if;
end if;
end process;
-- j_3_reg_435 assign process. --
j_3_reg_435_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
j_3_reg_435 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_435 <= j_7_reg_1762;
end if;
end if;
end process;
-- j_reg_458 assign process. --
j_reg_458_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and (ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
j_reg_458 <= j_4_reg_1799;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
j_reg_458 <= ap_const_lv32_0;
end if;
end if;
end process;
-- k_1_reg_321 assign process. --
k_1_reg_321_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
k_1_reg_321 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
k_1_reg_321 <= k_3_reg_1559;
end if;
end if;
end process;
-- k_reg_469 assign process. --
k_reg_469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
k_reg_469 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
k_reg_469 <= k_2_fu_1380_p2;
end if;
end if;
end process;
-- p_netOut_2_reg_402 assign process. --
p_netOut_2_reg_402_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_2_reg_402 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_2_reg_402 <= i_15_reg_1715;
end if;
end if;
end process;
-- p_netOut_reg_389 assign process. --
p_netOut_reg_389_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_reg_389 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_reg_389 <= p_netOut_1_fu_1211_p3;
end if;
end if;
end process;
-- phi_mul_reg_424 assign process. --
phi_mul_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
phi_mul_reg_424 <= next_mul_reg_1725;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
phi_mul_reg_424 <= ap_const_lv37_0;
end if;
end if;
end process;
-- sum_1_reg_355 assign process. --
sum_1_reg_355_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
sum_1_reg_355 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
sum_1_reg_355 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sum_reg_309 assign process. --
sum_reg_309_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
sum_reg_309 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
sum_reg_309 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sumsoft_reg_332 assign process. --
sumsoft_reg_332_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
sumsoft_reg_332 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
sumsoft_reg_332 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
P_config_read_reg_1470 <= P_config_TDATA;
ST_numLayer <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_408))) then
P_mode_read_reg_1443 <= P_mode;
ST_numLayer_load_reg_1452 <= ST_numLayer;
tmp_reg_1448 <= tmp_fu_596_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ST_layerSize_0_load_reg_1465 <= ST_layerSize_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and not((tmp_4_fu_1415_p1 = ap_const_lv2_2)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_1)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
i_11_reg_1678 <= i_11_fu_1031_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
i_12_reg_1625 <= i_12_fu_903_p2;
tmp_25_reg_1616 <= tmp_25_fu_884_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)))) then
i_14_reg_1733 <= i_14_fu_1118_p2;
next_mul_reg_1725 <= next_mul_fu_1103_p2;
tmp_90_reg_1720 <= tmp_90_fu_1099_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
i_15_reg_1715 <= i_15_fu_1093_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) then
j_4_reg_1799 <= j_4_fu_1304_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
j_5_reg_1529 <= j_5_fu_718_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
j_6_reg_1650 <= j_6_fu_975_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
j_7_reg_1762 <= j_7_fu_1236_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
k_3_reg_1559 <= k_3_fu_796_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))))) then
p_netOut_2_cast_reg_1697(30 downto 0) <= p_netOut_2_cast_fu_1056_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
p_uOut_addr_2_reg_1546 <= tmp_77_cast_fu_746_p1(8 - 1 downto 0);
tmp_26_reg_1534 <= tmp_26_fu_724_p6;
tmp_71_reg_1540(13 downto 2) <= tmp_71_fu_775_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
p_uOut_addr_4_reg_1642 <= tmp_81_cast_fu_931_p1(8 - 1 downto 0);
tmp_54_reg_1630 <= tmp_54_fu_909_p6;
tmp_75_reg_1636(13 downto 2) <= tmp_75_fu_960_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and not((ap_const_lv1_0 = tmp_30_fu_1026_p2)))) then
p_uOut_addr_5_reg_1683 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) then
p_uOut_load_4_reg_1743 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124) or (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143))) then
reg_550 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
reg_557 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
reg_563 <= grp_fu_498_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_574 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
reg_579 <= grp_fu_512_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
reg_584 <= grp_fu_529_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
reg_590 <= grp_fu_509_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
tmp_10_reg_1786 <= tmp_10_fu_1275_p1;
tmp_8_reg_1781 <= grp_fu_1269_p2;
tmp_9_t_reg_1791 <= tmp_9_t_fu_1279_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408))) then
tmp_1_reg_1461 <= tmp_1_fu_606_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
tmp_23_reg_1804(13 downto 2) <= tmp_23_fu_1343_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_24_reg_1511 <= grp_fu_651_p2;
tmp_27_reg_1516 <= tmp_27_fu_690_p1;
tmp_33_reg_1521 <= tmp_33_fu_694_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not(ap_sig_bdd_801))) then
tmp_2_reg_1822 <= tmp_2_fu_1404_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_31_reg_1501 <= tmp_31_fu_682_p1;
tmp_40_reg_1506 <= tmp_40_fu_686_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) then
tmp_37_reg_1579 <= grp_fu_519_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
tmp_38_reg_1584 <= grp_fu_524_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
tmp_46_reg_1599 <= tmp_46_fu_871_p1;
tmp_51_reg_1606 <= tmp_51_fu_875_p1;
tmp_56_reg_1611 <= tmp_56_fu_879_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
tmp_47_reg_1692 <= grp_fu_504_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2))) then
tmp_48_reg_1688 <= tmp_48_fu_1051_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_9_fu_642_p2))) then
tmp_52_reg_1496 <= tmp_52_fu_672_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
tmp_53_reg_1589 <= tmp_53_fu_863_p1;
tmp_58_reg_1594 <= tmp_58_fu_867_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) then
tmp_65_reg_1749 <= tmp_65_fu_1205_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) then
tmp_6_reg_1772 <= tmp_6_fu_1260_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
tmp_91_reg_1738 <= tmp_91_fu_1124_p1;
end if;
end if;
end process;
tmp_71_reg_1540(1 downto 0) <= "00";
tmp_75_reg_1636(1 downto 0) <= "00";
p_netOut_2_cast_reg_1697(31) <= '0';
tmp_23_reg_1804(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_596_p2, ap_sig_bdd_408, tmp_reg_1448, tmp_1_fu_606_p2, tmp_1_reg_1461, tmp_7_fu_622_p2, ap_sig_bdd_439, tmp_9_fu_642_p2, tmp_18_fu_712_p2, tmp_28_fu_791_p2, tmp_20_fu_897_p2, tmp_29_fu_970_p2, tmp_30_fu_1026_p2, tmp_48_reg_1688, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_55_fu_1230_p2, tmp_6_fu_1260_p2, tmp_6_reg_1772, tmp_s_fu_1298_p2, tmp_17_fu_1374_p2, ap_sig_bdd_786, tmp_2_fu_1404_p2, tmp_2_reg_1822, ap_sig_bdd_801, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_9_fu_642_p2)) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = tmp_18_fu_712_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_28_fu_791_p2)) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
if (not((ap_const_lv1_0 = tmp_20_fu_897_p2))) then
ap_NS_fsm <= ap_ST_st83_fsm_82;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st83_fsm_82 =>
if ((ap_const_lv1_0 = tmp_29_fu_970_p2)) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st84_fsm_83;
end if;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st124_fsm_123 =>
if ((ap_const_lv1_0 = tmp_30_fu_1026_p2)) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st125_fsm_124;
end if;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st143_fsm_142 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st147_fsm_146 =>
if (not((ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st148_fsm_147 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (not((ap_const_lv1_0 = tmp_6_fu_1260_p2))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st151_fsm_150;
when ap_ST_st151_fsm_150 =>
ap_NS_fsm <= ap_ST_st152_fsm_151;
when ap_ST_st152_fsm_151 =>
if ((ap_const_lv1_0 = tmp_s_fu_1298_p2)) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st153_fsm_152 =>
if ((not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st153_fsm_152;
elsif (((ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st152_fsm_151;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st154_fsm_153 =>
if ((not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((ap_const_lv1_0 = tmp_2_fu_1404_p2) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st154_fsm_153;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_TREADY assign process. --
P_config_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_596_p2, ap_sig_bdd_408, tmp_2_fu_1404_p2, ap_sig_cseq_ST_st154_fsm_153, ap_sig_bdd_801)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801)))) then
P_config_TREADY <= ap_const_logic_1;
else
P_config_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_TDATA <= p_netOut_reg_389;
-- P_netOut_TVALID assign process. --
P_netOut_TVALID_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_reg_ioackin_P_netOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY))) then
P_netOut_TVALID <= ap_const_logic_1;
else
P_netOut_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, tmp_85_cast_fu_815_p1, tmp_87_cast_fu_838_p1, tmp_88_cast_fu_994_p1, tmp_90_cast_fu_1017_p1, tmp_76_cast_fu_1395_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) then
ST_WandB_address0 <= tmp_76_cast_fu_1395_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2))) then
ST_WandB_address0 <= tmp_90_cast_fu_1017_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_994_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2))) then
ST_WandB_address0 <= tmp_87_cast_fu_838_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2)))) then
ST_WandB_address0 <= tmp_85_cast_fu_815_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not(ap_sig_bdd_786)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1021 assign process. --
ap_sig_bdd_1021_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1021 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_1028 assign process. --
ap_sig_bdd_1028_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1028 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_1036 assign process. --
ap_sig_bdd_1036_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1036 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_1043 assign process. --
ap_sig_bdd_1043_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1043 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_172 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_253 assign process. --
ap_sig_bdd_253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_253 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(124 downto 124));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_285 assign process. --
ap_sig_bdd_285_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_285 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_294 assign process. --
ap_sig_bdd_294_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_294 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_304 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_311 assign process. --
ap_sig_bdd_311_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_311 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_321 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_328 assign process. --
ap_sig_bdd_328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_328 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_337 assign process. --
ap_sig_bdd_337_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_337 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_344 assign process. --
ap_sig_bdd_344_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_344 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_354 assign process. --
ap_sig_bdd_354_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_354 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_361 assign process. --
ap_sig_bdd_361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_361 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_371 assign process. --
ap_sig_bdd_371_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_371 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_378 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_388 assign process. --
ap_sig_bdd_388_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_388 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_395 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_408 assign process. --
ap_sig_bdd_408_assign_proc : process(ap_start, P_config_TVALID, tmp_fu_596_p2)
begin
ap_sig_bdd_408 <= (((P_config_TVALID = ap_const_logic_0) and not((tmp_fu_596_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_432 assign process. --
ap_sig_bdd_432_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_432 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_439 assign process. --
ap_sig_bdd_439_assign_proc : process(P_netIn_TVALID, tmp_7_fu_622_p2)
begin
ap_sig_bdd_439 <= ((P_netIn_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)));
end process;
-- ap_sig_bdd_449 assign process. --
ap_sig_bdd_449_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_449 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_467 assign process. --
ap_sig_bdd_467_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_467 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_478 assign process. --
ap_sig_bdd_478_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_478 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_491 assign process. --
ap_sig_bdd_491_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_491 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_513 assign process. --
ap_sig_bdd_513_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_513 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_533 assign process. --
ap_sig_bdd_533_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_533 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_542 assign process. --
ap_sig_bdd_542_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_542 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_551 assign process. --
ap_sig_bdd_551_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_551 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_562 assign process. --
ap_sig_bdd_562_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_562 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_575 assign process. --
ap_sig_bdd_575_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_575 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_596 assign process. --
ap_sig_bdd_596_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_596 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_615 assign process. --
ap_sig_bdd_615_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_615 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_624 assign process. --
ap_sig_bdd_624_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_624 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_642 assign process. --
ap_sig_bdd_642_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_642 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_651 assign process. --
ap_sig_bdd_651_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_651 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_701 assign process. --
ap_sig_bdd_701_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_701 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_710 assign process. --
ap_sig_bdd_710_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_710 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_719 assign process. --
ap_sig_bdd_719_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_719 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_734 assign process. --
ap_sig_bdd_734_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_734 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_748 assign process. --
ap_sig_bdd_748_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_748 <= (ap_const_lv1_1 = ap_CS_fsm(150 downto 150));
end process;
-- ap_sig_bdd_761 assign process. --
ap_sig_bdd_761_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_761 <= (ap_const_lv1_1 = ap_CS_fsm(151 downto 151));
end process;
-- ap_sig_bdd_779 assign process. --
ap_sig_bdd_779_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_779 <= (ap_const_lv1_1 = ap_CS_fsm(152 downto 152));
end process;
-- ap_sig_bdd_786 assign process. --
ap_sig_bdd_786_assign_proc : process(P_WandB_TVALID, tmp_17_fu_1374_p2)
begin
ap_sig_bdd_786 <= ((P_WandB_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)));
end process;
-- ap_sig_bdd_796 assign process. --
ap_sig_bdd_796_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_796 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_801 assign process. --
ap_sig_bdd_801_assign_proc : process(P_config_TVALID, tmp_2_fu_1404_p2)
begin
ap_sig_bdd_801 <= ((P_config_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)));
end process;
-- ap_sig_bdd_832 assign process. --
ap_sig_bdd_832_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_832 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_853 assign process. --
ap_sig_bdd_853_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_853 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_879 assign process. --
ap_sig_bdd_879_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_879 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_976 assign process. --
ap_sig_bdd_976_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2)
begin
ap_sig_bdd_976 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2));
end process;
-- ap_sig_bdd_997 assign process. --
ap_sig_bdd_997_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_997 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_378)
begin
if (ap_sig_bdd_378) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_395)
begin
if (ap_sig_bdd_395) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_997)
begin
if (ap_sig_bdd_997) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_304)
begin
if (ap_sig_bdd_304) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_615)
begin
if (ap_sig_bdd_615) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_624)
begin
if (ap_sig_bdd_624) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st125_fsm_124 assign process. --
ap_sig_cseq_ST_st125_fsm_124_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_1021)
begin
if (ap_sig_bdd_1021) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_642)
begin
if (ap_sig_bdd_642) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_853)
begin
if (ap_sig_bdd_853) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_651)
begin
if (ap_sig_bdd_651) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_701)
begin
if (ap_sig_bdd_701) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_710)
begin
if (ap_sig_bdd_710) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_719)
begin
if (ap_sig_bdd_719) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_879)
begin
if (ap_sig_bdd_879) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st151_fsm_150 assign process. --
ap_sig_cseq_ST_st151_fsm_150_assign_proc : process(ap_sig_bdd_748)
begin
if (ap_sig_bdd_748) then
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st152_fsm_151 assign process. --
ap_sig_cseq_ST_st152_fsm_151_assign_proc : process(ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) then
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st153_fsm_152 assign process. --
ap_sig_cseq_ST_st153_fsm_152_assign_proc : process(ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) then
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_796)
begin
if (ap_sig_bdd_796) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_321)
begin
if (ap_sig_bdd_321) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_285)
begin
if (ap_sig_bdd_285) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_1028)
begin
if (ap_sig_bdd_1028) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_172)
begin
if (ap_sig_bdd_172) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_337)
begin
if (ap_sig_bdd_337) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_354)
begin
if (ap_sig_bdd_354) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_432)
begin
if (ap_sig_bdd_432) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_449)
begin
if (ap_sig_bdd_449) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_371)
begin
if (ap_sig_bdd_371) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_533)
begin
if (ap_sig_bdd_533) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_467)
begin
if (ap_sig_bdd_467) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_478)
begin
if (ap_sig_bdd_478) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_542)
begin
if (ap_sig_bdd_542) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_388)
begin
if (ap_sig_bdd_388) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_832)
begin
if (ap_sig_bdd_832) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_513)
begin
if (ap_sig_bdd_513) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_551)
begin
if (ap_sig_bdd_551) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_562)
begin
if (ap_sig_bdd_562) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_575)
begin
if (ap_sig_bdd_575) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_596)
begin
if (ap_sig_bdd_596) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_311)
begin
if (ap_sig_bdd_311) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_1036)
begin
if (ap_sig_bdd_1036) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_328)
begin
if (ap_sig_bdd_328) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_294)
begin
if (ap_sig_bdd_294) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_1043)
begin
if (ap_sig_bdd_1043) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_344)
begin
if (ap_sig_bdd_344) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_361)
begin
if (ap_sig_bdd_361) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_TREADY assign process. --
ap_sig_ioackin_P_netOut_TREADY_assign_proc : process(P_netOut_TREADY, ap_reg_ioackin_P_netOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY)) then
ap_sig_ioackin_P_netOut_TREADY <= P_netOut_TREADY;
else
ap_sig_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_1269_ce <= ap_const_logic_1;
grp_fu_1269_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_1269_p1 <= grp_fu_1269_p10(31 - 1 downto 0);
grp_fu_1269_p10 <= std_logic_vector(resize(unsigned(i_1_reg_446),38));
grp_fu_491_ce <= ap_const_logic_1;
-- grp_fu_491_p0 assign process. --
grp_fu_491_p0_assign_proc : process(sum_reg_309, sumsoft_reg_332, sum_1_reg_355, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p0 <= sumsoft_reg_332;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p0 <= sum_1_reg_355;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
grp_fu_491_p0 <= sum_reg_309;
else
grp_fu_491_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_491_p1 assign process. --
grp_fu_491_p1_assign_proc : process(reg_557, reg_563, reg_590, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p1 <= reg_590;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p1 <= reg_557;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
grp_fu_491_p1 <= reg_563;
else
grp_fu_491_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_498_ce <= ap_const_logic_1;
grp_fu_504_ce <= ap_const_logic_1;
-- grp_fu_509_p0 assign process. --
grp_fu_509_p0_assign_proc : process(reg_584, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st118_fsm_117, tmp_38_reg_1584)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_509_p0 <= reg_584;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
grp_fu_509_p0 <= tmp_38_reg_1584;
else
grp_fu_509_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_512_p0 assign process. --
grp_fu_512_p0_assign_proc : process(reg_574, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st99_fsm_98, tmp_34_fu_853_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) then
grp_fu_512_p0 <= reg_574;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
grp_fu_512_p0 <= tmp_34_fu_853_p1;
else
grp_fu_512_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_519_ce <= ap_const_logic_1;
grp_fu_524_ce <= ap_const_logic_1;
grp_fu_529_ce <= ap_const_logic_1;
grp_fu_651_ce <= ap_const_logic_1;
grp_fu_651_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_651_p1 <= grp_fu_651_p10(31 - 1 downto 0);
grp_fu_651_p10 <= std_logic_vector(resize(unsigned(i_3_reg_286),38));
grp_fu_666_ce <= ap_const_logic_1;
grp_fu_666_p0 <= ap_const_lv39_23(7 - 1 downto 0);
i_10_fu_781_p2 <= std_logic_vector(unsigned(i_3_reg_286) + unsigned(ap_const_lv31_1));
i_11_fu_1031_p2 <= std_logic_vector(unsigned(i_5_reg_378) + unsigned(ap_const_lv31_1));
i_12_fu_903_p2 <= std_logic_vector(unsigned(i_4_reg_344) + unsigned(ap_const_lv32_1));
i_14_fu_1118_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(i_6_reg_413));
i_15_fu_1093_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(p_netOut_2_reg_402));
i_1_cast_fu_1256_p1 <= std_logic_vector(resize(unsigned(i_1_reg_446),32));
i_2_cast_fu_618_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),32));
i_3_cast_fu_638_p1 <= std_logic_vector(resize(unsigned(i_3_reg_286),32));
i_5_cast_fu_1022_p1 <= std_logic_vector(resize(unsigned(i_5_reg_378),32));
i_6_cast_fu_1109_p1 <= std_logic_vector(resize(unsigned(i_6_reg_413),32));
i_7_fu_1409_p2 <= std_logic_vector(unsigned(i_reg_480) + unsigned(ap_const_lv31_1));
i_8_fu_627_p2 <= std_logic_vector(unsigned(i_2_reg_275) + unsigned(ap_const_lv31_1));
i_9_fu_1349_p2 <= std_logic_vector(unsigned(i_1_reg_446) + unsigned(ap_const_lv31_1));
i_cast_fu_1400_p1 <= std_logic_vector(resize(unsigned(i_reg_480),32));
j_2_cast_fu_966_p1 <= std_logic_vector(resize(unsigned(j_2_reg_367),32));
j_4_fu_1304_p2 <= std_logic_vector(unsigned(j_reg_458) + unsigned(ap_const_lv32_1));
j_5_fu_718_p2 <= std_logic_vector(unsigned(j_1_reg_298) + unsigned(ap_const_lv32_1));
j_6_fu_975_p2 <= std_logic_vector(unsigned(j_2_reg_367) + unsigned(ap_const_lv31_1));
j_7_fu_1236_p2 <= std_logic_vector(unsigned(j_3_reg_435) + unsigned(ap_const_lv32_1));
k_1_cast_fu_787_p1 <= std_logic_vector(resize(unsigned(k_1_reg_321),32));
k_2_fu_1380_p2 <= std_logic_vector(unsigned(k_reg_469) + unsigned(ap_const_lv32_1));
k_3_fu_796_p2 <= std_logic_vector(unsigned(k_1_reg_321) + unsigned(ap_const_lv31_1));
next_mul_fu_1103_p2 <= std_logic_vector(unsigned(ap_const_lv37_23) + unsigned(phi_mul_reg_424));
notlhs1_fu_1181_p2 <= "0" when (tmp_59_fu_1149_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_1163_p2 <= "0" when (tmp_57_fu_1132_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_1187_p2 <= "1" when (tmp_98_fu_1159_p1 = ap_const_lv23_0) else "0";
notrhs_fu_1169_p2 <= "1" when (tmp_97_fu_1142_p1 = ap_const_lv23_0) else "0";
p_netOut_1_fu_1211_p3 <=
p_netOut_2_cast_reg_1697 when (tmp_65_reg_1749(0) = '1') else
p_netOut_reg_389;
p_netOut_2_cast_fu_1056_p1 <= std_logic_vector(resize(unsigned(p_netOut_2_reg_402),32));
p_shl1_cast_fu_1335_p3 <= (tmp_19_fu_1331_p1 & ap_const_lv2_0);
p_shl2_cast_fu_755_p3 <= (tmp_69_fu_751_p1 & ap_const_lv5_0);
p_shl3_cast_fu_767_p3 <= (tmp_70_fu_763_p1 & ap_const_lv2_0);
p_shl4_cast_fu_940_p3 <= (tmp_73_fu_936_p1 & ap_const_lv5_0);
p_shl5_cast_fu_952_p3 <= (tmp_74_fu_948_p1 & ap_const_lv2_0);
p_shl_cast_fu_1323_p3 <= (tmp_14_fu_1319_p1 & ap_const_lv5_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_2_reg_1546, ap_sig_cseq_ST_st7_fsm_6, p_uOut_addr_4_reg_1642, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, p_uOut_addr_5_reg_1683, ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, tmp_3_fu_633_p1, tmp_86_cast_fu_825_p1, tmp_89_cast_fu_1004_p1, tmp_91_cast_fu_1046_p1, tmp_93_cast_fu_1074_p1, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1683;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
p_uOut_address0 <= p_uOut_addr_4_reg_1642;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
p_uOut_address0 <= p_uOut_addr_2_reg_1546;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_3_fu_633_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address0 <= tmp_93_cast_fu_1074_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
p_uOut_address0 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
p_uOut_address0 <= tmp_89_cast_fu_1004_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
p_uOut_address0 <= tmp_86_cast_fu_825_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st147_fsm_146, tmp_94_cast_fu_1088_p1, tmp_95_cast_fu_1251_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
p_uOut_address1 <= tmp_95_cast_fu_1251_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address1 <= tmp_94_cast_fu_1088_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_439, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) or ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st147_fsm_146)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_590, ap_sig_cseq_ST_st2_fsm_1, tmp_47_reg_1692, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_d0 <= tmp_47_reg_1692;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_d0 <= reg_590;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1128_p1 <= reg_550;
p_uOut_load_4_to_int_fu_1146_p1 <= p_uOut_load_4_reg_1743;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_1275_p1 <= i_1_reg_446(2 - 1 downto 0);
tmp_11_fu_676_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_3_reg_286));
tmp_12_fu_1314_p2 <= std_logic_vector(signed(tmp_4_cast_fu_1310_p1) + signed(tmp_8_reg_1781));
tmp_13_fu_657_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(ST_numLayer_load_reg_1452));
tmp_14_fu_1319_p1 <= tmp_12_fu_1314_p2(9 - 1 downto 0);
tmp_15_fu_858_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1452));
tmp_16_fu_1368_p2 <= std_logic_vector(unsigned(tmp_21_fu_1355_p6) + unsigned(ap_const_lv32_1));
tmp_17_fu_1374_p2 <= "1" when (signed(k_reg_469) < signed(tmp_16_fu_1368_p2)) else "0";
tmp_18_fu_712_p2 <= "1" when (signed(j_1_reg_298) < signed(tmp_22_fu_699_p6)) else "0";
tmp_19_fu_1331_p1 <= tmp_12_fu_1314_p2(12 - 1 downto 0);
tmp_1_fu_606_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_20_fu_897_p2 <= "1" when (signed(i_4_reg_344) < signed(tmp_25_fu_884_p6)) else "0";
tmp_23_fu_1343_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1323_p3) + unsigned(p_shl1_cast_fu_1335_p3));
tmp_24_cast_fu_737_p1 <= std_logic_vector(resize(signed(j_1_reg_298),38));
tmp_27_cast_fu_922_p1 <= std_logic_vector(resize(signed(i_4_reg_344),38));
tmp_27_fu_690_p1 <= i_3_reg_286(2 - 1 downto 0);
tmp_28_fu_791_p2 <= "1" when (signed(k_1_cast_fu_787_p1) < signed(tmp_26_reg_1534)) else "0";
tmp_29_fu_970_p2 <= "1" when (signed(j_2_cast_fu_966_p1) < signed(tmp_54_reg_1630)) else "0";
tmp_2_fu_1404_p2 <= "1" when (signed(i_cast_fu_1400_p1) < signed(P_config_read_reg_1470)) else "0";
tmp_30_fu_1026_p2 <= "1" when (signed(i_5_cast_fu_1022_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_31_fu_682_p1 <= tmp_11_fu_676_p2(9 - 1 downto 0);
tmp_33_fu_694_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_31_reg_1501))), 9));
tmp_34_fu_853_p1 <= tmp_34_neg_fu_847_p2;
tmp_34_neg_fu_847_p2 <= (tmp_34_to_int_fu_843_p1 xor ap_const_lv32_80000000);
tmp_34_to_int_fu_843_p1 <= reg_574;
tmp_3_fu_633_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),64));
tmp_40_fu_686_p1 <= tmp_11_fu_676_p2(2 - 1 downto 0);
tmp_46_fu_871_p1 <= grp_fu_666_p2(9 - 1 downto 0);
tmp_48_fu_1051_p2 <= "1" when (P_mode_read_reg_1443 = ap_const_lv32_3) else "0";
tmp_49_fu_1113_p2 <= "1" when (signed(i_6_cast_fu_1109_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_4_cast_fu_1310_p1 <= std_logic_vector(resize(signed(j_reg_458),38));
tmp_4_fu_1415_p1 <= i_reg_480(2 - 1 downto 0);
tmp_50_fu_1060_p2 <= "1" when (signed(p_netOut_2_cast_fu_1056_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_51_fu_875_p1 <= grp_fu_666_p2(38 - 1 downto 0);
tmp_52_fu_672_p1 <= tmp_13_fu_657_p2(2 - 1 downto 0);
tmp_53_fu_863_p1 <= tmp_15_fu_858_p2(9 - 1 downto 0);
tmp_55_fu_1230_p2 <= "1" when (signed(j_3_reg_435) < signed(tmp_66_fu_1217_p6)) else "0";
tmp_56_fu_879_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_53_reg_1589))), 9));
tmp_57_fu_1132_p4 <= p_uOut_load_3_to_int_fu_1128_p1(30 downto 23);
tmp_58_fu_867_p1 <= tmp_15_fu_858_p2(2 - 1 downto 0);
tmp_59_fu_1149_p4 <= p_uOut_load_4_to_int_fu_1146_p1(30 downto 23);
tmp_60_fu_1386_p1 <= k_reg_469(14 - 1 downto 0);
tmp_61_fu_1175_p2 <= (notrhs_fu_1169_p2 or notlhs_fu_1163_p2);
tmp_62_fu_1193_p2 <= (notrhs2_fu_1187_p2 or notlhs1_fu_1181_p2);
tmp_63_fu_1199_p2 <= (tmp_61_fu_1175_p2 and tmp_62_fu_1193_p2);
tmp_64_fu_515_opcode <= ap_const_lv5_2;
tmp_65_fu_1205_p2 <= (tmp_63_fu_1199_p2 and tmp_64_fu_515_p2);
tmp_67_fu_1390_p2 <= std_logic_vector(unsigned(tmp_23_reg_1804) + unsigned(tmp_60_fu_1386_p1));
tmp_68_fu_741_p2 <= std_logic_vector(signed(tmp_24_cast_fu_737_p1) + signed(tmp_24_reg_1511));
tmp_69_fu_751_p1 <= tmp_68_fu_741_p2(9 - 1 downto 0);
tmp_6_fu_1260_p2 <= "1" when (signed(i_1_cast_fu_1256_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_70_fu_763_p1 <= tmp_68_fu_741_p2(12 - 1 downto 0);
tmp_71_fu_775_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_755_p3) + unsigned(p_shl3_cast_fu_767_p3));
tmp_72_fu_926_p2 <= std_logic_vector(signed(tmp_27_cast_fu_922_p1) + signed(tmp_51_reg_1606));
tmp_73_fu_936_p1 <= tmp_72_fu_926_p2(9 - 1 downto 0);
tmp_74_fu_948_p1 <= tmp_72_fu_926_p2(12 - 1 downto 0);
tmp_75_fu_960_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_940_p3) + unsigned(p_shl5_cast_fu_952_p3));
tmp_76_cast_fu_1395_p1 <= std_logic_vector(resize(unsigned(tmp_67_fu_1390_p2),64));
tmp_76_fu_1037_p1 <= i_5_reg_378(9 - 1 downto 0);
tmp_77_cast_fu_746_p1 <= std_logic_vector(resize(signed(tmp_68_fu_741_p2),64));
tmp_77_fu_1041_p2 <= std_logic_vector(unsigned(tmp_46_reg_1599) + unsigned(tmp_76_fu_1037_p1));
tmp_78_fu_802_p1 <= k_1_reg_321(9 - 1 downto 0);
tmp_79_fu_806_p1 <= k_1_reg_321(14 - 1 downto 0);
tmp_7_fu_622_p2 <= "1" when (signed(i_2_cast_fu_618_p1) < signed(ST_layerSize_0_load_reg_1465)) else "0";
tmp_80_fu_810_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_79_fu_806_p1));
tmp_81_cast_fu_931_p1 <= std_logic_vector(resize(signed(tmp_72_fu_926_p2),64));
tmp_81_fu_820_p2 <= std_logic_vector(unsigned(tmp_33_reg_1521) + unsigned(tmp_78_fu_802_p1));
tmp_82_fu_830_p1 <= tmp_26_reg_1534(14 - 1 downto 0);
tmp_83_fu_833_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_82_fu_830_p1));
tmp_84_fu_981_p1 <= j_2_reg_367(9 - 1 downto 0);
tmp_85_cast_fu_815_p1 <= std_logic_vector(resize(unsigned(tmp_80_fu_810_p2),64));
tmp_85_fu_985_p1 <= j_2_reg_367(14 - 1 downto 0);
tmp_86_cast_fu_825_p1 <= std_logic_vector(resize(signed(tmp_81_fu_820_p2),64));
tmp_86_fu_989_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_85_fu_985_p1));
tmp_87_cast_fu_838_p1 <= std_logic_vector(resize(unsigned(tmp_83_fu_833_p2),64));
tmp_87_fu_999_p2 <= std_logic_vector(unsigned(tmp_56_reg_1611) + unsigned(tmp_84_fu_981_p1));
tmp_88_cast_fu_994_p1 <= std_logic_vector(resize(unsigned(tmp_86_fu_989_p2),64));
tmp_88_fu_1009_p1 <= tmp_54_reg_1630(14 - 1 downto 0);
tmp_89_cast_fu_1004_p1 <= std_logic_vector(resize(signed(tmp_87_fu_999_p2),64));
tmp_89_fu_1012_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_88_fu_1009_p1));
tmp_90_cast_fu_1017_p1 <= std_logic_vector(resize(unsigned(tmp_89_fu_1012_p2),64));
tmp_90_fu_1099_p1 <= phi_mul_reg_424(9 - 1 downto 0);
tmp_91_cast_fu_1046_p1 <= std_logic_vector(resize(signed(tmp_77_fu_1041_p2),64));
tmp_91_fu_1124_p1 <= i_6_reg_413(2 - 1 downto 0);
tmp_92_fu_1065_p1 <= p_netOut_2_reg_402(9 - 1 downto 0);
tmp_93_cast_fu_1074_p1 <= std_logic_vector(resize(signed(tmp_93_fu_1069_p2),64));
tmp_93_fu_1069_p2 <= std_logic_vector(unsigned(tmp_92_fu_1065_p1) + unsigned(tmp_46_reg_1599));
tmp_94_cast_fu_1088_p1 <= std_logic_vector(resize(signed(tmp_94_fu_1083_p2),64));
tmp_94_fu_1083_p2 <= std_logic_vector(unsigned(tmp_96_fu_1079_p1) + unsigned(tmp_46_reg_1599));
tmp_95_cast_fu_1251_p1 <= std_logic_vector(resize(unsigned(tmp_95_fu_1246_p2),64));
tmp_95_fu_1246_p2 <= std_logic_vector(unsigned(tmp_90_reg_1720) + unsigned(tmp_99_fu_1242_p1));
tmp_96_fu_1079_p1 <= p_netOut_reg_389(9 - 1 downto 0);
tmp_97_fu_1142_p1 <= p_uOut_load_3_to_int_fu_1128_p1(23 - 1 downto 0);
tmp_98_fu_1159_p1 <= p_uOut_load_4_to_int_fu_1146_p1(23 - 1 downto 0);
tmp_99_fu_1242_p1 <= j_3_reg_435(9 - 1 downto 0);
tmp_9_fu_642_p2 <= "1" when (signed(i_3_cast_fu_638_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_9_t_fu_1279_p2 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_10_fu_1275_p1));
tmp_fu_596_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_s_fu_1298_p2 <= "1" when (signed(j_reg_458) < signed(tmp_5_fu_1285_p6)) else "0";
end behav;
|
-------------------------------------------------------------------------------
--
-- $Id: t400_pack-p.vhd,v 1.4 2008-05-01 19:51:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package t400_pack is
-- Byte ---------------------------------------------------------------------
subtype byte_t is std_logic_vector(7 downto 0);
-- Data word ----------------------------------------------------------------
subtype dw_t is std_logic_vector(3 downto 0);
-- Misc ranges --------------------------------------------------------------
subtype dw_range_t is natural range dw_t'range;
subtype b_range_t is natural range 5 downto 0;
subtype br_range_t is natural range 5 downto 4;
subtype bd_range_t is natural range 3 downto 0;
-- B address ----------------------------------------------------------------
subtype b_t is std_logic_vector(b_range_t);
subtype br_t is std_logic_vector(br_range_t);
subtype bd_t is std_logic_vector(bd_range_t);
-- Program counter ----------------------------------------------------------
subtype pc_t is unsigned(9 downto 0);
-- Data memory address vector -----------------------------------------------
subtype dm_addr_t is std_logic_vector(5 downto 0);
-- Decoder data -------------------------------------------------------------
subtype dec_data_t is std_logic_vector(pc_t'range);
-- Program counter operations -----------------------------------------------
type pc_op_t is (PC_NONE,
PC_INC_PC,
PC_LOAD_6, PC_LOAD_7, PC_LOAD_8, PC_LOAD,
PC_POP,
PC_LOAD_A_M,
PC_INT);
-- Data memory controller operations ----------------------------------------
type dmem_op_t is (DMEM_RB,
DMEM_WB_SRC_Q, DMEM_WB_SRC_DEC, DMEM_WB_SRC_A,
DMEM_RDEC,
DMEM_WB_SET_BIT, DMEM_WB_RES_BIT,
DMEM_WDEC_SRC_A);
type b_op_t is (B_NONE,
B_SET_BD, B_SET_BR,
B_SET_B, B_SET_B_INC,
B_XOR_BR,
B_INC_BD,
B_DEC_BD);
-- Stack operations ---------------------------------------------------------
type stack_op_t is (STACK_NONE,
STACK_PUSH,
STACK_POP);
-- ALU operations -----------------------------------------------------------
type alu_op_t is (ALU_NONE,
ALU_CLRA,
ALU_LOAD_M,
ALU_LOAD_Q, ALU_LOAD_G, ALU_LOAD_IN, ALU_LOAD_IL,
ALU_LOAD_BR, ALU_LOAD_BD,
ALU_LOAD_SIO,
ALU_ADD, ALU_ADD_10, ALU_ADD_C, ALU_ADD_DEC,
ALU_COMP,
ALU_RC, ALU_SC,
ALU_XOR);
-- Skip operations ----------------------------------------------------------
type skip_op_t is (SKIP_NONE,
SKIP_UPDATE,
SKIP_NOW,
SKIP_CARRY, SKIP_C,
SKIP_BD_UFLOW, SKIP_BD_OFLOW,
SKIP_LBI,
SKIP_A_M,
SKIP_G_ZERO, SKIP_G_BIT,
SKIP_M_BIT,
SKIP_TIMER,
SKIP_PUSH, SKIP_POP);
-- IO L port operations -----------------------------------------------------
type io_l_op_t is (IOL_NONE,
IOL_LOAD_AM, IOL_LOAD_PM,
IOL_OUTPUT_L,
IOL_OUTPUT_Q);
-- IO D port operations -----------------------------------------------------
type io_d_op_t is (IOD_NONE,
IOD_LOAD);
-- IO G port operations -----------------------------------------------------
type io_g_op_t is (IOG_NONE,
IOG_LOAD_M,
IOG_LOAD_DEC);
-- IO IN port operations ----------------------------------------------------
type io_in_op_t is (IOIN_NONE,
IOIN_INIL,
IOIN_INTACK);
-- SIO operations -----------------------------------------------------------
type sio_op_t is (SIO_NONE,
SIO_LOAD);
end t400_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2006/05/27 19:16:52 arniml
-- interrupt functionality added
--
-- Revision 1.2 2006/05/22 00:01:21 arniml
-- operations for IN port added
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_sp605
-- File: ahb2mig_sp605.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_sp605 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem_p : in std_logic;
clk_mem_n : in std_logic;
clk_125 : out std_logic;
clk_50 : out std_logic
);
end ;
architecture rtl of ahb2mig_sp605 is
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.hirq <= (others => '0');
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : entity work.mig_38 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
-- C3_MEMCLK_PERIOD => 5000,
C3_RST_ACT_LOW => 1,
C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => clk_mem_p,
c3_sys_clk_n => clk_mem_n,
c3_sys_rst_i => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error,
clk_125 => clk_125,
clk_50 => clk_50
);
end;
|
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
MEM_SIB_SEL : out STD_LOGIC;
-- RAM interface
RAM_data_read : in STD_LOGIC_VECTOR (DataSize-1 downto 0);
RAM_data_write : out STD_LOGIC_VECTOR (DataSize-1 downto 0);
RAM_address_out : out STD_LOGIC_VECTOR (AddressSize-1 downto 0);
RAM_write_enable : out STD_LOGIC
);
end RAMAccessInstrument;
architecture RAMAccessInstrument_arch of RAMAccessInstrument is
signal RAM_address, RAM_address_update: STD_LOGIC_VECTOR (AddressSize-1 downto 0);
signal RAM_addr_inc_reg: STD_LOGIC;
signal RAM_write_enable_internal : STD_LOGIC;
signal RAM_write_enable_strobe : STD_LOGIC;
signal RAM_data_write_internal: STD_LOGIC_VECTOR (DataSize-1 downto 0);
signal sib_addr_update_strobe, sib_data_update_strobe: STD_LOGIC;
signal sib_addr_toUE_prev, sib_data_toUE_prev: STD_LOGIC;
signal Addr_service_bits, Addr_service_bits_update: STD_LOGIC_VECTOR (1 downto 0);
signal sib_mem_so, sib_data_so, sib_addr_so, addr_sreg_so, service_sreg_so: STD_LOGIC;
signal data_sreg_so: STD_LOGIC;
signal sib_mem_toCE, sib_data_toCE, sib_addr_toCE: STD_LOGIC;
signal sib_mem_toSE, sib_data_toSE, sib_addr_toSE: STD_LOGIC;
signal sib_mem_toUE, sib_data_toUE, sib_addr_toUE: STD_LOGIC;
signal sib_mem_toSEL, sib_data_toSEL, sib_addr_toSEL: STD_LOGIC;
signal sib_mem_toRST, sib_data_toRST, sib_addr_toRST: STD_LOGIC;
signal sib_mem_toTCK, sib_data_toTCK, sib_addr_toTCK: STD_LOGIC;
signal sib_mem_toSI, sib_data_toSI, sib_addr_toSI: STD_LOGIC;
component SReg is
Generic ( Size : positive := 33);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
component SIB_mux_pre is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC); -- ScanOutPort
end component;
begin
RAM_address_out <= RAM_address;
RAM_data_write <= RAM_data_write_internal;
RAM_write_enable <= RAM_write_enable_strobe and RAM_write_enable_internal;
-- .-------.
-- SI -----|sib_mem|-- SO
-- '-------'
-- | |_________________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib_data |--------------------->| sib_addr |----'
-- '----------' '------------'
-- | |_____________ | |______________
-- | _____________ | | ______ _______ |
-- '--->| data |-' '->|we,inc|-|address|-'
-- '-------------' '------' '-------'
-- Auto increment bit is MSb in Address shift register
SO <= sib_mem_so;
MEM_SIB_SEL <= sib_mem_toSEL;
-- Top-level SIB for integration into system's IJTAG network
sib_mem : SIB_mux_pre
port map (
SI => SI,
SE => SE,
UE => UE,
CE => CE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => sib_mem_so,
fromSO => sib_addr_so,
toCE => sib_mem_toCE,
toSE => sib_mem_toSE,
toUE => sib_mem_toUE,
toSEL => sib_mem_toSEL,
toRST => sib_mem_toRST,
toTCK => sib_mem_toTCK,
toSI => sib_mem_toSI);
-- Underlying SIB for efficient access to RAM data
sib_data : SIB_mux_pre
port map (
SI => sib_mem_toSI,
SE => sib_mem_toSE,
UE => sib_mem_toUE,
CE => sib_mem_toCE,
SEL => sib_mem_toSEL,
RST => sib_mem_toRST,
TCK => sib_mem_toTCK,
SO => sib_data_so,
fromSO => data_sreg_so,
toCE => sib_data_toCE,
toSE => sib_data_toSE,
toUE => sib_data_toUE,
toSEL => sib_data_toSEL,
toRST => sib_data_toRST,
toTCK => sib_data_toTCK,
toSI => sib_data_toSI);
-- Shift register for RAM data
data_shiftreg : SReg
Generic map ( Size => DataSize)
Port map ( -- Scan Interface scan_client ----------
SI => sib_data_toSI, -- Input Port SI = SI
SO => data_sreg_so,
SEL => sib_data_toSEL,
SE => sib_data_toSE,
UE => sib_data_toUE,
CE => sib_data_toCE,
RST => sib_data_toRST,
TCK => sib_data_toTCK,
DI => RAM_data_read,
DO => RAM_data_write_internal);
-- Underlying SIB for setting access address
sib_addr : SIB_mux_pre
port map (
SI => sib_data_so,
SE => sib_mem_toSE,
UE => sib_mem_toUE,
CE => sib_mem_toCE,
SEL => sib_mem_toSEL,
RST => sib_mem_toRST,
TCK => sib_mem_toTCK,
SO => sib_addr_so,
fromSO => addr_sreg_so,
toCE => sib_addr_toCE,
toSE => sib_addr_toSE,
toUE => sib_addr_toUE,
toSEL => sib_addr_toSEL,
toRST => sib_addr_toRST,
toTCK => sib_addr_toTCK,
toSI => sib_addr_toSI);
-- Shift register for Address increment bit and write enable bit
service_bits_shiftreg : SReg
Generic map ( Size => 2)
Port map ( -- Scan Interface scan_client ----------
SI => sib_addr_toSI,
SO => service_sreg_so,
SEL => sib_addr_toSEL,
SE => sib_addr_toSE,
CE => sib_addr_toCE,
UE => sib_addr_toUE,
RST => sib_addr_toRST,
TCK => sib_addr_toTCK,
DI => Addr_service_bits,
DO => Addr_service_bits_update);
Addr_service_bits <= RAM_write_enable_internal & RAM_addr_inc_reg;
-- Shift register for RAM address
addr_shiftreg : SReg
Generic map ( Size => AddressSize)
Port map ( -- Scan Interface scan_client ----------
SI => service_sreg_so,
SO => addr_sreg_so,
SEL => sib_addr_toSEL,
SE => sib_addr_toSE,
CE => sib_addr_toCE,
UE => sib_addr_toUE,
RST => sib_addr_toRST,
TCK => sib_addr_toTCK,
DI => RAM_address,
DO => RAM_address_update);
update_strobes: process(TCK)
begin
if TCK'event and TCK = '0' then
sib_addr_toUE_prev <= sib_addr_toUE;
sib_data_toUE_prev <= sib_data_toUE;
sib_addr_update_strobe <= not sib_addr_toUE_prev and sib_addr_toUE and sib_addr_toSEL;
sib_data_update_strobe <= not sib_data_toUE_prev and sib_data_toUE and sib_data_toSEL;
end if;
end process;
service_bits: process(TCK, RST)
begin
if RST = '1' then
RAM_addr_inc_reg <= '0';
RAM_write_enable_internal <= '0';
elsif TCK'event and TCK = '0' then
RAM_addr_inc_reg <= Addr_service_bits_update(0); -- Auto increment bit
RAM_write_enable_internal <= Addr_service_bits_update(1); -- Write enable bit
end if;
end process;
data_write_strobe_delay: process(TCK, RST)
begin
if RST = '1' then
RAM_write_enable_strobe <= '0';
elsif TCK'event and TCK = '0' then
RAM_write_enable_strobe <= sib_data_update_strobe;
end if;
end process;
address_set: process(TCK, RST)
begin
if RST = '1' then
RAM_address <= (others => '0');
elsif TCK'event and TCK = '0' then
if sib_addr_update_strobe = '1' then
RAM_address <= RAM_address_update;
elsif RAM_write_enable_strobe = '1' and RAM_addr_inc_reg = '1' then
RAM_address <= std_logic_vector(unsigned(RAM_address) + 1);
end if;
end if;
end process;
end RAMAccessInstrument_arch; |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
MEM_SIB_SEL : out STD_LOGIC;
-- RAM interface
RAM_data_read : in STD_LOGIC_VECTOR (DataSize-1 downto 0);
RAM_data_write : out STD_LOGIC_VECTOR (DataSize-1 downto 0);
RAM_address_out : out STD_LOGIC_VECTOR (AddressSize-1 downto 0);
RAM_write_enable : out STD_LOGIC
);
end RAMAccessInstrument;
architecture RAMAccessInstrument_arch of RAMAccessInstrument is
signal RAM_address, RAM_address_update: STD_LOGIC_VECTOR (AddressSize-1 downto 0);
signal RAM_addr_inc_reg: STD_LOGIC;
signal RAM_write_enable_internal : STD_LOGIC;
signal RAM_write_enable_strobe : STD_LOGIC;
signal RAM_data_write_internal: STD_LOGIC_VECTOR (DataSize-1 downto 0);
signal sib_addr_update_strobe, sib_data_update_strobe: STD_LOGIC;
signal sib_addr_toUE_prev, sib_data_toUE_prev: STD_LOGIC;
signal Addr_service_bits, Addr_service_bits_update: STD_LOGIC_VECTOR (1 downto 0);
signal sib_mem_so, sib_data_so, sib_addr_so, addr_sreg_so, service_sreg_so: STD_LOGIC;
signal data_sreg_so: STD_LOGIC;
signal sib_mem_toCE, sib_data_toCE, sib_addr_toCE: STD_LOGIC;
signal sib_mem_toSE, sib_data_toSE, sib_addr_toSE: STD_LOGIC;
signal sib_mem_toUE, sib_data_toUE, sib_addr_toUE: STD_LOGIC;
signal sib_mem_toSEL, sib_data_toSEL, sib_addr_toSEL: STD_LOGIC;
signal sib_mem_toRST, sib_data_toRST, sib_addr_toRST: STD_LOGIC;
signal sib_mem_toTCK, sib_data_toTCK, sib_addr_toTCK: STD_LOGIC;
signal sib_mem_toSI, sib_data_toSI, sib_addr_toSI: STD_LOGIC;
component SReg is
Generic ( Size : positive := 33);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
component SIB_mux_pre is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC); -- ScanOutPort
end component;
begin
RAM_address_out <= RAM_address;
RAM_data_write <= RAM_data_write_internal;
RAM_write_enable <= RAM_write_enable_strobe and RAM_write_enable_internal;
-- .-------.
-- SI -----|sib_mem|-- SO
-- '-------'
-- | |_________________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib_data |--------------------->| sib_addr |----'
-- '----------' '------------'
-- | |_____________ | |______________
-- | _____________ | | ______ _______ |
-- '--->| data |-' '->|we,inc|-|address|-'
-- '-------------' '------' '-------'
-- Auto increment bit is MSb in Address shift register
SO <= sib_mem_so;
MEM_SIB_SEL <= sib_mem_toSEL;
-- Top-level SIB for integration into system's IJTAG network
sib_mem : SIB_mux_pre
port map (
SI => SI,
SE => SE,
UE => UE,
CE => CE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => sib_mem_so,
fromSO => sib_addr_so,
toCE => sib_mem_toCE,
toSE => sib_mem_toSE,
toUE => sib_mem_toUE,
toSEL => sib_mem_toSEL,
toRST => sib_mem_toRST,
toTCK => sib_mem_toTCK,
toSI => sib_mem_toSI);
-- Underlying SIB for efficient access to RAM data
sib_data : SIB_mux_pre
port map (
SI => sib_mem_toSI,
SE => sib_mem_toSE,
UE => sib_mem_toUE,
CE => sib_mem_toCE,
SEL => sib_mem_toSEL,
RST => sib_mem_toRST,
TCK => sib_mem_toTCK,
SO => sib_data_so,
fromSO => data_sreg_so,
toCE => sib_data_toCE,
toSE => sib_data_toSE,
toUE => sib_data_toUE,
toSEL => sib_data_toSEL,
toRST => sib_data_toRST,
toTCK => sib_data_toTCK,
toSI => sib_data_toSI);
-- Shift register for RAM data
data_shiftreg : SReg
Generic map ( Size => DataSize)
Port map ( -- Scan Interface scan_client ----------
SI => sib_data_toSI, -- Input Port SI = SI
SO => data_sreg_so,
SEL => sib_data_toSEL,
SE => sib_data_toSE,
UE => sib_data_toUE,
CE => sib_data_toCE,
RST => sib_data_toRST,
TCK => sib_data_toTCK,
DI => RAM_data_read,
DO => RAM_data_write_internal);
-- Underlying SIB for setting access address
sib_addr : SIB_mux_pre
port map (
SI => sib_data_so,
SE => sib_mem_toSE,
UE => sib_mem_toUE,
CE => sib_mem_toCE,
SEL => sib_mem_toSEL,
RST => sib_mem_toRST,
TCK => sib_mem_toTCK,
SO => sib_addr_so,
fromSO => addr_sreg_so,
toCE => sib_addr_toCE,
toSE => sib_addr_toSE,
toUE => sib_addr_toUE,
toSEL => sib_addr_toSEL,
toRST => sib_addr_toRST,
toTCK => sib_addr_toTCK,
toSI => sib_addr_toSI);
-- Shift register for Address increment bit and write enable bit
service_bits_shiftreg : SReg
Generic map ( Size => 2)
Port map ( -- Scan Interface scan_client ----------
SI => sib_addr_toSI,
SO => service_sreg_so,
SEL => sib_addr_toSEL,
SE => sib_addr_toSE,
CE => sib_addr_toCE,
UE => sib_addr_toUE,
RST => sib_addr_toRST,
TCK => sib_addr_toTCK,
DI => Addr_service_bits,
DO => Addr_service_bits_update);
Addr_service_bits <= RAM_write_enable_internal & RAM_addr_inc_reg;
-- Shift register for RAM address
addr_shiftreg : SReg
Generic map ( Size => AddressSize)
Port map ( -- Scan Interface scan_client ----------
SI => service_sreg_so,
SO => addr_sreg_so,
SEL => sib_addr_toSEL,
SE => sib_addr_toSE,
CE => sib_addr_toCE,
UE => sib_addr_toUE,
RST => sib_addr_toRST,
TCK => sib_addr_toTCK,
DI => RAM_address,
DO => RAM_address_update);
update_strobes: process(TCK)
begin
if TCK'event and TCK = '0' then
sib_addr_toUE_prev <= sib_addr_toUE;
sib_data_toUE_prev <= sib_data_toUE;
sib_addr_update_strobe <= not sib_addr_toUE_prev and sib_addr_toUE and sib_addr_toSEL;
sib_data_update_strobe <= not sib_data_toUE_prev and sib_data_toUE and sib_data_toSEL;
end if;
end process;
service_bits: process(TCK, RST)
begin
if RST = '1' then
RAM_addr_inc_reg <= '0';
RAM_write_enable_internal <= '0';
elsif TCK'event and TCK = '0' then
RAM_addr_inc_reg <= Addr_service_bits_update(0); -- Auto increment bit
RAM_write_enable_internal <= Addr_service_bits_update(1); -- Write enable bit
end if;
end process;
data_write_strobe_delay: process(TCK, RST)
begin
if RST = '1' then
RAM_write_enable_strobe <= '0';
elsif TCK'event and TCK = '0' then
RAM_write_enable_strobe <= sib_data_update_strobe;
end if;
end process;
address_set: process(TCK, RST)
begin
if RST = '1' then
RAM_address <= (others => '0');
elsif TCK'event and TCK = '0' then
if sib_addr_update_strobe = '1' then
RAM_address <= RAM_address_update;
elsif RAM_write_enable_strobe = '1' and RAM_addr_inc_reg = '1' then
RAM_address <= std_logic_vector(unsigned(RAM_address) + 1);
end if;
end if;
end process;
end RAMAccessInstrument_arch; |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
MEM_SIB_SEL : out STD_LOGIC;
-- RAM interface
RAM_data_read : in STD_LOGIC_VECTOR (DataSize-1 downto 0);
RAM_data_write : out STD_LOGIC_VECTOR (DataSize-1 downto 0);
RAM_address_out : out STD_LOGIC_VECTOR (AddressSize-1 downto 0);
RAM_write_enable : out STD_LOGIC
);
end RAMAccessInstrument;
architecture RAMAccessInstrument_arch of RAMAccessInstrument is
signal RAM_address, RAM_address_update: STD_LOGIC_VECTOR (AddressSize-1 downto 0);
signal RAM_addr_inc_reg: STD_LOGIC;
signal RAM_write_enable_internal : STD_LOGIC;
signal RAM_write_enable_strobe : STD_LOGIC;
signal RAM_data_write_internal: STD_LOGIC_VECTOR (DataSize-1 downto 0);
signal sib_addr_update_strobe, sib_data_update_strobe: STD_LOGIC;
signal sib_addr_toUE_prev, sib_data_toUE_prev: STD_LOGIC;
signal Addr_service_bits, Addr_service_bits_update: STD_LOGIC_VECTOR (1 downto 0);
signal sib_mem_so, sib_data_so, sib_addr_so, addr_sreg_so, service_sreg_so: STD_LOGIC;
signal data_sreg_so: STD_LOGIC;
signal sib_mem_toCE, sib_data_toCE, sib_addr_toCE: STD_LOGIC;
signal sib_mem_toSE, sib_data_toSE, sib_addr_toSE: STD_LOGIC;
signal sib_mem_toUE, sib_data_toUE, sib_addr_toUE: STD_LOGIC;
signal sib_mem_toSEL, sib_data_toSEL, sib_addr_toSEL: STD_LOGIC;
signal sib_mem_toRST, sib_data_toRST, sib_addr_toRST: STD_LOGIC;
signal sib_mem_toTCK, sib_data_toTCK, sib_addr_toTCK: STD_LOGIC;
signal sib_mem_toSI, sib_data_toSI, sib_addr_toSI: STD_LOGIC;
component SReg is
Generic ( Size : positive := 33);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
component SIB_mux_pre is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC); -- ScanOutPort
end component;
begin
RAM_address_out <= RAM_address;
RAM_data_write <= RAM_data_write_internal;
RAM_write_enable <= RAM_write_enable_strobe and RAM_write_enable_internal;
-- .-------.
-- SI -----|sib_mem|-- SO
-- '-------'
-- | |_________________________________________________.
-- | |
-- | .----------. .------------. |
-- '--| sib_data |--------------------->| sib_addr |----'
-- '----------' '------------'
-- | |_____________ | |______________
-- | _____________ | | ______ _______ |
-- '--->| data |-' '->|we,inc|-|address|-'
-- '-------------' '------' '-------'
-- Auto increment bit is MSb in Address shift register
SO <= sib_mem_so;
MEM_SIB_SEL <= sib_mem_toSEL;
-- Top-level SIB for integration into system's IJTAG network
sib_mem : SIB_mux_pre
port map (
SI => SI,
SE => SE,
UE => UE,
CE => CE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => sib_mem_so,
fromSO => sib_addr_so,
toCE => sib_mem_toCE,
toSE => sib_mem_toSE,
toUE => sib_mem_toUE,
toSEL => sib_mem_toSEL,
toRST => sib_mem_toRST,
toTCK => sib_mem_toTCK,
toSI => sib_mem_toSI);
-- Underlying SIB for efficient access to RAM data
sib_data : SIB_mux_pre
port map (
SI => sib_mem_toSI,
SE => sib_mem_toSE,
UE => sib_mem_toUE,
CE => sib_mem_toCE,
SEL => sib_mem_toSEL,
RST => sib_mem_toRST,
TCK => sib_mem_toTCK,
SO => sib_data_so,
fromSO => data_sreg_so,
toCE => sib_data_toCE,
toSE => sib_data_toSE,
toUE => sib_data_toUE,
toSEL => sib_data_toSEL,
toRST => sib_data_toRST,
toTCK => sib_data_toTCK,
toSI => sib_data_toSI);
-- Shift register for RAM data
data_shiftreg : SReg
Generic map ( Size => DataSize)
Port map ( -- Scan Interface scan_client ----------
SI => sib_data_toSI, -- Input Port SI = SI
SO => data_sreg_so,
SEL => sib_data_toSEL,
SE => sib_data_toSE,
UE => sib_data_toUE,
CE => sib_data_toCE,
RST => sib_data_toRST,
TCK => sib_data_toTCK,
DI => RAM_data_read,
DO => RAM_data_write_internal);
-- Underlying SIB for setting access address
sib_addr : SIB_mux_pre
port map (
SI => sib_data_so,
SE => sib_mem_toSE,
UE => sib_mem_toUE,
CE => sib_mem_toCE,
SEL => sib_mem_toSEL,
RST => sib_mem_toRST,
TCK => sib_mem_toTCK,
SO => sib_addr_so,
fromSO => addr_sreg_so,
toCE => sib_addr_toCE,
toSE => sib_addr_toSE,
toUE => sib_addr_toUE,
toSEL => sib_addr_toSEL,
toRST => sib_addr_toRST,
toTCK => sib_addr_toTCK,
toSI => sib_addr_toSI);
-- Shift register for Address increment bit and write enable bit
service_bits_shiftreg : SReg
Generic map ( Size => 2)
Port map ( -- Scan Interface scan_client ----------
SI => sib_addr_toSI,
SO => service_sreg_so,
SEL => sib_addr_toSEL,
SE => sib_addr_toSE,
CE => sib_addr_toCE,
UE => sib_addr_toUE,
RST => sib_addr_toRST,
TCK => sib_addr_toTCK,
DI => Addr_service_bits,
DO => Addr_service_bits_update);
Addr_service_bits <= RAM_write_enable_internal & RAM_addr_inc_reg;
-- Shift register for RAM address
addr_shiftreg : SReg
Generic map ( Size => AddressSize)
Port map ( -- Scan Interface scan_client ----------
SI => service_sreg_so,
SO => addr_sreg_so,
SEL => sib_addr_toSEL,
SE => sib_addr_toSE,
CE => sib_addr_toCE,
UE => sib_addr_toUE,
RST => sib_addr_toRST,
TCK => sib_addr_toTCK,
DI => RAM_address,
DO => RAM_address_update);
update_strobes: process(TCK)
begin
if TCK'event and TCK = '0' then
sib_addr_toUE_prev <= sib_addr_toUE;
sib_data_toUE_prev <= sib_data_toUE;
sib_addr_update_strobe <= not sib_addr_toUE_prev and sib_addr_toUE and sib_addr_toSEL;
sib_data_update_strobe <= not sib_data_toUE_prev and sib_data_toUE and sib_data_toSEL;
end if;
end process;
service_bits: process(TCK, RST)
begin
if RST = '1' then
RAM_addr_inc_reg <= '0';
RAM_write_enable_internal <= '0';
elsif TCK'event and TCK = '0' then
RAM_addr_inc_reg <= Addr_service_bits_update(0); -- Auto increment bit
RAM_write_enable_internal <= Addr_service_bits_update(1); -- Write enable bit
end if;
end process;
data_write_strobe_delay: process(TCK, RST)
begin
if RST = '1' then
RAM_write_enable_strobe <= '0';
elsif TCK'event and TCK = '0' then
RAM_write_enable_strobe <= sib_data_update_strobe;
end if;
end process;
address_set: process(TCK, RST)
begin
if RST = '1' then
RAM_address <= (others => '0');
elsif TCK'event and TCK = '0' then
if sib_addr_update_strobe = '1' then
RAM_address <= RAM_address_update;
elsif RAM_write_enable_strobe = '1' and RAM_addr_inc_reg = '1' then
RAM_address <= std_logic_vector(unsigned(RAM_address) + 1);
end if;
end if;
end process;
end RAMAccessInstrument_arch; |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory management unit enables virtual address
-- support. Therefore it performs page table walks,
-- manages a TLB for faster translation and handles
-- page fault via the proc control unit.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
entity reconos_memif_mmu_microblaze is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_TLB_SIZE : integer := 128
);
port (
-- Input FIFO ports from the HWTs (via burst converter and transaction control)
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to memory controller
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Seperate control and data FIFOs (emulated) for page table walks
CTRL_FIFO_Mmu_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : out std_logic;
CTRL_FIFO_Mmu_RE : in std_logic;
MEMIF_FIFO_Mmu_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : out std_logic;
MEMIF_FIFO_Mmu_WE : in std_logic;
-- MMU ports
MMU_Pgf : out std_logic;
MMU_Fault_addr : out std_logic_vector(31 downto 0);
MMU_Retry : in std_logic;
MMU_Pgd : in std_logic_vector(31 downto 0);
MMU_Tlb_Hits : out std_logic_vector(31 downto 0);
MMU_Tlb_Misses : out std_logic_vector(31 downto 0);
MMU_Clk : in std_logic;
MMU_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(203 downto 0)
);
end entity reconos_memif_mmu_microblaze;
architecture implementation of reconos_memif_mmu_microblaze is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of MMU_Clk: SIGNAL is "xilinx.com:signal:clock:1.0 MMU_Clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of MMU_Clk: SIGNAL is "ASSOCIATED_RESET MMU_Rst, ASSOCIATED_BUSIF CTRL_FIFO_In:CTRL_FIFO_Out:CTRL_FIFO_Mmu:MEMIF_FIFO_Mmu";
ATTRIBUTE X_INTERFACE_INFO of MMU_Rst: SIGNAL is "xilinx.com:signal:reset:1.0 MMU_Rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER of MMU_Rst: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_In_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_In FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_In_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_In FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_In_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_In FIFO_S_RE";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_Out_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_Out FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_Out_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_Out FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_Out_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_Out FIFO_S_RE";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_Mmu_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_Mmu FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_Mmu_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_Mmu FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of CTRL_FIFO_Mmu_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 CTRL_FIFO_Mmu FIFO_S_RE";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_FIFO_Mmu_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_FIFO_Mmu FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_FIFO_Mmu_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_FIFO_Mmu FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_FIFO_Mmu_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_FIFO_Mmu FIFO_M_WE";
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
signal ctrl_mmu_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_mmu_fill : std_logic_vector(15 downto 0);
signal ctrl_mmu_empty : std_logic;
-- MMU signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR,
READ_L1_ENTRY_0, READ_L1_ENTRY_1, READ_L1_ENTRY_2,
READ_L2_ENTRY_0, READ_L2_ENTRY_1, READ_L2_ENTRY_2,
WRITE_CMD, WRITE_ADDR, PAGE_FAULT);
signal state : STATE_TYPE;
signal pgf : std_logic;
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal l1_table_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table
signal l1_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table entry
signal l2_table_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table
signal l2_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table entry
signal small_page_addr : std_logic_vector(31 downto 0); -- page table entry
signal physical_addr : std_logic_vector(31 downto 0); -- physical address
signal tlb_hit : std_logic;
signal tlb_tag : std_logic_vector(19 downto 0);
signal tlb_do : std_logic_vector(19 downto 0);
signal tlb_di : std_logic_vector(19 downto 0);
signal tlb_we : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
DEBUG_DATA(0) <= '1' when state = WAIT_REQUEST else '0';
DEBUG_DATA(1) <= '1' when state = READ_CMD else '0';
DEBUG_DATA(2) <= '1' when state = READ_ADDR else '0';
DEBUG_DATA(3) <= '1' when state = READ_L1_ENTRY_0 else '0';
DEBUG_DATA(4) <= '1' when state = READ_L1_ENTRY_1 else '0';
DEBUG_DATA(5) <= '1' when state = READ_L1_ENTRY_2 else '0';
DEBUG_DATA(6) <= '1' when state = READ_L2_ENTRY_0 else '0';
DEBUG_DATA(7) <= '1' when state = READ_L2_ENTRY_1 else '0';
DEBUG_DATA(8) <= '1' when state = READ_L2_ENTRY_2 else '0';
DEBUG_DATA(9) <= '1' when state = WRITE_CMD else '0';
DEBUG_DATA(10) <= '1' when state = WRITE_ADDR else '0';
DEBUG_DATA(11) <= '1' when state = PAGE_FAULT else '0';
DEBUG_DATA(203 downto 172) <= l1_table_addr;
DEBUG_DATA(171 downto 140) <= l1_descriptor_addr;
DEBUG_DATA(139 downto 108) <= l2_table_addr;
DEBUG_DATA(107 downto 76) <= l2_descriptor_addr;
DEBUG_DATA(75 downto 44) <= small_page_addr;
DEBUG_DATA(43 downto 12) <= physical_addr;
clk <= MMU_Clk;
rst <= MMU_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
CTRL_FIFO_Mmu_Data <= ctrl_mmu_data;
CTRL_FIFO_Mmu_Fill <= ctrl_mmu_fill;
CTRL_FIFO_Mmu_Empty <= ctrl_mmu_empty;
MEMIF_FIFO_Mmu_Rem <= X"1111";
MEMIF_FIFO_Mmu_Full <= '0';
MMU_Pgf <= pgf;
MMU_Fault_Addr <= ctrl_addr;
MMU_Tlb_Hits <= tlb_hits;
MMU_Tlb_Misses <= tlb_misses;
-- some address calculations based on the page table architecture
-- for detailed information look into the TRM on page 80
l1_table_addr <= MMU_Pgd;
l1_descriptor_addr <= "00" & l1_table_addr(29 downto 12) & ctrl_addr(31 downto 22) & "00";
l2_descriptor_addr <= "00" & l2_table_addr(29 downto 12) & ctrl_addr(21 downto 12) & "00";
physical_addr <= small_page_addr(31 downto 12) & ctrl_addr(11 downto 0);
mmu_proc : process(clk,rst) is
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= (others => '0');
ctrl_mmu_data <= (others => '0');
pgf <= '0';
tlb_hits <= (others => '0');
tlb_misses <= (others => '0');
elsif rising_edge(clk) then
tlb_we <= '0';
case state is
when WAIT_REQUEST =>
-- start reading if there are 2 word in FIFO
--if CTRL_FIFO_In_Empty = '0' and CTRL_FIFO_In_Fill >= X"0001" then
ctrl_in_re <= '1';
state <= READ_CMD;
--end if;
when READ_CMD =>
-- read cmd and length
if CTRL_FIFO_In_Empty = '0' then
ctrl_cmd <= CTRL_FIFO_In_Data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
-- read address
if CTRL_FIFO_In_Empty = '0' then
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
state <= READ_L1_ENTRY_0;
end if;
when READ_L1_ENTRY_0 =>
if tlb_hit = '1' then
small_page_addr(31 downto 12) <= tlb_do;
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_hits <= tlb_hits + 1;
state <= WRITE_CMD;
else
-- write command to memory controller
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l1_descriptor_addr;
tlb_misses <= tlb_misses + 1;
state <= READ_L1_ENTRY_1;
end if;
end if;
when READ_L1_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L1_ENTRY_2;
end if;
when READ_L1_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
l2_table_addr <= MEMIF_FIFO_Mmu_Data;
if or_reduce(MEMIF_FIFO_Mmu_Data) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
state <= READ_L2_ENTRY_0;
end if;
end if;
when READ_L2_ENTRY_0 =>
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l2_descriptor_addr;
state <= READ_L2_ENTRY_1;
end if;
when READ_L2_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L2_ENTRY_2;
end if;
when READ_L2_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
small_page_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_we <= '1';
state <= WRITE_CMD;
end if;
end if;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_fill <= X"0000";
ctrl_out_data <= physical_addr;
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
state <= WAIT_REQUEST;
end if;
when PAGE_FAULT =>
pgf <= '0';
if MMU_Retry = '1' then
pgf <= '0';
state <= READ_L1_ENTRY_0;
end if;
end case;
end if;
end process mmu_proc;
tlb_tag <= ctrl_addr(31 downto 12);
tlb_di <= small_page_addr(31 downto 12);
tlb_gen : if C_TLB_SIZE > 0 generate
tlb : entity work.reconos_memif_mmu_microblaze_tlb
generic map (
C_TLB_SIZE => C_TLB_SIZE,
C_TAG_SIZE => 20,
C_DATA_SIZE => 20
)
port map (
TLB_Tag => tlb_tag,
TLB_DI => tlb_di,
TLB_DO => tlb_do,
TLB_WE => tlb_we,
TLB_Hit => tlb_hit,
TLB_Clk => clk,
TLB_Rst => rst
);
end generate;
end architecture implementation;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-rtl-a.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ioblock0_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock0_e
--
architecture rtl of ioblock0_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_g_i --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_di : in std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
constant nand_out_0_c : std_ulogic := '0';
signal nand_out_0 : std_ulogic;
signal nand_out_1 : std_ulogic;
signal nand_out_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
nand_out_0 <= nand_out_0_c;
p_mix_nand_out_2_go <= nand_out_2; -- __I_O_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_g_i_1
ioc_g_i_1: ioc_g_i
port map (
di => data_i1, -- io data
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_0, -- Links ...
nand_out => nand_out_1, -- Links ...
p_di => pad_di_1, -- data in from pad
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_g_i_1
-- Generated Instance Port Map for ioc_g_o_2
ioc_g_o_2: ioc_g_o
port map (
do => data_o1, -- io data
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_1, -- Links ...
nand_out => nand_out_2, -- Links ...
p_do => pad_do_2, -- data out to pad
p_en => pad_en_2, -- pad output enable
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_g_o_2
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_credit_based_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
grants_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic
);
end LBDR_credit_based_pseudo;
architecture behavior of LBDR_credit_based_pseudo is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal grants: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
grants_out <= grants;
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, grants, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else -- Body flit
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
end; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY STD;
USE STD.textio.ALL;
USE ieee.numeric_std.ALL;
-- 16-bit Adder
ENTITY Adder IS
PORT (
A, B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
flag : OUT STD_LOGIC
);
END Adder;
ARCHITECTURE behavioural OF Adder IS
SIGNAL out_temp : INTEGER;
BEGIN
out_temp <= to_integer(unsigned(A)) + to_integer(unsigned(B));
PROCESS (out_temp)
BEGIN
IF out_temp <= 65535 THEN
flag <= '0';
output <= STD_LOGIC_VECTOR(to_unsigned(out_temp, 16));
ELSE
flag <= '1';
output <= "0000000000000000";
END IF;
END PROCESS;
END behavioural; |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package axilite_bfm_pkg is
--===============================================================================================
-- Types and constants for AXILITE BFMs
--===============================================================================================
constant C_SCOPE : string := "AXILITE BFM";
type t_axilite_response_status is (OKAY, SLVERR, DECERR, EXOKAY); -- EXOKAY not supported for AXI-Lite, will raise TB_FAILURE
type t_axilite_protection is(
UNPRIVILIGED_UNSECURE_DATA,
UNPRIVILIGED_UNSECURE_INSTRUCTION,
UNPRIVILIGED_SECURE_DATA,
UNPRIVILIGED_SECURE_INSTRUCTION,
PRIVILIGED_UNSECURE_DATA,
PRIVILIGED_UNSECURE_INSTRUCTION,
PRIVILIGED_SECURE_DATA,
PRIVILIGED_SECURE_INSTRUCTION
);
-- Configuration record to be assigned in the test harness.
type t_axilite_bfm_config is
record
max_wait_cycles : natural; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready and valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
expected_response : t_axilite_response_status; -- Sets the expected response for both read and write transactions.
expected_response_severity : t_alert_level; -- A response mismatch will have this severity.
protection_setting : t_axilite_protection; -- Sets the AXI access permissions (e.g. write to data/instruction, privileged and secure access).
num_aw_pipe_stages : natural; -- Write Address Channel pipeline steps.
num_w_pipe_stages : natural; -- Write Data Channel pipeline steps.
num_ar_pipe_stages : natural; -- Read Address Channel pipeline steps.
num_r_pipe_stages : natural; -- Read Data Channel pipeline steps.
num_b_pipe_stages : natural; -- Response Channel pipeline steps.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the AXI-Lite BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the AXI-Lite BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the AXI-Lite BFM
end record;
constant C_AXILITE_BFM_CONFIG_DEFAULT : t_axilite_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => TB_FAILURE,
clock_period => 10 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => 2.5 ns,
hold_time => 2.5 ns,
expected_response => OKAY,
expected_response_severity => TB_FAILURE,
protection_setting => UNPRIVILIGED_UNSECURE_DATA,
num_aw_pipe_stages => 1,
num_w_pipe_stages => 1,
num_ar_pipe_stages => 1,
num_r_pipe_stages => 1,
num_b_pipe_stages => 1,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_axilite_if_signals
------------------------------------------
-- - This function returns an AXILITE interface with initialized signals.
-- - All AXILITE input signals are initialized to 0
-- - All AXILITE output signals are initialized to Z
-- - awprot and arprot are initialized to UNPRIVILIGED_UNSECURE_DATA
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if;
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - The protection setting is set to UNPRIVILIGED_UNSECURE_DATA in this procedure
-- - The byte enable input is set to 1 for all bytes in this procedure
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_read
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and returns the read data in data_value.
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axilite_check
);
------------------------------------------
-- axilite_check
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and compares it to the data in data_exp.
-- - If the received data inconsistent with data_exp, an alert with severity
-- alert_level is issued.
-- - If the received data was correct, a log message with ID id_for_bfm is issued.
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
end package axilite_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body axilite_bfm_pkg is
----------------------------------------------------
-- Support procedures
----------------------------------------------------
function to_slv(
protection : t_axilite_protection
) return std_logic_vector is
variable v_prot_slv : std_logic_vector(2 downto 0);
begin
case protection is
when UNPRIVILIGED_UNSECURE_DATA =>
v_prot_slv := "010";
when UNPRIVILIGED_UNSECURE_INSTRUCTION =>
v_prot_slv := "011";
when UNPRIVILIGED_SECURE_DATA =>
v_prot_slv := "000";
when UNPRIVILIGED_SECURE_INSTRUCTION =>
v_prot_slv := "001";
when PRIVILIGED_UNSECURE_DATA =>
v_prot_slv := "110";
when PRIVILIGED_UNSECURE_INSTRUCTION =>
v_prot_slv := "111";
when PRIVILIGED_SECURE_DATA =>
v_prot_slv := "100";
when PRIVILIGED_SECURE_INSTRUCTION =>
v_prot_slv := "101";
end case;
return v_prot_slv;
end function;
function to_slv(
axilite_response_status : t_axilite_response_status;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return std_logic_vector is
variable v_axilite_response_status_slv : std_logic_vector(1 downto 0);
begin
check_value(axilite_response_status /= EXOKAY, TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case axilite_response_status is
when OKAY =>
v_axilite_response_status_slv := "00";
when SLVERR =>
v_axilite_response_status_slv := "10";
when DECERR =>
v_axilite_response_status_slv := "11";
when EXOKAY =>
v_axilite_response_status_slv := "01";
end case;
return v_axilite_response_status_slv;
end function;
function to_axilite_response_status(
resp : std_logic_vector(1 downto 0);
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return t_axilite_response_status is
begin
check_value(resp /= "01", TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case resp is
when "00" =>
return OKAY;
when "10" =>
return SLVERR;
when "11" =>
return DECERR;
when others =>
return EXOKAY;
end case;
end function;
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if is
variable init_if : t_axilite_if( write_address_channel( awaddr( addr_width -1 downto 0)),
write_data_channel( wdata( data_width -1 downto 0),
wstrb(( data_width/8) -1 downto 0)),
read_address_channel( araddr( addr_width -1 downto 0)),
read_data_channel( rdata( data_width -1 downto 0)));
begin
-- Write Address Channel
init_if.write_address_channel.awaddr := (init_if.write_address_channel.awaddr'range => '0');
init_if.write_address_channel.awvalid := '0';
init_if.write_address_channel.awprot := to_slv(UNPRIVILIGED_UNSECURE_DATA); --"010"
init_if.write_address_channel.awready := 'Z';
-- Write Data Channel
init_if.write_data_channel.wdata := (init_if.write_data_channel.wdata'range => '0');
init_if.write_data_channel.wstrb := (init_if.write_data_channel.wstrb'range => '0');
init_if.write_data_channel.wvalid := '0';
init_if.write_data_channel.wready := 'Z';
-- Write Response Channel
init_if.write_response_channel.bready := '0';
init_if.write_response_channel.bresp := (init_if.write_response_channel.bresp'range => 'Z');
init_if.write_response_channel.bvalid := 'Z';
-- Read Address Channel
init_if.read_address_channel.araddr := (init_if.read_address_channel.araddr'range => '0');
init_if.read_address_channel.arvalid := '0';
init_if.read_address_channel.arprot := to_slv(UNPRIVILIGED_UNSECURE_DATA); --"010"
init_if.read_address_channel.arready := 'Z';
-- Read Data Channel
init_if.read_data_channel.rready := '0';
init_if.read_data_channel.rdata := (init_if.read_data_channel.rdata'range => 'Z');
init_if.read_data_channel.rresp := (init_if.read_data_channel.rresp'range => 'Z');
init_if.read_data_channel.rvalid := 'Z';
return init_if;
end function;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant C_BYTE_ENABLE : std_logic_vector(axilite_if.write_data_channel.wstrb'length-1 downto 0) := (others => '1');
begin
axilite_write(addr_value, data_value, C_BYTE_ENABLE, msg, clk, axilite_if, scope, msg_id_panel, config);
end procedure axilite_write;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axilite_write";
constant proc_call : string := "axilite_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
constant max_pipe_stages : integer := maximum(config.num_w_pipe_stages, config.num_aw_pipe_stages);
variable v_await_awready : boolean := true;
variable v_await_wready : boolean := true;
variable v_await_bvalid : boolean := true;
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.write_address_channel.awaddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.write_address_channel.awaddr, ALLOW_NARROWER, "addr", "axilite_if.write_address_channel.awaddr", msg);
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_value, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
-- Helper variables
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
begin
check_value(v_normalized_data'length = 32 or v_normalized_data'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!", scope, ID_NEVER, msg_id_panel);
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
for cycle in 0 to config.max_wait_cycles loop
-- check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_call & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
if cycle = config.num_w_pipe_stages then
axilite_if.write_data_channel.wdata <= v_normalized_data;
axilite_if.write_data_channel.wstrb <= byte_enable;
axilite_if.write_data_channel.wvalid <= '1';
end if;
if cycle = config.num_aw_pipe_stages then
axilite_if.write_address_channel.awaddr <= v_normalized_addr;
axilite_if.write_address_channel.awvalid <= '1';
axilite_if.write_address_channel.awprot <= to_slv(config.protection_setting);
end if;
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "clk period not within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
if axilite_if.write_data_channel.wready = '1' and cycle >= config.num_w_pipe_stages then
axilite_if.write_data_channel.wvalid <= '0' after config.clock_period/4;
v_await_wready := false;
end if;
if axilite_if.write_address_channel.awready = '1' and cycle >= config.num_aw_pipe_stages then
axilite_if.write_address_channel.awvalid <= '0' after config.clock_period/4;
v_await_awready := false;
end if;
if not v_await_awready and not v_await_wready then
exit;
end if;
end loop;
check_value(not v_await_wready, config.max_wait_cycles_severity, ": Timeout waiting for WREADY", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(not v_await_awready, config.max_wait_cycles_severity, ": Timeout waiting for AWREADY", scope, ID_NEVER, msg_id_panel, proc_call);
-- check if enough room for setup_time before next clk rising edge
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_call & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
axilite_if.write_response_channel.bready <= '1';
for cycle in 0 to config.max_wait_cycles loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "clk period not within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
if axilite_if.write_response_channel.bvalid = '1' then
check_value(axilite_if.write_response_channel.bresp, to_slv(config.expected_response), config.expected_response_severity, ": BRESP detected", scope, BIN, AS_IS, ID_NEVER, msg_id_panel, proc_call);
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
axilite_if.write_response_channel.bready <= '0';
v_await_bvalid := false;
end if;
if not v_await_bvalid then
exit;
end if;
end loop;
check_value(not v_await_bvalid, config.max_wait_cycles_severity, ": Timeout waiting for BVALID", scope, ID_NEVER, msg_id_panel, proc_call);
axilite_if.write_address_channel.awaddr(axilite_if.write_address_channel.awaddr'length-1 downto 0) <= (others => '0');
axilite_if.write_address_channel.awvalid <= '0';
axilite_if.write_data_channel.wdata(axilite_if.write_data_channel.wdata'length-1 downto 0) <= (others => '0');
axilite_if.write_data_channel.wstrb(axilite_if.write_data_channel.wstrb'length-1 downto 0) <= (others => '1');
axilite_if.write_data_channel.wvalid <= '0';
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure axilite_write;
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axilite_check
) is
constant local_proc_name : string := "axilite_read"; -- Local proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")"; -- Local proc_call; used if called from sequncer or VVC
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.read_address_channel.araddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.read_address_channel.araddr, ALLOW_NARROWER, "addr", "axilite_if.read_address_channel.araddr", msg);
-- Helper variables
variable v_proc_call : line;
variable v_await_arready : boolean := true;
variable v_await_rvalid : boolean := true;
variable v_data_value : std_logic_vector(axilite_if.read_data_channel.rdata'length-1 downto 0);
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_call);
-- If called from sequencer/VVC, show 'axilite_read...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure like axilite_expect, log 'axilite_check(..) while executing axilite_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
check_value(v_data_value'length = 32 or v_data_value'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
axilite_if.read_address_channel.araddr <= v_normalized_addr;
axilite_if.read_address_channel.arvalid <= '1';
for cycle in 0 to config.max_wait_cycles loop
if axilite_if.read_address_channel.arready = '1' and cycle > 0 then
axilite_if.read_address_channel.arvalid <= '0';
axilite_if.read_address_channel.araddr(axilite_if.read_address_channel.araddr'length-1 downto 0) <= (others => '0');
axilite_if.read_address_channel.arprot <= to_slv(config.protection_setting);
v_await_arready := false;
end if;
if v_await_arready then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "clk period not within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
end loop;
check_value(not v_await_arready, config.max_wait_cycles_severity, ": Timeout waiting for ARREADY", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
axilite_if.read_data_channel.rready <= '1';
for cycle in 0 to config.max_wait_cycles loop
if axilite_if.read_data_channel.rvalid = '1' and cycle > 0 then
v_await_rvalid := false;
check_value(axilite_if.read_data_channel.rresp, to_slv(config.expected_response), config.expected_response_severity, ": RRESP detected", scope, BIN, AS_IS, ID_NEVER, msg_id_panel, v_proc_call.all);
v_data_value := axilite_if.read_data_channel.rdata;
-- Wait hold time specified in config record
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
axilite_if.read_data_channel.rready <= '0';
end if;
if v_await_rvalid then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "clk period not within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
end loop;
check_value(not v_await_rvalid, config.max_wait_cycles_severity, ": Timeout waiting for RVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
data_value := v_data_value;
if ext_proc_call = "" then -- proc_name = "axilite_read" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
end if;
end procedure axilite_read;
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axilite_check";
constant proc_call : string := "axilite_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
variable v_data_value : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
-- Normalize to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_exp, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
begin
axilite_read(addr_value, v_data_value, msg, clk, axilite_if, scope, msg_id_panel, config, proc_call);
v_check_ok := true;
for i in 0 to v_normalized_data'length-1 loop
if v_normalized_data(i) = '-' or v_normalized_data(i) = v_data_value(i) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
alert(alert_level, proc_call & "=> Failed. slv Was " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axilite_check;
end package body axilite_bfm_pkg;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY design_1_rst_ps7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_ps7_0_50M_0;
ARCHITECTURE design_1_rst_ps7_0_50M_0_arch OF design_1_rst_ps7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2018.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_50M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_50M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_ps7_0_50M_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
generic(
BITS : positive;
ZEROS : unsigned(BITS - 1 downto 0) := (others => '0'));
port(
min : in u_unsigned(BITS - 1 downto 0) := ZEROS);
end entity;
architecture rtl of test is
begin
process
variable sum : unsigned(BITS - 2 downto 0);
variable carry : std_ulogic;
begin
(carry, sum) := min;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Title : IF_ID_Register
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\IF_ID_Register.vhd
-- Generated : Wed Dec 7 14:30:02 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {IF_ID_Register} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity IF_ID_Register is
port (
instruction_in : in std_logic_vector(15 downto 0);
clk : in std_logic;
instruction_out : out std_logic_vector(15 downto 0)
);
end IF_ID_Register;
architecture behavioral of IF_ID_Register is
begin
process(clk)
variable instruction_in_reg : std_logic_vector(15 downto 0) := "0000000000000000";
variable instruction_out_reg : std_logic_vector(15 downto 0) := "0000000000000000";
begin
if rising_edge(clk) then
instruction_out_reg := instruction_in_reg;
instruction_in_reg := instruction_in;
end if;
instruction_out <= instruction_out_reg;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is
type rom_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= ("00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000",
"10010000000100000000000000010000",
"10110010000100000010000000000110","01111111111111111111111111110100",
"10100010000100000000000000010010","00010000101111111111111111111000",--"10000001110000000010000000000100",
"10100100000001000110000000000001","10100000000100000000000000010010",
"10100100000001000000000000011000",
"00000001000000000000000000000000","10000001110000111110000000000010",
"00000001000000000000000000000000","00101100100000000000000000000100",
"10000000101001000100000000011001","10100010000100000010000000000000",
"10100000000100000010000000000000","10110000000100000010000000001100",
"01000000000000000000000000001110");
--"00000000000000000000000000000000","10011110000001000100000000010000",
--"10101110100001010100000000010110","10101101001011010011000000010100",--"10101100100001010100000000010101",
--"10101011001011010011000000010011","10101000000100000010111111111111",
--"10100110100101000000000000010001","10100110100010000010011110101000",
--"10010000001001000100000000010010","10100100000001000010000000010000",
--"10100010000100000010000000010001","10100000000100000010000000001111");
begin
process(rst,Address,ROM)
begin
if rst='1' then
Instruction<=(others=>'0');
else
Instruction<=ROM(conv_integer(Address));
end if;
end process;
end syn; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_ba --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_TB IS --entity of the testbench is always empty
END ALU_TB;
ARCHITECTURE testbench OF ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
component ALU is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : in STD_LOGIC_VECTOR (1 downto 0); --1 downto 0
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--Inputs from the testbench
signal a_tb : std_logic_vector(3 downto 0) := (others => '0');
signal b_tb : std_logic_vector(3 downto 0) := (others => '0');
signal op_tb : std_logic_vector(1 downto 0) := (others => '0');
--Output from the testbench
signal o_tb : std_logic_vector(3 downto 0);
begin
--component port map
uut: ALU port map (
a => a_tb,
b => b_tb,
op => op_tb,
o => o_tb
);
process
begin
--Testing each function with 8 different combinations of inputs.
report "Test case 1";
a_tb <= "0000";
b_tb <= "0000";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 2";
a_tb <= "1111";
b_tb <= "0000";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 3";
a_tb <= "0000";
b_tb <= "1111";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 4";
a_tb <= "1010";
b_tb <= "0101";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 5";
a_tb <= "1100";
b_tb <= "0011";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 6";
a_tb <= "0011";
b_tb <= "1100";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 7";
a_tb <= "0001";
b_tb <= "0001";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
report "Test case 8";
a_tb <= "1000";
b_tb <= "1000";
op_tb <= "00";
wait for 10 ns;
op_tb <= "01";
wait for 10ns;
op_tb <= "10";
wait for 10ns;
op_tb <= "11";
wait for 10ns;
end process;
end testbench; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrpkg
-- File: ddrpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ddrpkg is
type ddrctrl_in_type is record
-- Data signals
data : std_logic_vector (127 downto 0);-- data in
cb : std_logic_vector(63 downto 0); -- checkbits in
-- Bus/timing control signals
datavalid : std_logic; -- Data-valid signal (DDR2,LPDDR2,LPDDR3)
writereq : std_logic; -- Write-data request (LPDDR2,LPDDR3)
-- Calibration and configuration
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in (DDR2)
end record;
constant ddrctrl_in_none : ddrctrl_in_type :=
((others => '0'), (others => '0'), '0', '0', (others => '0'));
type ddrctrl_out_type is record
-- Control signals to memory
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en (DDR1,DDR2,LPDDR1)
rasn : std_ulogic; -- row addr stb (DDR1,DDR2,LPDDR1)
casn : std_ulogic; -- col addr stb (DDR1,DDR2,LPDDR1)
address : std_logic_vector(14 downto 0); -- address out (DDR1,DDR2,LPDDR1)
ba : std_logic_vector (2 downto 0); -- bank address (DDR1,DDR2,LPDDR1)
odt : std_logic_vector(1 downto 0); -- On Die Termination (DDR2,LPDDR3)
ca : std_logic_vector(19 downto 0); -- Ctrl/Addr bus (LPDDR2,LPDDR3)
-- Data signals
data : std_logic_vector(127 downto 0); -- data out
dqm : std_logic_vector(15 downto 0); -- data i/o mask
cb : std_logic_vector(63 downto 0); -- checkbits
cbdqm : std_logic_vector(7 downto 0); -- checkbits data mask
-- Bus/timing control signals
bdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
qdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
nbdrive : std_ulogic; -- bdrive 1 cycle early (DDR2)
sdck : std_logic_vector(2 downto 0); -- Clock enable (DDR1,LPDDR1,LPDDR2,LPDDR3)
moben : std_logic; -- Mobile DDR mode (DDR1/LPDDR1)
oct : std_logic; -- On Chip Termination (DDR2)
dqs_gate : std_logic; -- DQS gate control (DDR2)
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy
-- delays) (DDR2,LPDDR2,LPDDR3)
wrpend : std_logic_vector(7 downto 0); -- Write pending (LPDDR2,LPDDR3)
boot : std_ulogic; -- Boot clock selection (LPDDR2,LPDDR3)
-- Calibration and configuration
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration (DDR2)
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay (DDR2)
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase (DDR2)
cal_rst : std_logic; -- calibration reset (DDR2)
conf : std_logic_vector(63 downto 0); -- Conf. interface (DDR1,LPDDR1)
cbcal_en : std_logic_vector(3 downto 0); -- CB enable delay calib (DDR2)
cbcal_inc : std_logic_vector(3 downto 0); -- CB inc/dec delay (DDR2)
regwdata : std_logic_vector(63 downto 0); -- Reg Write data (DDR2)
regwrite : std_logic_vector(1 downto 0); -- Reg write strobe (DDR2)
-- Status outputs to front-end
ce : std_ulogic; -- Error corrected
end record;
constant ddrctrl_out_none : ddrctrl_out_type :=
((others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0' );
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
-- DDR2 controller without PHY
component ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end component;
-- DDR2 controller with PHY
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer := 0;
dqsse : integer range 0 to 1 := 0;
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits+ftbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, including pads
component ddr2phy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
extraio : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0);-- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, not including pads
component ddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1: integer := 0;
cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR2 PHY with separate checkbit and data buses, including pads
component ddr2phy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
cben : integer := 0;
chkbits : integer := 8;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
-- DDR/LPDDR controller, without PHY
component ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end component;
-- DDR/LPDDR controller with PHY
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer range 0 to 1 := 0;
ddr400 : integer := 1;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
-- DDR/LPDDR PHY, including pads
component ddrphy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
scantest : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0);-- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, including pads
component ddrphy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
chkbits : integer := 0;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, without pads
component ddrphy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
component lpddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-----------------------------------------------------------------------------
-- Other components using DDRxSPA sub-components
-----------------------------------------------------------------------------
type ddravl_slv_in_type is record
burstbegin : std_ulogic;
addr : std_logic_vector(31 downto 0);
wdata : std_logic_vector(256 downto 0);
be : std_logic_vector(32 downto 0);
read_req : std_ulogic;
write_req : std_ulogic;
size : std_logic_vector(3 downto 0);
end record;
type ddravl_slv_out_type is record
ready : std_ulogic;
rdata_valid : std_ulogic;
rdata : std_logic_vector(256 downto 0);
end record;
constant ddravl_slv_in_none: ddravl_slv_in_type :=
('0',(others => '0'),(others => '0'),(others => '0'),'0','0',(others => '0'));
component ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end component;
end package;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_write.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Handles delaying various write control signals appropriately depending
-- on CAS latency, additive latency, etc. Also splits the data and mask in
-- rise and fall buses.
--Reference:
--Revision History:
-- Revision 1.22 Karthip merged DDR2 changes 11/11/2008
--*****************************************************************************
--******************************************************************************
--**$Id: phy_write.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_write.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_write is
generic (
TCQ : integer := 100;
WRLVL : string := "ON";
DRAM_TYPE : string := "DDR3";
DQ_WIDTH : integer := 64;
DQS_WIDTH : integer := 8;
nCWL : integer := 5;
REG_CTRL : string := "OFF";
RANK_WIDTH : integer := 1;
CLKPERF_DLY_USED : string := "OFF"
);
port (
clk : in std_logic;
rst : in std_logic;
-- Write-leveling control
mc_data_sel : in std_logic;
wrlvl_active : in std_logic;
wrlvl_done : in std_logic;
inv_dqs : in std_logic_vector(DQS_WIDTH-1 downto 0);
wr_calib_dly : in std_logic_vector(2*DQS_WIDTH-1 downto 0);
-- MC DFI Control/Address
dfi_wrdata : in std_logic_vector(4*DQ_WIDTH-1 downto 0);
dfi_wrdata_mask : in std_logic_vector((4*DQ_WIDTH/8)-1 downto 0);
dfi_wrdata_en : in std_logic;
-- MC sideband signal
mc_ioconfig_en : in std_logic; -- Possible future use
mc_ioconfig : in std_logic_vector(RANK_WIDTH downto 0); -- Possible future use
-- PHY DFI Control/Address
phy_wrdata_en : in std_logic;
phy_wrdata : in std_logic_vector(4*DQ_WIDTH-1 downto 0);
-- sideband signals
phy_ioconfig_en : in std_logic; -- Possible future use
phy_ioconfig : in std_logic_vector(0 downto 0); -- Possible future use
-- Write-path control
out_oserdes_wc : in std_logic;
dm_ce : out std_logic_vector(DQS_WIDTH-1 downto 0);
dq_oe_n : out std_logic_vector(4*DQS_WIDTH-1 downto 0);
dqs_oe_n : out std_logic_vector(4*DQS_WIDTH-1 downto 0);
dqs_rst : out std_logic_vector(4*DQS_WIDTH-1 downto 0);
dq_wc : out std_logic;
dqs_wc : out std_logic;
mask_data_rise0 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
mask_data_fall0 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
mask_data_rise1 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
mask_data_fall1 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
wl_sm_start : out std_logic;
wr_lvl_start : out std_logic;
wr_data_rise0 : out std_logic_vector(DQ_WIDTH-1 downto 0);
wr_data_fall0 : out std_logic_vector(DQ_WIDTH-1 downto 0);
wr_data_rise1 : out std_logic_vector(DQ_WIDTH-1 downto 0);
wr_data_fall1 : out std_logic_vector(DQ_WIDTH-1 downto 0)
);
end phy_write;
architecture trans of phy_write is
constant DQ_PER_DQS : integer := DQ_WIDTH/DQS_WIDTH;
constant RST_DLY_NUM : integer := 8;
signal rst_delayed : std_logic_vector(RST_DLY_NUM-1 downto 0);
signal dm_ce_r : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dq_wc_r : std_logic;
signal dqs_wc_r : std_logic;
signal dqs_wc_asrt : std_logic;
signal dqs_wc_deasrt : std_logic;
signal dm_ce_0 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dqs_asrt_cnt : std_logic_vector(1 downto 0);
signal mux_ioconfig_r : std_logic_vector(0 downto 0);
signal mux_wrdata_en : std_logic;
signal mux_ioconfig_en : std_logic;
signal mux_ioconfig : std_logic_vector(0 downto 0); -- bus to be expanded later
signal mc_wrdata : std_logic_vector(4*DQ_WIDTH-1 downto 0);
signal mc_wrdata_mask : std_logic_vector((4*DQ_WIDTH/8)-1 downto 0);
signal phy_wrdata_r : std_logic_vector(4*DQ_WIDTH-1 downto 0);
signal dfi_wrdata_r : std_logic_vector(4*DQ_WIDTH-1 downto 0);
signal dfi_wrdata_mask_r : std_logic_vector((4*DQ_WIDTH/8)-1 downto 0);
signal ocb_d1 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_d2 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_d3 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_d4 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_dq1 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_dq2 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_dq3 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ocb_dq4 : std_logic_vector(DQS_WIDTH-1 downto 0);
signal wrdata_en_r1 : std_logic;
signal wrdata_en_r2 : std_logic;
signal wrdata_en_r3 : std_logic;
signal wrdata_en_r4 : std_logic;
signal wrdata_en_r5 : std_logic;
signal wrdata_en_r6 : std_logic;
signal wrdata_en_r7 : std_logic;
signal wrlvl_active_r1 : std_logic;
signal wrlvl_active_r2 : std_logic;
signal wrlvl_done_r1 : std_logic;
signal wrlvl_done_r2 : std_logic;
signal wrlvl_done_r3 : std_logic;
signal wr_level_dqs_asrt_r : std_logic;
signal wr_level_dqs_stg_r : std_logic_vector(19 downto 0);
signal mux_ioconfig_latch : std_logic;
signal mux_ioconfig_last_r : std_logic;
signal dfi_wrdata_en_r : std_logic;
signal phy_wrdata_en_r : std_logic;
begin
--***************************************************************************
-- NOTE: As of 08/13/08, many signals in this module are not used. This is
-- because of a last-minute change to the WC timing - it was based on
-- IOCONFIG_STROBE, however IOCONFIG_STROBE will only occur when there is
-- a change in either the bus direction, or rank accessed. It will not
-- occur for succeeding writes to the same rank. Therefore, it cannot be
-- used to drive WC (which must be pulsed once to "restart" the circular
-- buffer once the bus has gone tri-state). For now, revert to using
-- WRDATA_EN to determining when WC is pulsed.
--***************************************************************************
process (clk, rst)
begin
if (rst = '1') then
rst_delayed <= (others => '1') after TCQ*1 ps;
elsif (clk'event and clk = '1') then
-- logical left shift by one (pads with 0)
rst_delayed <= std_logic_vector(unsigned(rst_delayed) sll 1) after TCQ*1 ps;
end if;
end process;
--***************************************************************************
-- MUX control/data inputs from either external DFI master or PHY init
--***************************************************************************
gen_wrdata_en_rdimm: if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
process(clk)
begin
if (clk'event and clk = '1') then
phy_wrdata_r <= phy_wrdata after TCQ*1 ps;
phy_wrdata_en_r <= phy_wrdata_en after TCQ*1 ps;
dfi_wrdata_en_r <= dfi_wrdata_en after TCQ*1 ps;
dfi_wrdata_r <= dfi_wrdata after TCQ*1 ps;
dfi_wrdata_mask_r <= dfi_wrdata_mask after TCQ*1 ps;
end if;
end process;
process (mc_data_sel,phy_wrdata_en_r,phy_wrdata_en,dfi_wrdata_en_r,dfi_wrdata_en)
begin
if ((mc_data_sel = '0') and (nCWL = 9)) then
mux_wrdata_en <= phy_wrdata_en_r;
else
if (mc_data_sel = '0') then
mux_wrdata_en <= phy_wrdata_en;
else
if ((nCWL = 7) or (nCWL = 9)) then
mux_wrdata_en <= dfi_wrdata_en_r;
else
mux_wrdata_en <= dfi_wrdata_en;
end if;
end if;
end if;
end process;
end generate;
gen_wrdata_en_udimm: if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
mux_wrdata_en <= dfi_wrdata_en when (mc_data_sel = '1') else
phy_wrdata_en;
end generate;
mux_ioconfig_en <= mc_ioconfig_en when (mc_data_sel = '1') else
phy_ioconfig_en;
mux_ioconfig(0) <= mc_ioconfig(RANK_WIDTH) when (mc_data_sel = '1') else
phy_ioconfig(0);
--***************************************************************************
-- OCB WC pulse generation on a per byte basis
--***************************************************************************
-- Store value of MUX_IOCONFIG when enable(latch) signal asserted
process (clk)
begin
if (clk'event and clk = '1') then
if (mux_ioconfig_en = '1') then
mux_ioconfig_last_r <= mux_ioconfig(0) after TCQ*1 ps;
end if;
end if;
end process;
-- dfi_wrdata_en - data enable sent by MC
-- ignoring dfi_wrdata_en1: data sent on both channels 0 and 1 simultaneously
-- tphy_wrlat set to 0 'clk' cycle for CWL = 5,6,7,8
-- Valid dfi_wrdata* sent 1 'clk' cycle after dfi_wrdata_en* is asserted
-- WC for OCB (Output Circular Buffer) assertion for 1 clk cycle
process (mux_ioconfig_en, mux_ioconfig_last_r, mux_ioconfig(0))
begin
if (mux_ioconfig_en = '1') then
mux_ioconfig_latch <= mux_ioconfig(0);
else
mux_ioconfig_latch <= mux_ioconfig_last_r;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
wl_sm_start <= '0' after TCQ*1 ps;
else
wl_sm_start <= wr_level_dqs_asrt_r after TCQ*1 ps;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst = '1') or ((mux_ioconfig_en = '1') and (mux_ioconfig(0) = '0'))) then
mux_ioconfig_r(0) <= '0' after TCQ*1 ps;
else
mux_ioconfig_r(0) <= mux_ioconfig_latch after TCQ*1 ps;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
wrdata_en_r1 <= mux_wrdata_en after TCQ*1 ps;
wrdata_en_r2 <= wrdata_en_r1 after TCQ*1 ps;
wrdata_en_r3 <= wrdata_en_r2 after TCQ*1 ps;
wrdata_en_r4 <= wrdata_en_r3 after TCQ*1 ps;
wrdata_en_r5 <= wrdata_en_r4 after TCQ*1 ps;
wrdata_en_r6 <= wrdata_en_r5 after TCQ*1 ps;
wrdata_en_r7 <= wrdata_en_r6 after TCQ*1 ps;
end if;
end process;
-- One WC signal for all data bits
-- Combinatorial for CWL=5 and registered for CWL>5
gen_wc_ddr3: if ((DRAM_TYPE(1 to 4) = "DDR3") and (CLKPERF_DLY_USED(1 to 2) = "ON")) generate
begin
gen_wc_ncwl5: if (nCWL = 5) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst = '1') or ((mux_ioconfig_en = '1') and (mux_ioconfig(0) = '0')) or (wrlvl_active = '1')) then
dq_wc_r <= '0' after TCQ*1 ps;
elsif (mux_ioconfig_latch = '1') then
dq_wc_r <= not(dq_wc_r) after TCQ*1 ps;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst = '1') or ((mux_ioconfig_en = '1') and (mux_ioconfig(0) = '0') and (wrlvl_active_r1 = '0')) or
(dqs_wc_deasrt = '1')) then
dqs_wc_r <= '0' after TCQ*1 ps;
elsif (dqs_wc_asrt = '1') then
dqs_wc_r <= '1' after TCQ*1 ps;
elsif ((mux_ioconfig_latch = '1') and (wrlvl_active_r1 = '0')) then
dqs_wc_r <= not(dqs_wc_r) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
gen_wc_ncwl7up: if ((nCWL = 7) or (nCWL = 6) or (nCWL = 8) or (nCWL = 9)) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst = '1') or ((mux_ioconfig_en = '1') and (mux_ioconfig(0) = '0')) or (wrlvl_active = '1')) then
dq_wc_r <= '0' after TCQ*1 ps;
elsif (mux_ioconfig_r(0) = '1') then
dq_wc_r <= not(dq_wc_r) after TCQ*1 ps;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst = '1') or ((mux_ioconfig_en = '1') and (mux_ioconfig(0) = '0') and (wrlvl_active_r1 = '0')) or (dqs_wc_deasrt = '1')) then
dqs_wc_r <= '0' after TCQ*1 ps;
elsif (dqs_wc_asrt = '1') then
dqs_wc_r <= '1' after TCQ*1 ps;
elsif ((mux_ioconfig_r(0) = '1') and (wrlvl_active_r1 = '0')) then
dqs_wc_r <= not(dqs_wc_r) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
gen_wc_ddr2: if ((DRAM_TYPE(1 to 4) /= "DDR3") or (CLKPERF_DLY_USED(1 to 2) /= "ON")) generate
begin
process (out_oserdes_wc)
begin
dq_wc_r <= out_oserdes_wc;
dqs_wc_r <= out_oserdes_wc;
end process;
end generate;
-- DQ_WC is pulsed with rising edge of MUX_WRDATA_EN
dq_wc <= dq_wc_r;
-- DQS_WC has the same timing, except there is an additional term for
-- write leveling
dqs_wc <= dqs_wc_r;
--***************************************************************************
-- DQS/DQ Output Enable Bitslip
-- Timing for output enable:
-- - Enable for DQS: For burst of 8 (over 4 clock cycles), OE is asserted
-- one cycle before first valid data (i.e. at same time as DQS write
-- preamble), and deasserted immediately after the last postamble
--***************************************************************************
gen_ddr3_dqs_ocb: if (DRAM_TYPE(1 to 4) = "DDR3") generate
begin
gen_ncwl5_odd: if ((nCWL = 5) and (CLKPERF_DLY_USED = "ON")) generate
begin
-- write command sent by MC on channel 1
-- D3,D4 inputs of the OCB used to send write command to DDR3
ncwl_odd_loop: for dqs_i in 0 to (DQS_WIDTH-1) generate
signal xhdl1: std_logic_vector(2 downto 0);
begin
xhdl1 <= wr_calib_dly(2*dqs_i + 1 downto 2*dqs_i) & inv_dqs(dqs_i);
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst_delayed(RST_DLY_NUM-1) = '1') or (wrlvl_active_r1 = '1')) then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
ocb_dq1(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq2(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq3(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq4(dqs_i) <= '1' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
dm_ce_0(dqs_i) <= (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case ( xhdl1 ) is
-- 0 clk_mem delay required as per write calibration
when "000" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
-- 1 clk_mem delay required as per write calibration
when "010" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
-- 2 clk_mem delay required as per write calibration
when "100" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 3 clk_mem delay required as per write calibration
when "110" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- 0 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "001" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
-- 1 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "011" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
-- 2 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "101" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 3 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "111" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- defaults to 0 clk_mem delay and no DQS inversion
when others =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
gen_ncwl5_noWC: if (((nCWL = 5) or (nCWL = 7) or (nCWL = 9))
and (CLKPERF_DLY_USED = "OFF")) generate
begin
-- Extending tri-state signal at the end when CLKPERF_DELAYED is not used
-- In this use case the data path goes through the ODELAY whereas the
-- tri-state path does not. Hence tri-state must be extended to
-- compensate for the ODELAY insertion delay and number of taps.
-- Tri-state signal is asserted for eight and a half clk_mem cycles.
ncwl_odd_loop: for dqs_i in 0 to (DQS_WIDTH-1) generate
signal xhdl2: std_logic_vector(2 downto 0);
begin
xhdl2 <= wr_calib_dly(2*dqs_i + 1 downto 2*dqs_i) & inv_dqs(dqs_i);
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst_delayed(RST_DLY_NUM-1) = '1') or (wrlvl_active_r1 = '1')) then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
ocb_dq1(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq2(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq3(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq4(dqs_i) <= '1' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
dm_ce_0(dqs_i) <= (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl2) is
-- 0 clk_mem delay required as per write calibration
when "000" =>
ocb_d1(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
-- 1 clk_mem delay required as per write calibration
when "010" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 2 clk_mem delay required as per write calibration
when "100" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 3 clk_mem delay required as per write calibration
when "110" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- 0 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "001" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or
wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
-- 1 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "011" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 2 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "101" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 3 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "111" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or
wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or
wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or
wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- defaults to 0 clk_mem delay and no DQS inversion
when others =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or
wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
gen_ncwl7_odd: if (((nCWL = 7) or (nCWL = 9)) and (CLKPERF_DLY_USED = "ON")) generate
begin
-- write command sent by MC on channel 1
-- D3,D4 inputs of the OCB used to send write command to DDR3
ncwl_odd_loop: for dqs_i in 0 to (DQS_WIDTH-1) generate
signal xhdl3: std_logic_vector(2 downto 0);
begin
xhdl3 <= wr_calib_dly(2*dqs_i + 1 downto 2*dqs_i) & inv_dqs(dqs_i);
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst_delayed(RST_DLY_NUM-1) = '1') or (wrlvl_active_r1 = '1')) then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
ocb_dq1(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq2(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq3(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq4(dqs_i) <= '1' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
dm_ce_0(dqs_i) <= (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl3) is
-- 0 clk_mem delay required as per write calibration
when "000" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 1 clk_mem delay required as per write calibration
when "010" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 2 clk_mem delay required as per write calibration
when "100" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- 3 clk_mem delay required as per write calibration
when "110" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- 0 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "001" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 1 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "011" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- 2 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "101" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- 3 clk_mem delay required as per write calibration
-- DQS inverted during write leveling
when "111" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- defaults to 0 clk_mem delay and no DQS inversion
when others =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
-- gen_ncwl7_noWC: if (((nCWL = 7) or (nCWL = 9)) and (CLKPERF_DLY_USED = "OFF")) generate
-- begin
-- -- Extending tri-state signal at the end when CLKPERF_DELAYED is not used
-- -- In this use case the data path goes through the ODELAY whereas the
-- -- tri-state path does not. Hence tri-state must be extended to
-- -- compensate for the ODELAY insertion delay and number of taps.
-- -- Tri-state signal is asserted for eight and a half clk_mem cycles.
-- ncwl_odd_loop: for dqs_i in 0 to (DQS_WIDTH-1) generate
-- begin
-- process (clk)
-- variable xhdl4: std_logic_vector(2 downto 0);
-- begin
--
-- if (clk'event and clk = '1') then
-- xhdl4 := wr_calib_dly(2*dqs_i + 1 downto 2*dqs_i) & inv_dqs(dqs_i);
-- if ((rst_delayed(RST_DLY_NUM-1) = '1') or (wrlvl_active_r1 = '1')) then
-- ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
-- ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
-- ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
-- ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= '1' after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= '1' after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= '1' after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= '1' after TCQ*1 ps;
-- dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
-- else
-- dm_ce_0(dqs_i) <= (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
--
-- -- Shift bitslip logic by 1 or 2 clk_mem cycles
-- -- Write calibration currently supports only upto 2 clk_mem cycles
-- case (xhdl4) is
-- -- 0 clk_mem delay required as per write calibration
-- when "000" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- -- 1 clk_mem delay required as per write calibration
-- when "010" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- -- 2 clk_mem delay required as per write calibration
-- when "100" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- -- 3 clk_mem delay required as per write calibration
-- when "110" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6 or wrdata_en_r7) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6 or wrdata_en_r7) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- -- 0 clk_mem delay required as per write calibration
-- -- DQS inverted during write leveling
-- when "001" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- -- 1 clk_mem delay required as per write calibration
-- -- DQS inverted during write leveling
-- when "011" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- -- 2 clk_mem delay required as per write calibration
-- -- DQS inverted during write leveling
-- when "101" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- -- 3 clk_mem delay required as per write calibration
-- -- DQS inverted during write leveling
-- when "111" =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
-- -- defaults to 0 clk_mem delay and no DQS inversion
-- when others =>
-- ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- end case;
-- end if;
-- end if;
-- end process;
-- end generate;
-- end generate;
gen_ncwl_even: if (((nCWL = 6) or (nCWL = 8)) and (CLKPERF_DLY_USED = "ON")) generate
begin
ncwl_even_loop: for dqs_i in 0 to (DQS_WIDTH-1) generate
signal xhdl5: std_logic_vector(2 downto 0);
begin
xhdl5 <= wr_calib_dly(2*dqs_i + 1 downto 2*dqs_i) & inv_dqs(dqs_i);
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst_delayed(RST_DLY_NUM-1) = '1') or (wrlvl_active_r1 = '1')) then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
ocb_dq1(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq2(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq3(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq4(dqs_i) <= '1' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
dm_ce_0(dqs_i) <= (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
-- Shift bitslip logic by 1 or 2 clk_mem cycles
case (xhdl5) is
when "000" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
when "010" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
when "100" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when "110" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
-- DQS inverted during write leveling
when "001" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
when "011" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
when "101" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when "111" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when others =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
gen_ncwl_noWC: if (((nCWL = 6) or (nCWL = 8)) and (CLKPERF_DLY_USED = "OFF")) generate
-- Extending tri-state signal at the end when CLKPERF_DELAYED is not used
-- In this use case the data path goes through the ODELAY whereas the
-- tri-state path does not. Hence tri-state must be extended to
-- compensate for the ODELAY insertion delay and number of taps.
-- Tri-state signal is asserted for eight and a half clk_mem cycles.
ncwl_odd_loop: for dqs_i in 0 to (DQS_WIDTH-1) generate
signal xhdl6: std_logic_vector(2 downto 0);
begin
xhdl6 <= wr_calib_dly(2*dqs_i + 1 downto 2*dqs_i) & inv_dqs(dqs_i);
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst_delayed(RST_DLY_NUM-1) = '1') or (wrlvl_active_r1 = '1')) then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
ocb_dq1(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq2(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq3(dqs_i) <= '1' after TCQ*1 ps;
ocb_dq4(dqs_i) <= '1' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
dm_ce_0(dqs_i) <= (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
-- Shift bitslip logic by 1 or 2 clk_mem cycles
case (xhdl6) is
when "000" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when "010" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when "100" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
when "110" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
-- DQS inverted during write leveling
when "001" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (mux_wrdata_en or wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
when "011" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when "101" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
when "111" =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5 or wrdata_en_r6) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4 or wrdata_en_r5) after TCQ*1 ps;
when others =>
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
ocb_dq4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3 or wrdata_en_r4) after TCQ*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
end generate;
gen_ddr2_dqs_wc: if (DRAM_TYPE(1 to 4) /= "DDR3") generate
begin
gen_ncwl_even: if (nCWL = 2) generate
begin
ncwl_2: for dqs_i in 0 to (DQS_WIDTH-1) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_delayed(RST_DLY_NUM-1) = '1') then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
ocb_d1(dqs_i) <= NOT (wrdata_en_r1) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or mux_wrdata_en) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or mux_wrdata_en) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or mux_wrdata_en) after TCQ*1 ps;
dm_ce_0(dqs_i) <= (wrdata_en_r1 or wrdata_en_r2 or mux_wrdata_en) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
gen_ncwl_3: if (nCWL = 3) generate
begin
-- write command sent by MC on channel 1
-- D3,D4 inputs of the OCB used to send write command to DDR3
ncwl_3: for dqs_i in 0 to (DQS_WIDTH-1) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_delayed(RST_DLY_NUM-1) = '1') then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
ocb_d1(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or mux_wrdata_en) after TCQ*1 ps;
dm_ce_0(dqs_i) <= (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate; --block: ncwl_odd_loop
gen_ncwl_4: if (nCWL = 4) generate
begin
ncwl_4: for dqs_i in 0 to (DQS_WIDTH-1) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_delayed(RST_DLY_NUM-1) = '1') then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
ocb_d1(dqs_i) <= NOT (wrdata_en_r2) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
dm_ce_0(dqs_i) <= (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
gen_ncwl_5: if (nCWL = 5) generate
begin
-- write command sent by MC on channel 1
-- D3,D4 inputs of the OCB used to send write command to DDR3
ncwl_5: for dqs_i in 0 to (DQS_WIDTH-1) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_delayed(RST_DLY_NUM-1) = '1') then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r2) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r2) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r1 or wrdata_en_r2) after TCQ*1 ps;
dm_ce_0(dqs_i) <= (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
gen_ncwl_6: if (nCWL = 6) generate
begin
ncwl_6: for dqs_i in 0 to (DQS_WIDTH-1) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_delayed(RST_DLY_NUM-1) = '1') then
ocb_d1(dqs_i) <= '0' after TCQ*1 ps;
ocb_d2(dqs_i) <= '0' after TCQ*1 ps;
ocb_d3(dqs_i) <= '0' after TCQ*1 ps;
ocb_d4(dqs_i) <= '0' after TCQ*1 ps;
dm_ce_0(dqs_i) <= '0' after TCQ*1 ps;
else
ocb_d1(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r2) after TCQ*1 ps;
ocb_d2(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r2) after TCQ*1 ps;
ocb_d3(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r2) after TCQ*1 ps;
ocb_d4(dqs_i) <= NOT (wrdata_en_r3 or wrdata_en_r2) after TCQ*1 ps;
dm_ce_0(dqs_i) <= (wrdata_en_r1 or wrdata_en_r2 or wrdata_en_r3) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
end generate; --block: gen_ddr2_dqs_wc
process (clk)
begin
if (clk'event and clk = '1') then
wrlvl_active_r1 <= wrlvl_active after TCQ*1 ps;
wrlvl_active_r2 <= wrlvl_active_r1 after TCQ*1 ps;
wrlvl_done_r1 <= wrlvl_done after TCQ*1 ps;
wrlvl_done_r2 <= wrlvl_done_r1 after TCQ*1 ps;
wrlvl_done_r3 <= wrlvl_done_r2 after TCQ*1 ps;
end if;
end process;
-- Staging dm_ce based on CWL.
-- For lower CWL in DDR2 FF stages are removed to
-- send the DM out on correct time.
DDR3_DM: if (DRAM_TYPE(1 to 4) = "DDR3") generate
begin
process (dm_ce_0)
begin
dm_ce <= dm_ce_0;
end process;
end generate;
DDR2_DM: if (DRAM_TYPE(1 to 4) = "DDR2") generate
begin
nCWL_5up: if (nCWL >= 5) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
dm_ce_r <= dm_ce_0 after TCQ*1 ps;
dm_ce <= dm_ce_r after TCQ*1 ps;
end if;
end process;
end generate;
nCWL_3n4: if ((nCWL = 3) or (nCWL = 4)) generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
dm_ce <= dm_ce_0 after TCQ*1 ps;
end if;
end process;
end generate;
nCWL_2: if (nCWL = 2) generate
begin
process (dm_ce_0)
begin
dm_ce <= dm_ce_0;
end process;
end generate;
end generate;
-- NOTE: Restructure/retime later to improve timing
DDR3_TRISTATE: if (DRAM_TYPE = "DDR3") generate
gen_oe: for dqs_cnt_i in 0 to (DQS_WIDTH-1) generate
begin
dqs_oe_n((dqs_cnt_i*4) + 0) <= ocb_d1(dqs_cnt_i);
dqs_oe_n((dqs_cnt_i*4) + 1) <= ocb_d2(dqs_cnt_i);
dqs_oe_n((dqs_cnt_i*4) + 2) <= ocb_d3(dqs_cnt_i);
dqs_oe_n((dqs_cnt_i*4) + 3) <= ocb_d4(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 0) <= ocb_dq1(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 1) <= ocb_dq2(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 2) <= ocb_dq3(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 3) <= ocb_dq4(dqs_cnt_i);
end generate;
end generate;
DDR2_TRISTATE: if (DRAM_TYPE = "DDR2") generate
gen_oe: for dqs_cnt_i in 0 to (DQS_WIDTH-1) generate
begin
dqs_oe_n((dqs_cnt_i*4) + 0) <= ocb_d1(dqs_cnt_i);
dqs_oe_n((dqs_cnt_i*4) + 1) <= ocb_d2(dqs_cnt_i);
dqs_oe_n((dqs_cnt_i*4) + 2) <= ocb_d3(dqs_cnt_i);
dqs_oe_n((dqs_cnt_i*4) + 3) <= ocb_d4(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 0) <= ocb_d1(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 1) <= ocb_d2(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 2) <= ocb_d3(dqs_cnt_i);
dq_oe_n((dqs_cnt_i*4) + 3) <= ocb_d4(dqs_cnt_i);
end generate;
end generate;
-- signal used to assert DQS for write leveling.
-- the DQS will be asserted once every 16 clock cycles.
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
wr_level_dqs_asrt_r <= '0' after TCQ*1 ps;
dqs_wc_asrt <= '0' after TCQ*1 ps;
dqs_wc_deasrt <= '0' after TCQ*1 ps;
else
wr_level_dqs_asrt_r <= (wr_level_dqs_stg_r(19) and wrlvl_active_r1) after TCQ*1 ps;
dqs_wc_asrt <= (wr_level_dqs_stg_r(15) and wrlvl_active_r1) after TCQ*1 ps;
dqs_wc_deasrt <= (wr_level_dqs_stg_r(16) and wrlvl_active_r1) after TCQ*1 ps;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
dqs_asrt_cnt <= "00" after TCQ*1 ps;
elsif ((wr_level_dqs_asrt_r = '1') and (dqs_asrt_cnt /= "11")) then
dqs_asrt_cnt <= dqs_asrt_cnt + '1' after TCQ*1 ps;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if ((rst = '1') or (wrlvl_active = '0'))then
wr_lvl_start <= '0' after TCQ*1 ps;
elsif (dqs_asrt_cnt = "11") then
wr_lvl_start <= '1' after TCQ*1 ps;
end if;
end if;
end process;
-- shift register that is used to assert the DQS once every
-- 16 clock cycles during write leveling.
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
wr_level_dqs_stg_r <= "10000000000000000000" after TCQ*1 ps;
else
wr_level_dqs_stg_r <= (wr_level_dqs_stg_r(18 downto 0) & wr_level_dqs_stg_r(19)) after TCQ*1 ps;
end if;
end if;
end process;
gen_dqs_r_i: for dqs_r_i in 0 to (DQS_WIDTH-1) generate
begin
gen_ddr3_dqs: if (DRAM_TYPE(1 to 4) = "DDR3") generate
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
dqs_rst((dqs_r_i*4) + 0) <= '0' after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 1) <= '0' after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 2) <= '0' after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 3) <= '0' after TCQ*1 ps;
elsif (inv_dqs(dqs_r_i) = '1') then
dqs_rst((dqs_r_i*4) + 0) <= ((wr_level_dqs_stg_r(19) and wrlvl_active_r1) or (not(wrlvl_active_r1))) after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 1) <= '0' after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 2) <= ((wr_level_dqs_stg_r(19) and wrlvl_active_r1) or (not(wrlvl_active_r1))) after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 3) <= '0' after TCQ*1 ps;
elsif (inv_dqs(dqs_r_i) = '0') then
dqs_rst((dqs_r_i*4) + 0) <= '0' after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 1) <= ((wr_level_dqs_stg_r(19) and wrlvl_active_r1) or (not(wrlvl_active_r1))) after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 2) <= '0' after TCQ*1 ps;
dqs_rst((dqs_r_i*4) + 3) <= ((wr_level_dqs_stg_r(19) and wrlvl_active_r1) or (not(wrlvl_active_r1))) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
gen_ddr2_dqs: if (DRAM_TYPE(1 to 4) /= "DDR3") generate
begin
dqs_rst((dqs_r_i*4) +0) <= '0';
dqs_rst((dqs_r_i*4) +1) <= '1' when ((wr_level_dqs_asrt_r='1') or (wrlvl_active_r2='0')) else '0';
dqs_rst((dqs_r_i*4) +2) <= '0';
dqs_rst((dqs_r_i*4) +3) <= '1' when (wrlvl_active_r2='0') else '0';
end generate;
end generate;
--***************************************************************************
-- Format write data/mask: Data is in format: {fall, rise}
--***************************************************************************
gen_wrdata_mask_rdimm: if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
process (mc_data_sel,phy_wrdata_r,phy_wrdata,dfi_wrdata_r,dfi_wrdata)
begin
if ((mc_data_sel = '0') and (nCWL = 9)) then
wr_data_rise0 <= phy_wrdata_r((DQ_WIDTH-1) downto 0);
wr_data_fall0 <= phy_wrdata_r((2*DQ_WIDTH)-1 downto DQ_WIDTH);
wr_data_rise1 <= phy_wrdata_r((3*DQ_WIDTH)-1 downto 2*DQ_WIDTH);
wr_data_fall1 <= phy_wrdata_r((4*DQ_WIDTH)-1 downto 3*DQ_WIDTH);
else
if (mc_data_sel = '0') then
wr_data_rise0 <= phy_wrdata((DQ_WIDTH-1) downto 0);
wr_data_fall0 <= phy_wrdata((2*DQ_WIDTH)-1 downto DQ_WIDTH);
wr_data_rise1 <= phy_wrdata((3*DQ_WIDTH)-1 downto 2*DQ_WIDTH);
wr_data_fall1 <= phy_wrdata((4*DQ_WIDTH)-1 downto 3*DQ_WIDTH);
else
if ((nCWL = 7) or (nCWL = 9)) then
wr_data_rise0 <= dfi_wrdata_r((DQ_WIDTH-1) downto 0);
wr_data_fall0 <= dfi_wrdata_r((2*DQ_WIDTH)-1 downto DQ_WIDTH);
wr_data_rise1 <= dfi_wrdata_r((3*DQ_WIDTH)-1 downto 2*DQ_WIDTH);
wr_data_fall1 <= dfi_wrdata_r((4*DQ_WIDTH)-1 downto 3*DQ_WIDTH);
else
wr_data_rise0 <= dfi_wrdata((DQ_WIDTH-1) downto 0);
wr_data_fall0 <= dfi_wrdata((2*DQ_WIDTH)-1 downto DQ_WIDTH);
wr_data_rise1 <= dfi_wrdata((3*DQ_WIDTH)-1 downto 2*DQ_WIDTH);
wr_data_fall1 <= dfi_wrdata((4*DQ_WIDTH)-1 downto 3*DQ_WIDTH);
end if;
end if;
end if;
end process;
mask_data_rise0 <= (others => '0') when (mc_data_sel = '0') else
dfi_wrdata_mask_r((DQ_WIDTH/8)-1 downto 0) when ((mc_data_sel = '1') and ((REG_CTRL = "ON") and ((nCWL = 7) or (nCWL = 9)))) else
dfi_wrdata_mask((DQ_WIDTH/8)-1 downto 0);
mask_data_fall0 <= (others => '0') when (mc_data_sel = '0') else
dfi_wrdata_mask_r(2*(DQ_WIDTH/8)-1 downto (DQ_WIDTH/8)) when ((mc_data_sel = '1') and
((REG_CTRL = "ON") and ((nCWL = 7) or (nCWL = 9)))) else
dfi_wrdata_mask(2*(DQ_WIDTH/8)-1 downto (DQ_WIDTH/8));
mask_data_rise1 <= (others => '0') when (mc_data_sel = '0') else
dfi_wrdata_mask_r(3*(DQ_WIDTH/8)-1 downto 2*(DQ_WIDTH/8)) when ((mc_data_sel = '1') and
((REG_CTRL = "ON") and ((nCWL = 7) or (nCWL = 9)))) else
dfi_wrdata_mask(3*(DQ_WIDTH/8)-1 downto 2*(DQ_WIDTH/8));
mask_data_fall1 <= (others => '0') when (mc_data_sel = '0') else
dfi_wrdata_mask_r(4*(DQ_WIDTH/8)-1 downto 3*(DQ_WIDTH/8)) when ((mc_data_sel = '1') and
((REG_CTRL = "ON") and ((nCWL = 7) or (nCWL = 9)))) else
dfi_wrdata_mask (4*(DQ_WIDTH/8)-1 downto 3*(DQ_WIDTH/8));
end generate;
gen_wrdata_mask_udimm: if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
wr_data_rise0 <= dfi_wrdata(DQ_WIDTH-1 downto 0) when (mc_data_sel = '1') else
phy_wrdata(DQ_WIDTH-1 downto 0);
wr_data_fall0 <= dfi_wrdata((2*DQ_WIDTH)-1 downto DQ_WIDTH) when (mc_data_sel = '1') else
phy_wrdata((2*DQ_WIDTH)-1 downto DQ_WIDTH);
wr_data_rise1 <= dfi_wrdata((3*DQ_WIDTH)-1 downto 2*DQ_WIDTH) when (mc_data_sel = '1') else
phy_wrdata((3*DQ_WIDTH)-1 downto 2*DQ_WIDTH);
wr_data_fall1 <= dfi_wrdata((4*DQ_WIDTH)-1 downto 3*DQ_WIDTH) when (mc_data_sel = '1') else
phy_wrdata((4*DQ_WIDTH)-1 downto 3*DQ_WIDTH);
mask_data_rise0 <= dfi_wrdata_mask((DQ_WIDTH/8)-1 downto 0) when (mc_data_sel = '1') else
(others => '0');
mask_data_fall0 <= dfi_wrdata_mask(2*(DQ_WIDTH/8)-1 downto (DQ_WIDTH/8)) when (mc_data_sel = '1') else
(others => '0');
mask_data_rise1 <= dfi_wrdata_mask(3*(DQ_WIDTH/8)-1 downto 2*(DQ_WIDTH/8)) when (mc_data_sel = '1') else
(others => '0');
mask_data_fall1 <= dfi_wrdata_mask(4*(DQ_WIDTH/8)-1 downto 3*(DQ_WIDTH/8)) when (mc_data_sel = '1') else
(others => '0');
end generate;
end trans;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <tobiflex@opencores.org> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic;
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal clkenareg : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkenareg='1' THEN
-- IF falling_edge(clk) THEN
-- IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt, enaWRreg, enaRDreg)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaWRreg;
clkenareg <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaRDreg;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' AND enaWRreg='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' AND enaWRreg='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' AND enaWRreg='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <tobiflex@opencores.org> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic;
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal clkenareg : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkenareg='1' THEN
-- IF falling_edge(clk) THEN
-- IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt, enaWRreg, enaRDreg)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaWRreg;
clkenareg <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaRDreg;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' AND enaWRreg='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' AND enaWRreg='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' AND enaWRreg='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <tobiflex@opencores.org> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic;
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal clkenareg : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkenareg='1' THEN
-- IF falling_edge(clk) THEN
-- IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt, enaWRreg, enaRDreg)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaWRreg;
clkenareg <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaRDreg;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' AND enaWRreg='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' AND enaWRreg='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' AND enaWRreg='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2526.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n03i02526ent IS
END c07s03b05x00p06n03i02526ent;
ARCHITECTURE c07s03b05x00p06n03i02526arch OF c07s03b05x00p06n03i02526ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
type MVL is ('0','1','Z') ;
variable Macintosh : Apples;
variable Seville, valencia : Oranges;
variable V1 : MVL;
BEGIN
Macintosh := Apples (Seville) ;
V1 := Oranges (76) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p06n03i02526 - Target type is not an Integer or floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n03i02526arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2526.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n03i02526ent IS
END c07s03b05x00p06n03i02526ent;
ARCHITECTURE c07s03b05x00p06n03i02526arch OF c07s03b05x00p06n03i02526ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
type MVL is ('0','1','Z') ;
variable Macintosh : Apples;
variable Seville, valencia : Oranges;
variable V1 : MVL;
BEGIN
Macintosh := Apples (Seville) ;
V1 := Oranges (76) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p06n03i02526 - Target type is not an Integer or floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n03i02526arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2526.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n03i02526ent IS
END c07s03b05x00p06n03i02526ent;
ARCHITECTURE c07s03b05x00p06n03i02526arch OF c07s03b05x00p06n03i02526ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
type MVL is ('0','1','Z') ;
variable Macintosh : Apples;
variable Seville, valencia : Oranges;
variable V1 : MVL;
BEGIN
Macintosh := Apples (Seville) ;
V1 := Oranges (76) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p06n03i02526 - Target type is not an Integer or floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n03i02526arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity image_filter_FAST_t_opr_core_buf_val_0_V_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 11;
mem_size : integer := 1927
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
clk : in std_logic
);
end entity;
architecture rtl of image_filter_FAST_t_opr_core_buf_val_0_V_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1)) := d1;
end if;
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_FAST_t_opr_core_buf_val_0_V is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 1927;
AddressWidth : INTEGER := 11);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_FAST_t_opr_core_buf_val_0_V is
component image_filter_FAST_t_opr_core_buf_val_0_V_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC);
end component;
begin
image_filter_FAST_t_opr_core_buf_val_0_V_ram_U : component image_filter_FAST_t_opr_core_buf_val_0_V_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity image_filter_FAST_t_opr_core_buf_val_0_V_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 11;
mem_size : integer := 1927
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
clk : in std_logic
);
end entity;
architecture rtl of image_filter_FAST_t_opr_core_buf_val_0_V_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1)) := d1;
end if;
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_FAST_t_opr_core_buf_val_0_V is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 1927;
AddressWidth : INTEGER := 11);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_FAST_t_opr_core_buf_val_0_V is
component image_filter_FAST_t_opr_core_buf_val_0_V_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC);
end component;
begin
image_filter_FAST_t_opr_core_buf_val_0_V_ram_U : component image_filter_FAST_t_opr_core_buf_val_0_V_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_1x4 is
Port ( Selector : in STD_LOGIC;
input_A, input_B: in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end Multiplexer_1x4;
architecture skeleton of Multiplexer_1x4 is
begin
with Selector select
output <= input_A when '0',
input_B when others;
end skeleton; |
--
-- File Name: ScoreBoardGenericPkg.vhd
-- Design Unit Name: ScoreBoardGenericPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis email: jim@synthworks.com
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Removed deprecated SetAlertLogID in Singleton API
-- 02/2022 2022.02 Added WriteScoreboardYaml and GotScoreboards. Updated NewID with ParentID,
-- ReportMode, Search, PrintParent. Supports searching for Scoreboard models..
-- 01/2022 2022.01 Added CheckExpected. Added SetCheckCountZero to ScoreboardPType
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 10/2020 2020.10 Added Peek
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 11/2016 2016.11 Released as part of OSVVM
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2010 2010.08 Added Tailpointer
-- 12/2006 2006.12 Initial revision
--
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package ScoreboardGenericPkg is
generic (
type ExpectedType ;
type ActualType ;
function Match(Actual : ActualType ; -- defaults
Expected : ExpectedType) return boolean ; -- is "=" ;
function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
function actual_to_string (A : ActualType) return string -- is to_string ;
) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
-- subtype ExpectedType is std_logic_vector ;
-- subtype ActualType is std_logic_vector ;
-- alias Match is std_match [ActualType, ExpectedType return boolean] ; -- for std_logic_vector
-- alias expected_to_string is to_hstring [ExpectedType return string]; -- VHDL-2008
-- alias actual_to_string is to_hstring [ActualType return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreboardIdType is record
Id : integer_max ;
end record ScoreboardIdType ;
type ScoreboardIdArrayType is array (integer range <>) of ScoreboardIdType ;
type ScoreboardIdMatrixType is array (integer range <>, integer range <>) of ScoreboardIdType ;
-- Preparation for refactoring - if that ever happens.
subtype FifoIdType is ScoreboardIdType ;
subtype FifoIdArrayType is ScoreboardIdArrayType ;
subtype FifoIdMatrixType is ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) ; -- Deletes all allocated items
procedure Initialize (
constant ID : in ScoreboardIDType
) ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType ;
type ScoreBoardPType is protected
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-------------------------------
-- Array of Tagged Scoreboards
impure function CheckExpected (
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
-- ReportMode := ENABLED when not DoNotReport else DISABLED ;
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
-- Clear check counter. Caution does not change AffirmationCounters
procedure SetCheckCountZero ; -- Simple, with or without tags
procedure SetCheckCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
------------------------------------------------------------
------------------------------------------------------------
-- -- Deprecated Interface to NewID
-- impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- -- Vector: 1 to Size
-- impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Vector: X(X'Left) to X(X'Right)
-- impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Matrix: 1 to X, 1 to Y
-- impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
-- impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end protected ScoreBoardPType ;
------------------------------------------------------------
-- Deprecated Interface to NewID
impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- Vector: 1 to Size
impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end ScoreboardGenericPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreboardGenericPkg is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
--!! Replace the following with
-- type ScoreboardRecType is record
-- HeadPointer : ListPointerType ;
-- TailPointer : ListPointerType ;
-- PopListPointer : ListPointerType ;
--
-- ErrCnt : integer ;
-- DropCount : integer ;
-- ItemNumber : integer ;
-- PopCount : integer ;
-- CheckCount : integer ;
-- AlertLogID : AlertLogIDType ;
-- Name : NameStoreIDType ;
-- ReportMode : ScoreboardReportType ;
-- end record ScoreboardRecType ;
--
-- type ScoreboardRecArrayType is array (integer range <>) of ScoreboardRecType ;
-- type ScoreboardRecArrayPointerType is access ScoreboardRecArrayType ;
-- variable ScoreboardPointer : ScoreboardRecArrayPointerType ;
--
-- -- Alas unfortunately aliases don't word as follows:
-- -- alias HeadPointer(I) is ScoreboardPointer(I).HeadPointer ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
-- Original Code
-- variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
--
-- Legal, but crashes simulator more thoroughly
-- variable HeadPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- Working work around for QS 2020.04 and 2021.02
variable Template : ListArrayType(1 to 1) ; -- Work around for QS 2020.04 and 2021.02
variable HeadPointer : ListArrayPointerType := new ListArrayType'(Template) ;
variable TailPointer : ListArrayPointerType := new ListArrayType'(Template) ;
-- PopListPointer needed for Pop to be a function - alternately need 2019 features
variable PopListPointer : ListArrayPointerType := new ListArrayType'(Template) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
variable PrintIndexVar : boolean := TRUE ;
variable CalledNewID : boolean := FALSE ;
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Used by ScoreboardStore
variable NumItems : integer := 0 ;
constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
-- constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
procedure SetPrintIndex (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
PrintIndexVar := Enable ;
end procedure SetPrintIndex ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
constant MinNumItems : in integer
) is
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if NewNumItems > HeadPointer'length then
SetArrayIndex(1, NormalizeArraySize(NewNumItems, MinNumItems)) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- Local/Private to package
impure function LocalNewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable NameID : integer ;
begin
NameID := LocalNameStore.find(Name, ParentID, Search) ;
-- Share the scoreboards if they match
if NameID /= ID_NOT_FOUND.ID then
return ScoreboardIDType'(ID => NameID) ;
else
-- Resize Data Structure as necessary
GrowNumberItems(NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
AlertLogIDVar(NumItems) := NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, Search) ;
AlertIfNotEqual(AlertLogIDVar(NumItems), NameID, NumItems, "ScoreboardPkg: Index of LocalNameStore /= ScoreboardID") ;
return ScoreboardIDType'(ID => NumItems) ;
end if ;
end function LocalNewID ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
return LocalNewID(Name, ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector. Assumes valid range (done by NewID)
impure function LocalNewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
variable Result : ScoreboardIDArrayType(X(X'left) to X(X'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in Result'range loop
Result(i) := LocalNewID(Name & "(" & to_string(i) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1, Size) , ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Array parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Array parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
return LocalNewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix. Assumes valid indices (done by NewID)
impure function LocalNewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable Result : ScoreboardIdMatrixType(X(X'left) to X(X'right), Y(Y'left) to Y(Y'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ;
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in X(X'left) to X(X'right) loop
for j in Y(Y'left) to Y(Y'right) loop
Result(i, j) := LocalNewID(Name & "(" & to_string(i) & ", " & to_string(j) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1,X), (1,Y), ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Matrix parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, Y'length /= 2, "ScoreboardPkg.NewID Matrix parameter Y has " & to_string(Y'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Matrix parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
AlertIf(ParentID, Y(Y'Left) > Y(Y'right), "ScoreboardPkg.NewID Matrix parameter Y(Y'left): " & to_string(Y'Left) & " must be <= Y(Y'right): " & to_string(Y(Y'right)), FAILURE) ;
return LocalNewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
NumItems := 0 ;
CalledNewID := FALSE ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(Index) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(FirstIndexVar) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean ;
constant ExpectedInFIFO : in boolean := TRUE
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 and PrintIndexVar then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
if ExpectedInFIFO then
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
else
write(WriteBuf, " Received: " & expected_to_string(ExpectedPtr.all)) ;
if FoundError then
write(WriteBuf, " Expected: " & actual_to_string(ActualData)) ;
end if ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Scoreboard Store. Index. Tag.
impure function CheckExpected (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ExpectedData, FoundError, ExpectedInFIFO => FALSE) ;
return not FoundError ;
end function CheckExpected ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero (Index : integer) is
------------------------------------------------------------
begin
CheckCountVar(Index) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero is
------------------------------------------------------------
begin
CheckCountVar(FirstIndexVar) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
impure function GotScoreboards return boolean is
------------------------------------------------------------
begin
return CalledNewID ;
end function GotScoreboards ;
------------------------------------------------------------
-- pt local
procedure WriteScoreboardYaml (Index : integer; file CovYamlFile : text) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
write(buf, NAME_PREFIX & "- Name: " & '"' & string'(GetAlertLogName(AlertLogIDVar(Index))) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemCount: " & '"' & to_string(ItemNumberVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ErrorCount: " & '"' & to_string(ErrCntVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsChecked: " & '"' & to_string(CheckCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsPopped: " & '"' & to_string(PopCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsDropped: " & '"' & to_string(DropCountVar(Index)) & '"' & LF) ;
writeline(CovYamlFile, buf) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_sb.yml", FileName) ;
file SbYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
if AlertLogIDVar = NULL or AlertLogIDVar'length <= 0 then
Alert("Scoreboard.WriteScoreboardYaml: no scoreboards defined ", ERROR) ;
return ;
end if ;
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "TestCase: " & '"' & GetAlertLogName & '"' & LF) ;
swrite(buf, "Scoreboards: ") ;
writeline(SbYamlFile, buf) ;
if CalledNewID then
-- Used by singleton
for i in 1 to NumItems loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
else
-- Used by PT method, but not singleton
for i in AlertLogIDVar'range loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
end if ;
file_close(SbYamlFile) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: 1 to Size
--!! impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, (1, Size) , ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: X(X'Left) to X(X'Right)
--!! impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: 1 to X, 1 to Y
--!! impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
--!! impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
end protected body ScoreBoardPType ;
shared variable ScoreboardStore : ScoreBoardPType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, Size, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (
------------------------------------------------------------
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Item) ;
end procedure Push ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, ActualData) ;
end procedure Check ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end procedure Check ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, ActualData) ;
end function Check ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end function Check ;
-------------
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end procedure CheckExpected ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end procedure CheckExpected ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end function CheckExpected ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end function CheckExpected ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Item) ;
end procedure Pop ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Tag, Item) ;
end procedure Pop ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID) ;
end function Pop ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID, Tag) ;
end function Pop ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Tag, Item) ;
end procedure Peek ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Item) ;
end procedure Peek ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
-- return ScoreboardStore.Peek(Tag) ;
-- log("Issues compiling return later");
return ScoreboardStore.Peek(Index => ID.ID, Tag => Tag) ;
end function Peek ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Peek(Index => ID.ID) ;
end function Peek ;
------------------------------------------------------------
-- ScoreboardEmpty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function ScoreboardEmpty ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function ScoreboardEmpty ;
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function Empty ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function Empty ;
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, Name, ParentID, CreateHierarchy, DoNotReport) ;
--!! end procedure SetAlertLogID ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, A) ;
--!! end procedure SetAlertLogID ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType is
begin
return ScoreboardStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetItemCount(ID.ID) ;
end function GetItemCount ;
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPushCount(ID.ID) ;
end function GetPushCount ;
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPopCount(ID.ID) ;
end function GetPopCount ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetFifoCount(ID.ID) ;
end function GetFifoCount ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetCheckCount(ID.ID) ;
end function GetCheckCount ;
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetDropCount(ID.ID) ;
end function GetDropCount ;
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, ActualData) ;
end function Find ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, ItemNumber) ;
end procedure Flush ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Scoreboard YAML Reports
impure function GotScoreboards return boolean is
begin
return ScoreboardStore.GotScoreboards ;
end function GotScoreboards ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
begin
ScoreboardStore.WriteScoreboardYaml(FileName, OpenKind) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Deallocate ;
end procedure Deallocate ;
procedure Initialize (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Initialize ;
end procedure Initialize ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer is
begin
return GetAlertCount(ScoreboardStore.GetAlertLogID(ID.ID)) ;
end function GetErrorCount ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
ScoreboardStore.CheckFinish(ID.ID, FinishCheckCount, FinishEmpty) ;
end procedure CheckFinish ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) is
begin
-- ScoreboardStore.SetReportMode(ID.ID, ReportModeIn) ;
ScoreboardStore.SetReportMode(ReportModeIn) ;
end procedure SetReportMode ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType is
begin
-- return ScoreboardStore.GetReportMode(ID.ID) ;
return ScoreboardStore.GetReportMode ;
end function GetReportMode ;
--==========================================================
--!! Deprecated Subprograms
--==========================================================
------------------------------------------------------------
-- Deprecated interface to NewID
impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, Size, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
end ScoreboardGenericPkg ; |
-- Twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_encryption_monte_carlo_testbench128 is
end ecb_encryption_monte_carlo_testbench128;
architecture ecb_encryption128_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v, -- key vector input
pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_encryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_encryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_encryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Encryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process ecb_emc_proc;
end ecb_encryption128_monte_carlo_testbench_arch;
|
library verilog;
use verilog.vl_types.all;
entity controller_vlg_sample_tst is
port(
clk : in vl_logic;
coin_Detected : in vl_logic;
comp_equal_in : in vl_logic;
comp_greater_in : in vl_logic;
comp_smaller_in : in vl_logic;
reset : in vl_logic;
soda_choice : in vl_logic;
soda_price_0 : in vl_logic_vector(7 downto 0);
soda_price_1 : in vl_logic_vector(7 downto 0);
value_cents : in vl_logic_vector(7 downto 0);
sampler_tx : out vl_logic
);
end controller_vlg_sample_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- convert Hex string to 32-bit into std_logic_vector
function strhex_to_slv(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
-- convert Hex string to 32-bit SLV
function strhex_to_slv(s : string) return std_logic_vector is
variable int : string(1 to s'length) := s;
variable ptr : integer range 0 to 32 := 0;
variable slv: std_logic_vector(31 downto 0) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => slv(ptr+3 downto ptr) := "0000"; ptr := ptr+4;
when '1' => slv(ptr+3 downto ptr) := "0001"; ptr := ptr+4;
when '2' => slv(ptr+3 downto ptr) := "0010"; ptr := ptr+4;
when '3' => slv(ptr+3 downto ptr) := "0011"; ptr := ptr+4;
when '4' => slv(ptr+3 downto ptr) := "0100"; ptr := ptr+4;
when '5' => slv(ptr+3 downto ptr) := "0101"; ptr := ptr+4;
when '6' => slv(ptr+3 downto ptr) := "0110"; ptr := ptr+4;
when '7' => slv(ptr+3 downto ptr) := "0111"; ptr := ptr+4;
when '8' => slv(ptr+3 downto ptr) := "1000"; ptr := ptr+4;
when '9' => slv(ptr+3 downto ptr) := "1001"; ptr := ptr+4;
when 'a'|'A' => slv(ptr+3 downto ptr) := "1010"; ptr := ptr+4;
when 'b'|'B' => slv(ptr+3 downto ptr) := "1011"; ptr := ptr+4;
when 'c'|'C' => slv(ptr+3 downto ptr) := "1100"; ptr := ptr+4;
when 'd'|'D' => slv(ptr+3 downto ptr) := "1101"; ptr := ptr+4;
when 'e'|'E' => slv(ptr+3 downto ptr) := "1110"; ptr := ptr+4;
when 'f'|'F' => slv(ptr+3 downto ptr) := "1111"; ptr := ptr+4;
when others => null;
end case;
end loop;
return slv;
end strhex_to_slv;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- convert Hex string to 32-bit into std_logic_vector
function strhex_to_slv(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
-- convert Hex string to 32-bit SLV
function strhex_to_slv(s : string) return std_logic_vector is
variable int : string(1 to s'length) := s;
variable ptr : integer range 0 to 32 := 0;
variable slv: std_logic_vector(31 downto 0) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => slv(ptr+3 downto ptr) := "0000"; ptr := ptr+4;
when '1' => slv(ptr+3 downto ptr) := "0001"; ptr := ptr+4;
when '2' => slv(ptr+3 downto ptr) := "0010"; ptr := ptr+4;
when '3' => slv(ptr+3 downto ptr) := "0011"; ptr := ptr+4;
when '4' => slv(ptr+3 downto ptr) := "0100"; ptr := ptr+4;
when '5' => slv(ptr+3 downto ptr) := "0101"; ptr := ptr+4;
when '6' => slv(ptr+3 downto ptr) := "0110"; ptr := ptr+4;
when '7' => slv(ptr+3 downto ptr) := "0111"; ptr := ptr+4;
when '8' => slv(ptr+3 downto ptr) := "1000"; ptr := ptr+4;
when '9' => slv(ptr+3 downto ptr) := "1001"; ptr := ptr+4;
when 'a'|'A' => slv(ptr+3 downto ptr) := "1010"; ptr := ptr+4;
when 'b'|'B' => slv(ptr+3 downto ptr) := "1011"; ptr := ptr+4;
when 'c'|'C' => slv(ptr+3 downto ptr) := "1100"; ptr := ptr+4;
when 'd'|'D' => slv(ptr+3 downto ptr) := "1101"; ptr := ptr+4;
when 'e'|'E' => slv(ptr+3 downto ptr) := "1110"; ptr := ptr+4;
when 'f'|'F' => slv(ptr+3 downto ptr) := "1111"; ptr := ptr+4;
when others => null;
end case;
end loop;
return slv;
end strhex_to_slv;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- convert Hex string to 32-bit into std_logic_vector
function strhex_to_slv(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
-- convert Hex string to 32-bit SLV
function strhex_to_slv(s : string) return std_logic_vector is
variable int : string(1 to s'length) := s;
variable ptr : integer range 0 to 32 := 0;
variable slv: std_logic_vector(31 downto 0) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => slv(ptr+3 downto ptr) := "0000"; ptr := ptr+4;
when '1' => slv(ptr+3 downto ptr) := "0001"; ptr := ptr+4;
when '2' => slv(ptr+3 downto ptr) := "0010"; ptr := ptr+4;
when '3' => slv(ptr+3 downto ptr) := "0011"; ptr := ptr+4;
when '4' => slv(ptr+3 downto ptr) := "0100"; ptr := ptr+4;
when '5' => slv(ptr+3 downto ptr) := "0101"; ptr := ptr+4;
when '6' => slv(ptr+3 downto ptr) := "0110"; ptr := ptr+4;
when '7' => slv(ptr+3 downto ptr) := "0111"; ptr := ptr+4;
when '8' => slv(ptr+3 downto ptr) := "1000"; ptr := ptr+4;
when '9' => slv(ptr+3 downto ptr) := "1001"; ptr := ptr+4;
when 'a'|'A' => slv(ptr+3 downto ptr) := "1010"; ptr := ptr+4;
when 'b'|'B' => slv(ptr+3 downto ptr) := "1011"; ptr := ptr+4;
when 'c'|'C' => slv(ptr+3 downto ptr) := "1100"; ptr := ptr+4;
when 'd'|'D' => slv(ptr+3 downto ptr) := "1101"; ptr := ptr+4;
when 'e'|'E' => slv(ptr+3 downto ptr) := "1110"; ptr := ptr+4;
when 'f'|'F' => slv(ptr+3 downto ptr) := "1111"; ptr := ptr+4;
when others => null;
end case;
end loop;
return slv;
end strhex_to_slv;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- convert Hex string to 32-bit into std_logic_vector
function strhex_to_slv(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
-- convert Hex string to 32-bit SLV
function strhex_to_slv(s : string) return std_logic_vector is
variable int : string(1 to s'length) := s;
variable ptr : integer range 0 to 32 := 0;
variable slv: std_logic_vector(31 downto 0) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => slv(ptr+3 downto ptr) := "0000"; ptr := ptr+4;
when '1' => slv(ptr+3 downto ptr) := "0001"; ptr := ptr+4;
when '2' => slv(ptr+3 downto ptr) := "0010"; ptr := ptr+4;
when '3' => slv(ptr+3 downto ptr) := "0011"; ptr := ptr+4;
when '4' => slv(ptr+3 downto ptr) := "0100"; ptr := ptr+4;
when '5' => slv(ptr+3 downto ptr) := "0101"; ptr := ptr+4;
when '6' => slv(ptr+3 downto ptr) := "0110"; ptr := ptr+4;
when '7' => slv(ptr+3 downto ptr) := "0111"; ptr := ptr+4;
when '8' => slv(ptr+3 downto ptr) := "1000"; ptr := ptr+4;
when '9' => slv(ptr+3 downto ptr) := "1001"; ptr := ptr+4;
when 'a'|'A' => slv(ptr+3 downto ptr) := "1010"; ptr := ptr+4;
when 'b'|'B' => slv(ptr+3 downto ptr) := "1011"; ptr := ptr+4;
when 'c'|'C' => slv(ptr+3 downto ptr) := "1100"; ptr := ptr+4;
when 'd'|'D' => slv(ptr+3 downto ptr) := "1101"; ptr := ptr+4;
when 'e'|'E' => slv(ptr+3 downto ptr) := "1110"; ptr := ptr+4;
when 'f'|'F' => slv(ptr+3 downto ptr) := "1111"; ptr := ptr+4;
when others => null;
end case;
end loop;
return slv;
end strhex_to_slv;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_arbitrator is
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- active low pre-amp chip select
--AD_CONV: out std_logic; -- active high ADC chip select
--DAC_CS: out std_logic; -- active low DAC chip select
----- resets ---
AMP_SHDN: out std_logic; -- ADC pre-amp shutdown signal (active high)
-- control signals
spi_controller_busy: in std_logic;
dac_ready: in std_logic;
adc_send_data: out std_logic;
amp_send_data: out std_logic;
dac_send_data: out std_logic;
req_adc: in std_logic;
req_amp: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end spi_arbitrator;
architecture Behavioral of spi_arbitrator is
type arbitration_type is (waiting,adc,amp);
signal curr_state: arbitration_type := waiting;
signal amp_requested: std_logic;
signal adc_requested: std_logic;
signal delay: std_logic;
begin
dac_proc: process(clk,rst)
begin
if(rst = '1') then
dac_send_data <= '0';
elsif(rising_edge(clk)) then
if(dac_ready = '1') then
delay <= '1';
if(delay = '1') then
dac_send_data <= '1';
end if;
else
delay <= '0';
dac_send_data <= '0';
end if;
end if;
end process;
process(clk,rst)
begin
if(rst = '1') then
curr_state <= waiting;
adc_send_data <= '0';
amp_send_data <= '0';
elsif(rising_edge(clk)) then
if(spi_controller_busy = '1') then
adc_send_data <= '0';
amp_send_data <= '0';
curr_state <= waiting;
if(req_amp = '1') then
amp_requested <= '1';
elsif(req_adc = '1') then
adc_requested <= '1';
end if;
else
case curr_state is
when waiting =>
AMP_CS <= '1';
--AD_CONV <= '0';
if(req_amp = '1') then
amp_requested <= '1';
elsif(req_adc = '1') then
adc_requested <= '1';
end if;
if(amp_requested = '1') then
curr_state <= amp;
amp_requested <= '0';
elsif(adc_requested = '1') then
curr_state <= adc;
adc_requested <= '0';
end if;
when adc =>
AMP_CS <= '1';
--AD_CONV <= '1';
adc_send_data <= '1';
when amp =>
AMP_CS <= '0';
--AD_CONV <= '0';
amp_send_data <= '1';
when others =>
end case;
end if;
end if;
end process;
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
AMP_SHDN <= '0';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_arbitrator is
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- active low pre-amp chip select
--AD_CONV: out std_logic; -- active high ADC chip select
--DAC_CS: out std_logic; -- active low DAC chip select
----- resets ---
AMP_SHDN: out std_logic; -- ADC pre-amp shutdown signal (active high)
-- control signals
spi_controller_busy: in std_logic;
dac_ready: in std_logic;
adc_send_data: out std_logic;
amp_send_data: out std_logic;
dac_send_data: out std_logic;
req_adc: in std_logic;
req_amp: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end spi_arbitrator;
architecture Behavioral of spi_arbitrator is
type arbitration_type is (waiting,adc,amp);
signal curr_state: arbitration_type := waiting;
signal amp_requested: std_logic;
signal adc_requested: std_logic;
signal delay: std_logic;
begin
dac_proc: process(clk,rst)
begin
if(rst = '1') then
dac_send_data <= '0';
elsif(rising_edge(clk)) then
if(dac_ready = '1') then
delay <= '1';
if(delay = '1') then
dac_send_data <= '1';
end if;
else
delay <= '0';
dac_send_data <= '0';
end if;
end if;
end process;
process(clk,rst)
begin
if(rst = '1') then
curr_state <= waiting;
adc_send_data <= '0';
amp_send_data <= '0';
elsif(rising_edge(clk)) then
if(spi_controller_busy = '1') then
adc_send_data <= '0';
amp_send_data <= '0';
curr_state <= waiting;
if(req_amp = '1') then
amp_requested <= '1';
elsif(req_adc = '1') then
adc_requested <= '1';
end if;
else
case curr_state is
when waiting =>
AMP_CS <= '1';
--AD_CONV <= '0';
if(req_amp = '1') then
amp_requested <= '1';
elsif(req_adc = '1') then
adc_requested <= '1';
end if;
if(amp_requested = '1') then
curr_state <= amp;
amp_requested <= '0';
elsif(adc_requested = '1') then
curr_state <= adc;
adc_requested <= '0';
end if;
when adc =>
AMP_CS <= '1';
--AD_CONV <= '1';
adc_send_data <= '1';
when amp =>
AMP_CS <= '0';
--AD_CONV <= '0';
amp_send_data <= '1';
when others =>
end case;
end if;
end if;
end process;
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
AMP_SHDN <= '0';
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity FAM_tb is
end FAM_tb;
architecture tb of FAM_tb is
component FAM is
port( X, Y, B, Cin : in std_logic;
Sout, Cout : out std_logic);
end component;
signal X, Y, B, Cin, Sout, Cout : std_logic;
begin
mapping: FAM port map(X, Y, B, Cin, Sout, Cout);
--concurrent processes
process
begin
X <= '0'; wait for 40 ns;
X <= '1'; wait for 40 ns;
end process;
process
begin
Y <= '0'; wait for 20 ns;
Y <= '1'; wait for 20 ns;
end process;
process
begin
B <= '0'; wait for 10 ns;
B <= '1'; wait for 10 ns;
end process;
process
begin
Cin <= '0'; wait for 5 ns;
Cin <= '1'; wait for 5 ns;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of FAM_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.processor_functions.all;
ENTITY ram_infer IS
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (wordlen-1 DOWNTO 0);
write_address: IN integer RANGE 0 to 2**(n-oplen-1);
read_address: IN integer RANGE 0 to 2**(n-oplen-1);
we: IN std_logic;
q: OUT std_logic_vector (wordlen-1 DOWNTO 0)
);
END ram_infer;
ARCHITECTURE rtl OF ram_infer IS
SIGNAL ram_block : memory_array;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
END IF;
END PROCESS;
END rtl; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2645.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02645ent IS
END c13s03b01x00p02n01i02645ent;
ARCHITECTURE c13s03b01x00p02n01i02645arch OF c13s03b01x00p02n01i02645ent IS
BEGIN
TESTING: PROCESS
variable #k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02645 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02645arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2645.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02645ent IS
END c13s03b01x00p02n01i02645ent;
ARCHITECTURE c13s03b01x00p02n01i02645arch OF c13s03b01x00p02n01i02645ent IS
BEGIN
TESTING: PROCESS
variable #k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02645 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02645arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2645.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02645ent IS
END c13s03b01x00p02n01i02645ent;
ARCHITECTURE c13s03b01x00p02n01i02645arch OF c13s03b01x00p02n01i02645ent IS
BEGIN
TESTING: PROCESS
variable #k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02645 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02645arch;
|
-- basic array declarations
entity test is
end entity test;
architecture test_arch of test is
constant size : integer := 10;
type vector is array (0 to size-1) of integer;
constant c1 : integer := 1;
constant c2 : integer := 2;
constant c3 : integer := 3;
signal x1 : vector := (c1 => c1, 2=>2, others => c3);
type infvector is array (integer range <>) of integer;
constant x2 : infvector := (0 => 0, 1 => 1, 2 => 2);
begin
main: process
begin
report integer'image(x2'left);
report integer'image(x2'right);
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity record_test is
port (
o : out integer
);
end record_test;
architecture rtl of record_test is
type t_record is record
int : integer;
end record t_record;
function get_constants(choice : std_logic) return t_record is
variable v_const : t_record;
begin
if choice = '0' then
v_const := (int => 27.777 us / 83.333 ns);
elsif choice = '1' then
v_const := (int => 26.316 us / 83.333 ns);
end if;
return v_const;
end function get_constants;
constant rec_constant : t_record := get_constants('0');
begin
o <= rec_constant.int;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
package dbe_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
end dbe_common_pkg;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple wrapper for the 'spi_master' and 'spi_slave' cores, to synthesize the 2 cores and
-- test them in the simulator.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);
----- debug -----
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
----------------SLAVE-----------------------
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic; -- preload lookahead data request line
s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
s_wren_i : IN std_logic := 'X'; -- user data write enable
s_do_valid_o : OUT std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
s_do_o : OUT std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
----- debug -----
s_do_transfer_o : OUT std_logic; -- debug: internal transfer driver
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector (5 downto 0) -- debug: internal state register
-- s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_loopback;
architecture Structural of spi_loopback is
begin
--=============================================================================================
-- Component instantiation for the SPI master port
--=============================================================================================
Inst_spi_master: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => m_clk_i, -- system clock is used for serial and parallel ports
pclk_i => m_clk_i,
rst_i => m_rst_i,
spi_ssel_o => m_spi_ssel_o,
spi_sck_o => m_spi_sck_o,
spi_mosi_o => m_spi_mosi_o,
spi_miso_i => m_spi_miso_i,
di_req_o => m_di_req_o,
di_i => m_di_i,
wren_i => m_wren_i,
do_valid_o => m_do_valid_o,
do_o => m_do_o,
----- debug -----
do_transfer_o => m_do_transfer_o,
wren_o => m_wren_o,
wren_ack_o => m_wren_ack_o,
rx_bit_reg_o => m_rx_bit_reg_o,
state_dbg_o => m_state_dbg_o,
core_clk_o => m_core_clk_o,
core_n_clk_o => m_core_n_clk_o,
sh_reg_dbg_o => m_sh_reg_dbg_o
);
--=============================================================================================
-- Component instantiation for the SPI slave port
--=============================================================================================
Inst_spi_slave: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => s_clk_i,
spi_ssel_i => s_spi_ssel_i,
spi_sck_i => s_spi_sck_i,
spi_mosi_i => s_spi_mosi_i,
spi_miso_o => s_spi_miso_o,
di_req_o => s_di_req_o,
di_i => s_di_i,
wren_i => s_wren_i,
do_valid_o => s_do_valid_o,
do_o => s_do_o,
----- debug -----
do_transfer_o => s_do_transfer_o,
wren_o => s_wren_o,
wren_ack_o => s_wren_ack_o,
rx_bit_reg_o => s_rx_bit_reg_o,
state_dbg_o => s_state_dbg_o
-- sh_reg_dbg_o => s_sh_reg_dbg_o
);
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple wrapper for the 'spi_master' and 'spi_slave' cores, to synthesize the 2 cores and
-- test them in the simulator.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);
----- debug -----
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
----------------SLAVE-----------------------
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic; -- preload lookahead data request line
s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
s_wren_i : IN std_logic := 'X'; -- user data write enable
s_do_valid_o : OUT std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
s_do_o : OUT std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
----- debug -----
s_do_transfer_o : OUT std_logic; -- debug: internal transfer driver
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector (5 downto 0) -- debug: internal state register
-- s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_loopback;
architecture Structural of spi_loopback is
begin
--=============================================================================================
-- Component instantiation for the SPI master port
--=============================================================================================
Inst_spi_master: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => m_clk_i, -- system clock is used for serial and parallel ports
pclk_i => m_clk_i,
rst_i => m_rst_i,
spi_ssel_o => m_spi_ssel_o,
spi_sck_o => m_spi_sck_o,
spi_mosi_o => m_spi_mosi_o,
spi_miso_i => m_spi_miso_i,
di_req_o => m_di_req_o,
di_i => m_di_i,
wren_i => m_wren_i,
do_valid_o => m_do_valid_o,
do_o => m_do_o,
----- debug -----
do_transfer_o => m_do_transfer_o,
wren_o => m_wren_o,
wren_ack_o => m_wren_ack_o,
rx_bit_reg_o => m_rx_bit_reg_o,
state_dbg_o => m_state_dbg_o,
core_clk_o => m_core_clk_o,
core_n_clk_o => m_core_n_clk_o,
sh_reg_dbg_o => m_sh_reg_dbg_o
);
--=============================================================================================
-- Component instantiation for the SPI slave port
--=============================================================================================
Inst_spi_slave: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => s_clk_i,
spi_ssel_i => s_spi_ssel_i,
spi_sck_i => s_spi_sck_i,
spi_mosi_i => s_spi_mosi_i,
spi_miso_o => s_spi_miso_o,
di_req_o => s_di_req_o,
di_i => s_di_i,
wren_i => s_wren_i,
do_valid_o => s_do_valid_o,
do_o => s_do_o,
----- debug -----
do_transfer_o => s_do_transfer_o,
wren_o => s_wren_o,
wren_ack_o => s_wren_ack_o,
rx_bit_reg_o => s_rx_bit_reg_o,
state_dbg_o => s_state_dbg_o
-- sh_reg_dbg_o => s_sh_reg_dbg_o
);
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2371.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p07n01i02371ent IS
END c07s03b01x00p07n01i02371ent;
ARCHITECTURE c07s03b01x00p07n01i02371arch OF c07s03b01x00p07n01i02371ent IS
constant S1 : BIT_VECTOR := B"111_111_110";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((S1'LEFT = 0) and (S1'RIGHT = 8))
report "***PASSED TEST: c07s03b01x00p07n01i02371"
severity NOTE;
assert ((S1'LEFT = 0) and (S1'RIGHT = 8))
report "***FAILED TEST: c07s03b01x00p07n01i02371 - The number of elements in the aggregate is equal to the length of the string or bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p07n01i02371arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2371.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p07n01i02371ent IS
END c07s03b01x00p07n01i02371ent;
ARCHITECTURE c07s03b01x00p07n01i02371arch OF c07s03b01x00p07n01i02371ent IS
constant S1 : BIT_VECTOR := B"111_111_110";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((S1'LEFT = 0) and (S1'RIGHT = 8))
report "***PASSED TEST: c07s03b01x00p07n01i02371"
severity NOTE;
assert ((S1'LEFT = 0) and (S1'RIGHT = 8))
report "***FAILED TEST: c07s03b01x00p07n01i02371 - The number of elements in the aggregate is equal to the length of the string or bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p07n01i02371arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2371.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p07n01i02371ent IS
END c07s03b01x00p07n01i02371ent;
ARCHITECTURE c07s03b01x00p07n01i02371arch OF c07s03b01x00p07n01i02371ent IS
constant S1 : BIT_VECTOR := B"111_111_110";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((S1'LEFT = 0) and (S1'RIGHT = 8))
report "***PASSED TEST: c07s03b01x00p07n01i02371"
severity NOTE;
assert ((S1'LEFT = 0) and (S1'RIGHT = 8))
report "***FAILED TEST: c07s03b01x00p07n01i02371 - The number of elements in the aggregate is equal to the length of the string or bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p07n01i02371arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1304.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01304ent IS
END c08s04b00x00p06n01i01304ent;
ARCHITECTURE c08s04b00x00p06n01i01304arch OF c08s04b00x00p06n01i01304ent IS
signal X : integer := 5;
type INIT_1 is range 1 to 1000;
subtype SUBI_1 is INIT_1 range 10 to 20;
BEGIN
TESTING: PROCESS
BEGIN
SUBI_1 <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01304 - A subtype name can not used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01304
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1304.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01304ent IS
END c08s04b00x00p06n01i01304ent;
ARCHITECTURE c08s04b00x00p06n01i01304arch OF c08s04b00x00p06n01i01304ent IS
signal X : integer := 5;
type INIT_1 is range 1 to 1000;
subtype SUBI_1 is INIT_1 range 10 to 20;
BEGIN
TESTING: PROCESS
BEGIN
SUBI_1 <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01304 - A subtype name can not used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01304
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1304.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01304ent IS
END c08s04b00x00p06n01i01304ent;
ARCHITECTURE c08s04b00x00p06n01i01304arch OF c08s04b00x00p06n01i01304ent IS
signal X : integer := 5;
type INIT_1 is range 1 to 1000;
subtype SUBI_1 is INIT_1 range 10 to 20;
BEGIN
TESTING: PROCESS
BEGIN
SUBI_1 <= X;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01304 - A subtype name can not used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01304
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_fwft_64x512_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- return clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1 downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
phyiconf => phyiconf
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck);
clkread <= '0';
dqvalid <= '1';
end generate;
xc3se : if (tech = spartan3e) or (tech = spartan6) generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
dqvalid <= '1';
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddrphy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddrphy_builtin_pads(tech)=0 generate
phywop: ddrphy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
rskew,mobile,abits,nclk,ncs,scantest,phyiconf)
port map (
rst,clk,clkout,clkoutret,clkread,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,
addr,ba,dqin,dqout,dm,oen,dqs,dqsoen,rasn,casn,wen,csn,cke,ck,
moben,dqvalid,testen,testrst,scanen,testoen);
pads: ddrpads
generic map (tech,dbits,abits,nclk,ncs,0)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,
ddr_ad,ddr_ba,ddr_dq,
open,open,open,open,open,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen);
end generate;
nseppads: if ddrphy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrphy_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wo_pads is
begin
gut90: if (tech = ut90) generate
ddr_phy0: ut90nhbd_ddr_phy_wo_pads
generic map (
MHz => MHz, abits => abits, dbits => dbits,
nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen, rasn, casn, wen, csn, cke, ck,
moben, dqvalid, testen, testrst, scanen, testoen
);
ddr_clk_fb_out <= '0';
clkread <= '0';
end generate;
inf : if (tech = inferred) generate
ddr_phy0 : generic_ddr_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck, moben);
clkread <= '0';
dqvalid <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrpads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddrphy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddrphy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of ddr2pads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddr2phy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddr2phy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_odt(i), lddr_odt(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsse0 : if dqsse = 0 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad_ds generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
dqsse1 : if dqsse = 1 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.n2x_padcontrol_none;
-- With built-in pads
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0;
resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_dqsn_in,lddr_dqsn_out,lddr_dqsn_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
signal lddr_odt: std_logic_vector(ncs-1 downto 0);
signal customdin_exp: std_logic_vector(132 downto 0);
begin
customdin_exp(custombits-1 downto 0) <= customdin;
customdin_exp(customdin_exp'high downto custombits) <= (others => '0');
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
customdout <= (others => '0');
end generate;
stra2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
dqin_valid <= '1';
end generate;
stra3 : if (tech = stratix3) generate
ddr_phy0 : stratixiii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, rskew => rskew, eightbanks => eightbanks
)
port map (
rst, clk, clkref, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_pll, cal_rst, odt, oct);
dqin_valid <= '1';
end generate;
sp3a : if (tech = spartan3) generate
ddr_phy0 : spartan3a_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, tech => tech, rskew => rskew,
eightbanks => eightbanks)
port map ( rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_pll, odt);
dqin_valid <= '1';
end generate;
nextreme : if (tech = easic90) generate
ddr_phy0 : easic90_ddr2_phy
generic map (
tech => tech,
MHz => MHz,
clk_mul => clk_mul,
clk_div => clk_div,
dbits => dbits,
rstdelay => rstdelay,
eightbanks => eightbanks)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, odt, '1');
dqin_valid <= '1';
end generate;
nextreme2 : if (tech = easic45) generate
-- This requires dbits/8 extra bidir I/O that are suppliedd on the ddr_dqs port
ddr_phy0 : n2x_ddr2_phy
generic map (
MHz => MHz, rstdelay => rstdelay,
dbits => dbits, clk_mul => clk_mul, clk_div => clk_div, norefclk => norefclk,
eightbanks => eightbanks, dqsse => dqsse, abits => abits,
nclk => nclk, ncs => ncs, ctrl2en => ctrl2en)
port map (
rst => rst, clk => clk, clk270d => clkref,
clkout => clkout, clkoutret => clkoutret, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke,
ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs(dbits/8-1 downto 0), ddr_dqsn => ddr_dqsn, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt, rden_pad => ddr_dqs(dbits/4-1 downto dbits/8),
addr => addr, ba => ba, dqin => dqin, dqout => dqout, dm => dm,
noen => noen,
rasn => rasn, casn => casn, wen => wen, csn => csn, cke => cke,
odt => odt, read_pend => read_pend, dqin_valid => dqin_valid,
regwdata => regwdata, regwrite => regwrite, regrdata => regrdata,
ddr_web2 => ddr_web2, ddr_rasb2 => ddr_rasb2, ddr_casb2 => ddr_casb2,
ddr_ad2 => ddr_ad2, ddr_ba2 => ddr_ba2,
dq_control => customdin_exp(73 downto 56),
dqs_control => customdin_exp(55 downto 38),
ck_control => customdin_exp(37 downto 20),
cmd_control => customdin_exp(19 downto 2),
compen => customdin_exp(0),
compupd => customdin_exp(1)
);
ddr_clk_fb_out <= '0';
customdout <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddr2phy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddr2phy_builtin_pads(tech)=0 generate
phywop: ddr2phy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7,
ddelayb8,ddelayb9,ddelayb10,ddelayb11,
numidelctrl,norefclk,rskew,eightbanks,dqsse,abits,nclk,ncs,
resync,custombits,scantest)
port map (
rst,clk,clkref,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt,
addr,ba,dqin,dqout,dm,oen,noen,dqs,dqsoen,rasn,casn,wen,csn,cke,
cal_en,cal_inc,cal_pll,cal_rst,odt,oct,
read_pend,regwdata,regwrite,regrdata,dqin_valid,customclk,customdin,customdout,
testen,testrst,scanen,testoen);
pads: ddr2pads
generic map (tech,dbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,ddr_dqsn,
ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt);
end generate;
nseppads: if ddr2phy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_dqsn_in <= (others => '0');
lddr_dqsn_out <= (others => '0');
lddr_dqsn_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
lddr_odt <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
-- without pads (typically used for ASIC technologies)
entity ddr2phy_wo_pads is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wo_pads is
begin
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 generate
customdout <= (others => '0');
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddr_phy0 : virtex5_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, ddelayb8 => ddelayb8,
ddelayb9 => ddelayb9, ddelayb10 => ddelayb10, ddelayb11 => ddelayb11,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkref, clkout, clkoutret, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen,ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
sp6 : if (tech = spartan6) generate
ddr_phy0 : spartan6_ddr2_phy_wo_pads
generic map (
MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
tech => tech, rskew => rskew,
eightbanks => eightbanks,
abits => abits, nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clkb <= (others => '0');
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
inf : if (has_ddr2phy(tech) = 0) generate
ddr_phy0 : generic_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
eightbanks => eightbanks, abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, "111", odt
);
dqin_valid <= '1';
end generate;
end;
-------------------------------------------------------------------------------
-- LPDDR2 phy
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity lpddr2phy_wo_pads is
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture tmap of lpddr2phy_wo_pads is
begin
inf: if true generate
phy0: generic_lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits,
nclk => nclk,
ncs => ncs,
clkratio => clkratio,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dm,
ckstop => ckstop,
boot => boot,
wrpend => wrpend,
rdpend => rdpend,
wrreq => wrreq,
rdvalid => rdvalid,
refcal => refcal,
refcalwu => refcalwu,
refcaldone => refcaldone,
phycmd => phycmd,
phycmden => phycmden,
phycmdin => phycmdin,
phycmdout => phycmdout,
testen => testen,
testrst => testrst,
scanen => scanen,
testoen => testoen);
end generate;
end;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C3 is
port (A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
F: out std_logic_vector(7 downto 0)
);
end C3;
architecture circuito of C3 is
begin
F <= A xor B;
end circuito; |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity Mult is
generic (
wordLengthA : natural := 8;
wordLengthB : natural := 8;
fractionalBitsA : natural := 7;
fractionalBitsB : natural := 7;
wordLengthP : natural := 16;
fractionalBitsP : natural := 7
);
port (
a : in std_logic_vector(wordLengthA-1 downto 0);
b : in std_logic_vector(wordLengthB-1 downto 0);
p : out std_logic_vector(wordLengthP-1 downto 0)
);
end entity ; -- Mult
architecture arch of Mult is
signal product : signed(wordLengthA+wordLengthB-1 downto 0);
signal pEntire : std_logic_vector(wordLengthA+wordLengthB-1 downto 0);
constant LSB : natural := fractionalBitsA+fractionalBitsB-fractionalBitsP;
constant MSB : natural := LSB + wordLengthP-1;
begin
product <= (signed(a)*signed(b));
pEntire <= std_logic_vector(product);
p <= pEntire(MSB downto LSB);
end architecture ; -- arch |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
use work.tb_05_13.all;
-- end not in book
entity adder is
port ( a, b : in word;
sum : out word );
end entity adder;
|
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