content stringlengths 1 1.04M ⌀ |
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-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- BBC Micro for Altera DE1
--
-- Copyright (c) 2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
... |
library IEEE;
use IEEE.std_logic_1164.All;
entity HybridVelocityCounter is port (
clk : in std_logic;
encoder : in std_logic;
speed : out real;
measurementType: out std_logic);
end HybridVelocityCounter;
architecture velocity of HybridVelocityCounter is
type measurementTypes is (HighSpeed, LowSpee... |
-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, ... |
-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620.P2: Multi transport transactions occurred on concurrent signal asg passed
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- Copyright (c) ARMadeus Project 2009
--
-- Wishbone component that drive sn74hc594 8 bits shift register
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (a... |
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : F... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; |
------------------------------------------------------------------------------
---- ----
---- gmZPU core
---- ----
---- http://github.com/sonologic/gmzpu ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. A... |
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. A... |
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. A... |
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. A... |
-- Template for VGA output by: Rene Kristensen
-- This design template uses gated clocks which generally are bad design practice.
-- This implies that the template design is not optimized for speed and will only serve for educational purpose.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
enti... |
package Config is
constant CfgClkGating : boolean := false;
end Config;
package body Config is
end Config;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:33 03/21/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/MII_test2.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Descri... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- NEED RESULT: ARCH00577: Can declare entities with same name as entities declared in a use'd pkg passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
package std_ovl_procs is
------------------------------------------------------------------------------
-- U... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\CPU_Subsystem_8_bit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- ----... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_2 is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_2 is
signal sig : std_logic := ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_2 is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_2 is
signal sig : std_logic := ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
entity tb_rec04 is
end tb_rec04;
library ieee;
use ieee.std_logic_1164.all;
use work.rec04_pkg.all;
architecture behav of tb_rec04 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec04
port map (inp => inp, o => r);
process
begin
inp.a <= "0000";
inp.b <= '1';
wait for 1... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
library ieee ;
entity mytestbench is
end mytestbench;
architecture arch of mytestbench is
signal zero_length_array : bit_vector(-1 downto 0);
begin
-- Just here so we get a meaningful dump.
main_process: process
begin
wait for 10 ns;
wait;
end process;
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
entity LIFO is
generic(
-- address bus
m: integer := 5;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;... |
------------------------------------------------------------------------------------------
---------------------------- Global PCI --------------------------------------------
------------------------------------------------------------------------------------------
package GLOBAL_PCI_CONFIG is
-- Cloc... |
-- This example was provided by:
-- Bruce Cockburn and Jie Han
-- However it was a collaboration between Qiushi Jiang and myself
-- to modify it and fix up changes
library IEEE;
using IEEE.STD_LOGIC_1164.all;
entity NBitAdder is
generic(width: integer := 16);
Port (
A: in STD_LOGIC_VECTOR... |
-------------------------------------------------------------------------------
--
-- Title : or3
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : or3.vhd
-- Generated : Fri ... |
-------------------------------------------------------------------------------
--
-- Title : or3
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : or3.vhd
-- Generated : Fri ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:10:16 07/01/2015
-- Design Name:
-- Module Name: keyMatrixLED - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.constants.all;
entity test_shifter is
end test_shifter;
architecture testbench of test_shifter is
component bshift
port (
direction : in std_logic; -- '1' for left, '0' for right
logical : in std_logic; -- '1' for logical, '0' for arithme... |
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--****************************... |
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--****************************... |
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--****************************... |
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--****************************... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2014
-- Module Name: MUX_2to1
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool... |
----------------------------------------------------------------------------------
--
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Michael J. Wouters
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
... |
-------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 ... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fo... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fo... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fo... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fo... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the fo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux8x2 is
port(
in0: in unsigned(15 downto 0);
in1: in unsigned(15 downto 0);
in2: in unsigned(15 downto 0);
in3: in unsigned(15 downto 0);
in4: in unsigned(15 downto 0);
in5: in unsigned(15 downto 0);
in6: in unsig... |
-- $Id: tb_tst_rlink_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_n2
-- Description: Configurat... |
library verilog;
use verilog.vl_types.all;
entity arm_alu is
port(
alu_or_mac : in vl_logic;
alu_op1 : in vl_logic_vector(31 downto 0);
alu_op2 : in vl_logic_vector(31 downto 0);
alu_sel : in vl_logic_vector(3 downto 0);
alu_cin ... |
---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit si... |
---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit si... |
---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit si... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tl_car_bench is
port(
db_clk: in std_logic;
db_reset: in std_logic;
db_switches: in std_logic_vector(3 downto 0);
db_leds: out std_logic_vector(7 downto 0);
--
l_lvds_io: inout std_logic;
r_lvds_io: inout std_logic;
--
i2s1... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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