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-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.714000,HLS_SYN_LAT=45,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=329,HLS_SYN_LUT=214}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_178 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_187 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_134_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_123_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_206 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_211 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal acc_1_fu_167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal acc_reg_89 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_106_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_102 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_157_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_123_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_fu_161_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
acc_reg_89_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
acc_reg_89 <= acc_1_fu_167_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
acc_reg_89 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0))) then
data1_reg_114 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
data1_reg_114 <= x;
end if;
end if;
end process;
i_reg_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_reg_102 <= i_1_reg_206;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_102 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_206 <= grp_fu_123_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_178 <= i_cast_fu_130_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0))) then
tmp_1_reg_187 <= tmp_1_fu_142_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_6_reg_211 <= tmp_6_fu_161_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_134_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
acc_1_fu_167_p2 <= std_logic_vector(unsigned(tmp_6_reg_211) + unsigned(acc_reg_89));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_157_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_123_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_106_p4, i_reg_102)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_123_p0 <= i_reg_102;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_123_p0 <= i_phi_fu_106_p4;
else
grp_fu_123_p0 <= "XXXXX";
end if;
end process;
grp_fu_123_p2 <= std_logic_vector(unsigned(grp_fu_123_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_130_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_102),32));
i_phi_fu_106_p4 <= i_reg_102;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3, tmp_3_fu_148_p1, tmp_4_fu_153_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_153_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_148_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_142_p2, tmp_1_reg_187, tmp_fu_134_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_187 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_0) and (tmp_1_fu_142_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_142_p2 <= "1" when (i_reg_102 = ap_const_lv5_0) else "0";
tmp_3_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_123_p2),64));
tmp_4_fu_153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_5_fu_157_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_178),64));
tmp_6_fu_161_p0 <= c_q0;
tmp_6_fu_161_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(tmp_6_fu_161_p0) * signed(data1_reg_114))), 32));
tmp_fu_134_p3 <= i_reg_102(4 downto 4);
y <= acc_reg_89;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_134_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_134_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
|
-- BBC Micro for Altera DE1
--
-- Copyright (c) 2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- MC6845 CRTC
--
-- Synchronous implementation for FPGA
--
-- (C) 2011 Mike Stirling
--
-- Corrected cursor flash rate
-- Fixed incorrect positioning of cursor when over left most character
-- Fixed timing of VSYNC
-- Fixed interlaced timing (add an extra line)
-- Implemented r05_v_total_adj
-- Implemented delay parts of r08_interlace (see Hitacht HD6845SP datasheet)
--
-- (C) 2015 David Banks
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mc6845 is
port (
CLOCK : in std_logic;
CLKEN : in std_logic;
nRESET : in std_logic;
-- Bus interface
ENABLE : in std_logic;
R_nW : in std_logic;
RS : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- Display interface
VSYNC : out std_logic;
HSYNC : out std_logic;
DE : out std_logic;
CURSOR : out std_logic;
LPSTB : in std_logic;
-- Memory interface
MA : out std_logic_vector(13 downto 0);
RA : out std_logic_vector(4 downto 0)
);
end entity;
architecture rtl of mc6845 is
-- Host-accessible registers
signal addr_reg : std_logic_vector(4 downto 0); -- Currently addressed register
-- These are write-only
signal r00_h_total : unsigned(7 downto 0); -- Horizontal total, chars
signal r01_h_displayed : unsigned(7 downto 0); -- Horizontal active, chars
signal r02_h_sync_pos : unsigned(7 downto 0); -- Horizontal sync position, chars
signal r03_v_sync_width : unsigned(3 downto 0); -- Vertical sync width, scan lines (0=16 lines)
signal r03_h_sync_width : unsigned(3 downto 0); -- Horizontal sync width, chars (0=no sync)
signal r04_v_total : unsigned(6 downto 0); -- Vertical total, character rows
signal r05_v_total_adj : unsigned(4 downto 0); -- Vertical offset, scan lines
signal r06_v_displayed : unsigned(6 downto 0); -- Vertical active, character rows
signal r07_v_sync_pos : unsigned(6 downto 0); -- Vertical sync position, character rows
signal r08_interlace : std_logic_vector(7 downto 0);
signal r09_max_scan_line_addr : unsigned(4 downto 0);
signal r10_cursor_mode : std_logic_vector(1 downto 0);
signal r10_cursor_start : unsigned(4 downto 0); -- Cursor start, scan lines
signal r11_cursor_end : unsigned(4 downto 0); -- Cursor end, scan lines
signal r12_start_addr_h : unsigned(5 downto 0);
signal r13_start_addr_l : unsigned(7 downto 0);
-- These are read/write
signal r14_cursor_h : unsigned(5 downto 0);
signal r15_cursor_l : unsigned(7 downto 0);
-- These are read-only
signal r16_light_pen_h : unsigned(5 downto 0);
signal r17_light_pen_l : unsigned(7 downto 0);
-- Timing generation
-- Horizontal counter counts position on line
signal h_counter : unsigned(7 downto 0);
-- HSYNC counter counts duration of sync pulse
signal h_sync_counter : unsigned(3 downto 0);
-- Row counter counts current character row
signal row_counter : unsigned(6 downto 0);
-- Line counter counts current line within each character row
signal line_counter : unsigned(4 downto 0);
-- VSYNC counter counts duration of sync pulse
signal v_sync_counter : unsigned(3 downto 0);
-- Field counter counts number of complete fields for cursor flash
signal field_counter : unsigned(4 downto 0);
-- Internal signals
signal h_sync_start : std_logic;
signal v_sync_start : std_logic;
signal h_display : std_logic;
signal h_display_early : std_logic;
signal hs : std_logic;
signal v_display : std_logic;
signal v_display_early : std_logic;
signal vs : std_logic;
signal odd_field : std_logic;
signal ma_i : unsigned(13 downto 0);
signal ma_row_start : unsigned(13 downto 0); -- Start address of current character row
signal cursor_i : std_logic;
signal lpstb_i : std_logic;
signal de0 : std_logic;
signal de1 : std_logic;
signal de2 : std_logic;
signal cursor0 : std_logic;
signal cursor1 : std_logic;
signal cursor2 : std_logic;
begin
HSYNC <= hs; -- External HSYNC driven directly from internal signal
VSYNC <= vs; -- External VSYNC driven directly from internal signal
de0 <= h_display and v_display;
-- In Mode 7 DE Delay is set to 01, but in our implementation no delay is needed
-- TODO: Fix SAA5050
DE <= de0 when r08_interlace(5 downto 4) = "00" else
de0 when r08_interlace(5 downto 4) = "01" else -- not accurate, should be de1
de2 when r08_interlace(5 downto 4) = "10" else
'0';
-- Cursor output generated combinatorially from the internal signal in
-- accordance with the currently selected cursor mode
cursor0 <= cursor_i when r10_cursor_mode = "00" else
'0' when r10_cursor_mode = "01" else
(cursor_i and field_counter(3)) when r10_cursor_mode = "10" else
(cursor_i and field_counter(4));
-- In Mode 7 Cursor Delay is set to 10, but in our implementation one one cycle is needed
-- TODO: Fix SAA5050
CURSOR <= cursor0 when r08_interlace(7 downto 6) = "00" else
cursor1 when r08_interlace(7 downto 6) = "01" else
cursor1 when r08_interlace(7 downto 6) = "10" else -- not accurate, should be cursor2
'0';
-- Synchronous register access. Enabled on every clock.
process(CLOCK,nRESET)
begin
if nRESET = '0' then
-- Reset registers to defaults
addr_reg <= (others => '0');
r00_h_total <= (others => '0');
r01_h_displayed <= (others => '0');
r02_h_sync_pos <= (others => '0');
r03_v_sync_width <= (others => '0');
r03_h_sync_width <= (others => '0');
r04_v_total <= (others => '0');
r05_v_total_adj <= (others => '0');
r06_v_displayed <= (others => '0');
r07_v_sync_pos <= (others => '0');
r08_interlace <= (others => '0');
r09_max_scan_line_addr <= (others => '0');
r10_cursor_mode <= (others => '0');
r10_cursor_start <= (others => '0');
r11_cursor_end <= (others => '0');
r12_start_addr_h <= (others => '0');
r13_start_addr_l <= (others => '0');
r14_cursor_h <= (others => '0');
r15_cursor_l <= (others => '0');
DO <= (others => '0');
elsif rising_edge(CLOCK) then
if ENABLE = '1' then
if R_nW = '1' then
-- Read
case addr_reg is
when "01100" =>
DO <= "00" & std_logic_vector(r12_start_addr_h);
when "01101" =>
DO <= std_logic_vector(r13_start_addr_l);
when "01110" =>
DO <= "00" & std_logic_vector(r14_cursor_h);
when "01111" =>
DO <= std_logic_vector(r15_cursor_l);
when "10000" =>
DO <= "00" & std_logic_vector(r16_light_pen_h);
when "10001" =>
DO <= std_logic_vector(r17_light_pen_l);
when others =>
DO <= (others => '0');
end case;
else
-- Write
if RS = '0' then
addr_reg <= DI(4 downto 0);
else
case addr_reg is
when "00000" =>
r00_h_total <= unsigned(DI);
when "00001" =>
r01_h_displayed <= unsigned(DI);
when "00010" =>
r02_h_sync_pos <= unsigned(DI);
when "00011" =>
r03_v_sync_width <= unsigned(DI(7 downto 4));
r03_h_sync_width <= unsigned(DI(3 downto 0));
when "00100" =>
r04_v_total <= unsigned(DI(6 downto 0));
when "00101" =>
r05_v_total_adj <= unsigned(DI(4 downto 0));
when "00110" =>
r06_v_displayed <= unsigned(DI(6 downto 0));
when "00111" =>
r07_v_sync_pos <= unsigned(DI(6 downto 0));
when "01000" =>
r08_interlace <= DI(7 downto 0);
when "01001" =>
r09_max_scan_line_addr <= unsigned(DI(4 downto 0));
when "01010" =>
r10_cursor_mode <= DI(6 downto 5);
r10_cursor_start <= unsigned(DI(4 downto 0));
when "01011" =>
r11_cursor_end <= unsigned(DI(4 downto 0));
when "01100" =>
r12_start_addr_h <= unsigned(DI(5 downto 0));
when "01101" =>
r13_start_addr_l <= unsigned(DI(7 downto 0));
when "01110" =>
r14_cursor_h <= unsigned(DI(5 downto 0));
when "01111" =>
r15_cursor_l <= unsigned(DI(7 downto 0));
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process; -- registers
-- Horizontal, vertical and address counters
process(CLOCK,nRESET)
variable ma_row_start : unsigned(13 downto 0);
variable max_scan_line : unsigned(4 downto 0);
variable adj_scan_line : unsigned(4 downto 0);
variable in_adj : std_logic;
variable need_adj : std_logic;
begin
if nRESET = '0' then
-- H
h_counter <= (others => '0');
-- V
line_counter <= (others => '0');
row_counter <= (others => '0');
odd_field <= '0';
-- Fields (cursor flash)
field_counter <= (others => '0');
-- Addressing
ma_row_start := (others => '0');
ma_i <= (others => '0');
in_adj := '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Horizontal counter increments on each clock, wrapping at
-- h_total
if h_counter = r00_h_total then
-- h_total reached
h_counter <= (others => '0');
-- Compute
if r05_v_total_adj /= 0 or odd_field = '1' then
need_adj := '1';
else
need_adj := '0';
end if;
-- Compute the max scan line for this row
if in_adj = '0' then
-- This is a normal row, so use r09_max_scan_line_addr
max_scan_line := r09_max_scan_line_addr;
else
-- This is the "adjust" row, so use r05_v_total_adj
max_scan_line := r05_v_total_adj - 1;
-- If interlaced, the odd field contains an additional scan line
if odd_field = '1' then
if r08_interlace(1 downto 0) = "11" then
max_scan_line := max_scan_line + 2;
else
max_scan_line := max_scan_line + 1;
end if;
end if;
end if;
-- In interlace sync + video mode mask off the LSb of the
-- max scan line address
if r08_interlace(1 downto 0) = "11" then
max_scan_line(0) := '0';
end if;
if line_counter = max_scan_line and ((need_adj = '0' and row_counter = r04_v_total) or in_adj = '1') then
line_counter <= (others => '0');
-- If in interlace mode we toggle to the opposite field.
-- Save on some logic by doing this here rather than at the
-- end of v_total_adj - it shouldn't make any difference to the
-- output
if r08_interlace(0) = '1' then
odd_field <= not odd_field;
else
odd_field <= '0';
end if;
-- Address is loaded from start address register at the top of
-- each field and the row counter is reset
ma_row_start := r12_start_addr_h & r13_start_addr_l;
row_counter <= (others => '0');
-- Increment field counter
field_counter <= field_counter + 1;
-- Reset the in extra time flag
in_adj := '0';
elsif in_adj = '0' and line_counter = max_scan_line then
-- Scan line counter increments, wrapping at max_scan_line_addr
-- Next character row
line_counter <= (others => '0');
-- On all other character rows within the field the row start address is
-- increased by h_displayed and the row counter is incremented
ma_row_start := ma_row_start + r01_h_displayed;
row_counter <= row_counter + 1;
-- Test if we are entering the adjust phase, and set
-- in_adj accordingly
if row_counter = r04_v_total and need_adj = '1' then
in_adj := '1';
end if;
else
-- Next scan line. Count in twos in interlaced sync+video mode
if r08_interlace(1 downto 0) = "11" then
line_counter <= line_counter + 2;
line_counter(0) <= '0'; -- Force to even
else
line_counter <= line_counter + 1;
end if;
end if;
-- Memory address preset to row start at the beginning of each
-- scan line
ma_i <= ma_row_start;
else
-- Increment horizontal counter
h_counter <= h_counter + 1;
-- Increment memory address
ma_i <= ma_i + 1;
end if;
end if;
end if;
end process;
-- Signals to mark hsync and and vsync in even and odd fields
process(h_counter, r00_h_total, r02_h_sync_pos, odd_field)
begin
h_sync_start <= '0';
v_sync_start <= '0';
if h_counter = r02_h_sync_pos then
h_sync_start <= '1';
end if;
-- dmb: measurements on a real beeb confirm this is the actual
-- 6845 behaviour. i.e. in non-interlaced mode the start of vsync
-- coinscides with the start of the active display, and in intelaced
-- mode the vsync of the odd field is delayed by half a scan line
if (odd_field = '0' and h_counter = 0) or (odd_field = '1' and h_counter = "0" & r00_h_total(7 downto 1)) then
v_sync_start <= '1';
end if;
end process;
h_display_early <= '1' when h_counter < r01_h_displayed else '0';
v_display_early <= '1' when row_counter < r06_v_displayed else '0';
-- Video timing and sync counters
process(CLOCK,nRESET)
begin
if nRESET = '0' then
-- H
h_display <= '0';
hs <= '0';
h_sync_counter <= (others => '0');
-- V
v_display <= '0';
vs <= '0';
v_sync_counter <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Horizontal active video
h_display <= h_display_early;
-- Horizontal sync
if h_sync_start = '1' or hs = '1' then
-- In horizontal sync
hs <= '1';
h_sync_counter <= h_sync_counter + 1;
else
h_sync_counter <= (others => '0');
end if;
if h_sync_counter = r03_h_sync_width then
-- Terminate hsync after h_sync_width (0 means no hsync so this
-- can immediately override the setting above)
hs <= '0';
end if;
-- Vertical active video
v_display <= v_display_early;
-- Vertical sync occurs either at the same time as the horizontal sync (even fields)
-- or half a line later (odd fields)
if (v_sync_start = '1') then
if (row_counter = r07_v_sync_pos and line_counter = 0) or vs = '1' then
-- In vertical sync
vs <= '1';
v_sync_counter <= v_sync_counter + 1;
else
v_sync_counter <= (others => '0');
end if;
if v_sync_counter = r03_v_sync_width and vs = '1' then
-- Terminate vsync after v_sync_width (0 means 16 lines so this is
-- masked by 'vs' to ensure a full turn of the counter in this case)
vs <= '0';
end if;
end if;
end if;
end if;
end process;
-- Address generation
process(CLOCK,nRESET)
variable slv_line : std_logic_vector(4 downto 0);
begin
if nRESET = '0' then
RA <= (others => '0');
MA <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
slv_line := std_logic_vector(line_counter);
-- Character row address is just the scan line counter delayed by
-- one clock to line up with the syncs.
if r08_interlace(1 downto 0) = "11" then
-- In interlace sync and video mode the LSb is determined by the
-- field number. The line counter counts up in 2s in this case.
RA <= slv_line(4 downto 1) & (slv_line(0) or odd_field);
else
RA <= slv_line;
end if;
-- Internal memory address delayed by one cycle as well
MA <= std_logic_vector(ma_i);
end if;
end if;
end process;
-- Cursor control
process(CLOCK,nRESET)
variable cursor_line : std_logic;
begin
-- Internal cursor enable signal delayed by 1 clock to line up
-- with address outputs
if nRESET = '0' then
cursor_i <= '0';
cursor_line := '0';
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
if h_display_early = '1' and v_display_early = '1' and ma_i = r14_cursor_h & r15_cursor_l then
if line_counter = 0 then
-- Suppress wrap around if last line is > max scan line
cursor_line := '0';
end if;
if line_counter = r10_cursor_start then
-- First cursor scanline
cursor_line := '1';
end if;
-- Cursor output is asserted within the current cursor character
-- on the selected lines only
cursor_i <= cursor_line;
if line_counter = r11_cursor_end then
-- Last cursor scanline
cursor_line := '0';
end if;
else
-- Cursor is off in all character positions apart from the
-- selected one
cursor_i <= '0';
end if;
end if;
end if;
end process;
-- Light pen capture
process(CLOCK,nRESET)
begin
if nRESET = '0' then
lpstb_i <= '0';
r16_light_pen_h <= (others => '0');
r17_light_pen_l <= (others => '0');
elsif rising_edge(CLOCK) then
if CLKEN = '1' then
-- Register light-pen strobe input
lpstb_i <= LPSTB;
if LPSTB = '1' and lpstb_i = '0' then
-- Capture address on rising edge
r16_light_pen_h <= ma_i(13 downto 8);
r17_light_pen_l <= ma_i(7 downto 0);
end if;
end if;
end if;
end process;
-- Delayed CURSOR and DE (selected by R08)
process(CLOCK,nRESET)
begin
if rising_edge(CLOCK) then
if CLKEN = '1' then
de1 <= de0;
de2 <= de1;
cursor1 <= cursor0;
cursor2 <= cursor1;
end if;
end if;
end process;
end architecture;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- --- ---------------------------- ---- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- --- ---------------------------- ---- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTS _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- --- ---------------------------- ---- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- --- ---------------------------- ---- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTS _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.All;
entity HybridVelocityCounter is port (
clk : in std_logic;
encoder : in std_logic;
speed : out real;
measurementType: out std_logic);
end HybridVelocityCounter;
architecture velocity of HybridVelocityCounter is
type measurementTypes is (HighSpeed, LowSpeed);
constant clockFrequency : integer := 25; -- frequency in nanoseconds
constant samplingPeriod: integer := 1500; -- sampling period in nanoseconds
constant minimumHighSpeedCounter : integer := 5;
constant maximumLowSpeed : real := 0.005;
signal currentMeasurementType : measurementTypes := HighSpeed;
begin
speedMeasurement: process(clk)
variable pulseCounter : integer := 0;
variable timeChange : integer := 0;
variable counted : std_logic := '0';
variable timeReal : real;
variable currentSpeed : real;
variable measuringTime : std_logic;
begin
if rising_edge(clk) then
if currentMeasurementType = HighSpeed then
if encoder = '1' then
if counted = '0' then
pulseCounter := pulseCounter + 1;
counted := '1';
end if;
elsif counted = '1' then
counted := '0';
end if;
timeChange := timeChange + 2 * clockFrequency;
if timeChange >= samplingPeriod then
--we switch to a low-velocity mode if the pulse counter
--is below a predefined threshold
if pulseCounter < minimumHighSpeedCounter then
currentMeasurementType <= LowSpeed;
measurementType <= '1';
else
measurementType <= '0';
end if;
timeReal := real(samplingPeriod);
speed <= real(pulseCounter) / timeReal;
-- we reset the variables to allow for new measurements
pulseCounter := 0;
timeChange := 0;
counted := '0';
end if;
else
if encoder = '1' then
if measuringTime = '1' then
timeChange := timeChange + 2 * clockFrequency;
if counted = '0' then
timeReal := real(timeChange);
currentSpeed := 1.0 / timeReal;
if currentSpeed > maximumLowSpeed then
currentMeasurementType <= HighSpeed;
measurementType <= '0';
else
measurementType <= '1';
end if;
speed <= currentSpeed;
-- we reset the variables to allow for new measurements
timeChange := 0;
counted := '0';
measuringTime := '0';
end if;
else
counted := '1';
measuringTime := '1';
end if;
else
if measuringTime = '1' then
timeChange := timeChange + 2 * clockFrequency;
end if;
if counted = '1' then
counted := '0';
end if;
end if;
end if;
end if;
end process;
end velocity;
|
-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
end package sys_conf;
|
-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
end package sys_conf;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1665.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01665ent IS
port (A,B : inout bit);
END c09s01b00x00p05n01i01665ent;
ARCHITECTURE c09s01b00x00p05n01i01665arch OF c09s01b00x00p05n01i01665ent IS
BEGIN
BL: block
begin
end block BL; -- No_failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p05n01i01665"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01665arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1665.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01665ent IS
port (A,B : inout bit);
END c09s01b00x00p05n01i01665ent;
ARCHITECTURE c09s01b00x00p05n01i01665arch OF c09s01b00x00p05n01i01665ent IS
BEGIN
BL: block
begin
end block BL; -- No_failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p05n01i01665"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01665arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1665.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01665ent IS
port (A,B : inout bit);
END c09s01b00x00p05n01i01665ent;
ARCHITECTURE c09s01b00x00p05n01i01665arch OF c09s01b00x00p05n01i01665ent IS
BEGIN
BL: block
begin
end block BL; -- No_failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p05n01i01665"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01665arch;
|
-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon_sb - sim
-- Description: simbus wrapper for rbus monitor (for tb's)
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- use sbcntl_sbf_cpmon def
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
entity rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon_sb;
architecture sim of rb_mon_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
RBMON : rb_mon
generic map (
DBASE => DBASE)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end sim;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library std;
use std.standard.all;
package altera_standard_functions is
function maximum (L, R: integer) return integer;
function minimum (L, R: integer) return integer;
end altera_standard_functions;
package body altera_standard_functions is
function maximum (L, R: integer) return integer is
begin
if L > R then
return L;
else
return R;
end if;
end maximum;
function minimum (L, R: integer) return integer is
begin
if L > R then
return R;
else
return L;
end if;
end minimum;
end altera_standard_functions;
|
-- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00620: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00620
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00620(ARCH00620)
-- ENT00620_Test_Bench(ARCH00620_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00620 is
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00620 ;
--
--
architecture ARCH00620 of ENT00620 is
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
procedure P1
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_arr3_vector : in st_arr3_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr3_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <= transport
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_arr3_vector ,
st_arr3_vector_select ,
s_st_arr3_vector_savt ,
chk_st_arr3_vector ,
s_st_arr3_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <= transport
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ;
--
end ARCH00620 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00620_Test_Bench is
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00620_Test_Bench ;
--
--
architecture ARCH00620_Test_Bench of ENT00620_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00620 ( ARCH00620 ) ;
begin
CIS1 : UUT
port map (
s_st_arr2_vector
, s_st_arr3_vector
)
;
end block L1 ;
end ARCH00620_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1339.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01339ent IS
END c08s04b01x00p04n01i01339ent;
ARCHITECTURE c08s04b01x00p04n01i01339arch OF c08s04b01x00p04n01i01339ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 us;
wait for 10 us;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01339"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01339 - Predefined TIME unit us as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01339arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1339.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01339ent IS
END c08s04b01x00p04n01i01339ent;
ARCHITECTURE c08s04b01x00p04n01i01339arch OF c08s04b01x00p04n01i01339ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 us;
wait for 10 us;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01339"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01339 - Predefined TIME unit us as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01339arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1339.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01339ent IS
END c08s04b01x00p04n01i01339ent;
ARCHITECTURE c08s04b01x00p04n01i01339arch OF c08s04b01x00p04n01i01339ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 us;
wait for 10 us;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01339"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01339 - Predefined TIME unit us as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01339arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
OUTPUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture control of ROUTE is
--******************************************PROTOTYPE FOR REFERENCE************************************************
-- RAM 0 -----> ram_0_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 1 -----> ram_1_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 2 -----> ram_2_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 3 -----> ram_3_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 4 -----> ram_4_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 5 -----> ram_5_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 6 -----> ram_6_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 7 -----> ram_7_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
component ROUTE_SIGNAL
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal select_a : std_logic_vector (15 downto 0);
signal select_b : std_logic_vector (15 downto 0);
signal select_c : std_logic_vector (15 downto 0);
signal select_0 : std_logic_vector (15 downto 0);
signal select_1 : std_logic_vector (15 downto 0);
signal select_a_1hot : std_logic_vector (15 downto 0);
signal select_b_1hot : std_logic_vector (15 downto 0);
signal select_c_1hot : std_logic_vector (15 downto 0);
signal select_0_1hot : std_logic_vector (15 downto 0);
signal select_1_1hot : std_logic_vector (15 downto 0);
begin
select_a <= ram_0_sel_vector(9 downto 8) & ram_1_sel_vector(9 downto 8) &
ram_2_sel_vector(9 downto 8) & ram_3_sel_vector(9 downto 8) &
ram_4_sel_vector(9 downto 8) & ram_5_sel_vector(9 downto 8) &
ram_6_sel_vector(9 downto 8) & ram_7_sel_vector(9 downto 8);
select_b <= ram_0_sel_vector(7 downto 6) & ram_1_sel_vector(7 downto 6) &
ram_2_sel_vector(7 downto 6) & ram_3_sel_vector(7 downto 6) &
ram_4_sel_vector(7 downto 6) & ram_5_sel_vector(7 downto 6) &
ram_6_sel_vector(7 downto 6) & ram_7_sel_vector(7 downto 6);
select_c <= ram_0_sel_vector(5 downto 4) & ram_1_sel_vector(5 downto 4) &
ram_2_sel_vector(5 downto 4) & ram_3_sel_vector(5 downto 4) &
ram_4_sel_vector(5 downto 4) & ram_5_sel_vector(5 downto 4) &
ram_6_sel_vector(5 downto 4) & ram_7_sel_vector(5 downto 4);
select_0 <= ram_0_sel_vector(3 downto 2) & ram_1_sel_vector(3 downto 2) &
ram_2_sel_vector(3 downto 2) & ram_3_sel_vector(3 downto 2) &
ram_4_sel_vector(3 downto 2) & ram_5_sel_vector(3 downto 2) &
ram_6_sel_vector(3 downto 2) & ram_7_sel_vector(3 downto 2);
select_1 <= ram_0_sel_vector(1 downto 0) & ram_1_sel_vector(1 downto 0) &
ram_2_sel_vector(1 downto 0) & ram_3_sel_vector(1 downto 0) &
ram_4_sel_vector(1 downto 0) & ram_5_sel_vector(1 downto 0) &
ram_6_sel_vector(1 downto 0) & ram_7_sel_vector(1 downto 0);
select_a_1hot <= select_a(15) & (not(select_a(15) and select_a(14)) and select_a(14)) &
select_a(13) & (not(select_a(13) and select_a(12)) and select_a(12)) &
select_a(11) & (not(select_a(11) and select_a(10)) and select_a(10)) &
select_a(9) & (not(select_a(9) and select_a(8)) and select_a(8)) &
select_a(7) & (not(select_a(7) and select_a(6)) and select_a(6)) &
select_a(5) & (not(select_a(5) and select_a(4)) and select_a(4)) &
select_a(3) & (not(select_a(3) and select_a(2)) and select_a(2)) &
select_a(1) & (not(select_a(1) and select_a(0)) and select_a(0));
select_b_1hot <= select_b(15) & (not(select_b(15) and select_b(14)) and select_b(14)) &
select_b(13) & (not(select_b(13) and select_b(12)) and select_b(12)) &
select_b(11) & (not(select_b(11) and select_b(10)) and select_b(10)) &
select_b(9) & (not(select_b(9) and select_b(8)) and select_b(8)) &
select_b(7) & (not(select_b(7) and select_b(6)) and select_b(6)) &
select_b(5) & (not(select_b(5) and select_b(4)) and select_b(4)) &
select_b(3) & (not(select_b(3) and select_b(2)) and select_b(2)) &
select_b(1) & (not(select_b(1) and select_b(0)) and select_b(0));
select_c_1hot <= select_c(15) & (not(select_c(15) and select_c(14)) and select_c(14)) &
select_c(13) & (not(select_c(13) and select_c(12)) and select_c(12)) &
select_c(11) & (not(select_c(11) and select_c(10)) and select_c(10)) &
select_c(9) & (not(select_c(9) and select_c(8)) and select_c(8)) &
select_c(7) & (not(select_c(7) and select_c(6)) and select_c(6)) &
select_c(5) & (not(select_c(5) and select_c(4)) and select_c(4)) &
select_c(3) & (not(select_c(3) and select_c(2)) and select_c(2)) &
select_c(1) & (not(select_c(1) and select_c(0)) and select_c(0));
select_0_1hot <= select_0(15) & (not(select_0(15) and select_0(14)) and select_0(14)) &
select_0(13) & (not(select_0(13) and select_0(12)) and select_0(12)) &
select_0(11) & (not(select_0(11) and select_0(10)) and select_0(10)) &
select_0(9) & (not(select_0(9) and select_0(8)) and select_0(8)) &
select_0(7) & (not(select_0(7) and select_0(6)) and select_0(6)) &
select_0(5) & (not(select_0(5) and select_0(4)) and select_0(4)) &
select_0(3) & (not(select_0(3) and select_0(2)) and select_0(2)) &
select_0(1) & (not(select_0(1) and select_0(0)) and select_0(0));
select_1_1hot <= select_1(15) & (not(select_1(15) and select_1(14)) and select_1(14)) &
select_1(13) & (not(select_1(13) and select_1(12)) and select_1(12)) &
select_1(11) & (not(select_1(11) and select_1(10)) and select_1(10)) &
select_1(9) & (not(select_1(9) and select_1(8)) and select_1(8)) &
select_1(7) & (not(select_1(7) and select_1(6)) and select_1(6)) &
select_1(5) & (not(select_1(5) and select_1(4)) and select_1(4)) &
select_1(3) & (not(select_1(3) and select_1(2)) and select_1(2)) &
select_1(1) & (not(select_1(1) and select_1(0)) and select_1(0));
route_a : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_a_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_A
);
route_b : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_b_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_B
);
route_c : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_c_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_C
);
route_0 : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_0_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_0
);
route_1 : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_1_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_1
);
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
OUTPUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture control of ROUTE is
--******************************************PROTOTYPE FOR REFERENCE************************************************
-- RAM 0 -----> ram_0_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 1 -----> ram_1_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 2 -----> ram_2_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 3 -----> ram_3_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 4 -----> ram_4_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 5 -----> ram_5_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 6 -----> ram_6_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 7 -----> ram_7_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
component ROUTE_SIGNAL
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal select_a : std_logic_vector (15 downto 0);
signal select_b : std_logic_vector (15 downto 0);
signal select_c : std_logic_vector (15 downto 0);
signal select_0 : std_logic_vector (15 downto 0);
signal select_1 : std_logic_vector (15 downto 0);
signal select_a_1hot : std_logic_vector (15 downto 0);
signal select_b_1hot : std_logic_vector (15 downto 0);
signal select_c_1hot : std_logic_vector (15 downto 0);
signal select_0_1hot : std_logic_vector (15 downto 0);
signal select_1_1hot : std_logic_vector (15 downto 0);
begin
select_a <= ram_0_sel_vector(9 downto 8) & ram_1_sel_vector(9 downto 8) &
ram_2_sel_vector(9 downto 8) & ram_3_sel_vector(9 downto 8) &
ram_4_sel_vector(9 downto 8) & ram_5_sel_vector(9 downto 8) &
ram_6_sel_vector(9 downto 8) & ram_7_sel_vector(9 downto 8);
select_b <= ram_0_sel_vector(7 downto 6) & ram_1_sel_vector(7 downto 6) &
ram_2_sel_vector(7 downto 6) & ram_3_sel_vector(7 downto 6) &
ram_4_sel_vector(7 downto 6) & ram_5_sel_vector(7 downto 6) &
ram_6_sel_vector(7 downto 6) & ram_7_sel_vector(7 downto 6);
select_c <= ram_0_sel_vector(5 downto 4) & ram_1_sel_vector(5 downto 4) &
ram_2_sel_vector(5 downto 4) & ram_3_sel_vector(5 downto 4) &
ram_4_sel_vector(5 downto 4) & ram_5_sel_vector(5 downto 4) &
ram_6_sel_vector(5 downto 4) & ram_7_sel_vector(5 downto 4);
select_0 <= ram_0_sel_vector(3 downto 2) & ram_1_sel_vector(3 downto 2) &
ram_2_sel_vector(3 downto 2) & ram_3_sel_vector(3 downto 2) &
ram_4_sel_vector(3 downto 2) & ram_5_sel_vector(3 downto 2) &
ram_6_sel_vector(3 downto 2) & ram_7_sel_vector(3 downto 2);
select_1 <= ram_0_sel_vector(1 downto 0) & ram_1_sel_vector(1 downto 0) &
ram_2_sel_vector(1 downto 0) & ram_3_sel_vector(1 downto 0) &
ram_4_sel_vector(1 downto 0) & ram_5_sel_vector(1 downto 0) &
ram_6_sel_vector(1 downto 0) & ram_7_sel_vector(1 downto 0);
select_a_1hot <= select_a(15) & (not(select_a(15) and select_a(14)) and select_a(14)) &
select_a(13) & (not(select_a(13) and select_a(12)) and select_a(12)) &
select_a(11) & (not(select_a(11) and select_a(10)) and select_a(10)) &
select_a(9) & (not(select_a(9) and select_a(8)) and select_a(8)) &
select_a(7) & (not(select_a(7) and select_a(6)) and select_a(6)) &
select_a(5) & (not(select_a(5) and select_a(4)) and select_a(4)) &
select_a(3) & (not(select_a(3) and select_a(2)) and select_a(2)) &
select_a(1) & (not(select_a(1) and select_a(0)) and select_a(0));
select_b_1hot <= select_b(15) & (not(select_b(15) and select_b(14)) and select_b(14)) &
select_b(13) & (not(select_b(13) and select_b(12)) and select_b(12)) &
select_b(11) & (not(select_b(11) and select_b(10)) and select_b(10)) &
select_b(9) & (not(select_b(9) and select_b(8)) and select_b(8)) &
select_b(7) & (not(select_b(7) and select_b(6)) and select_b(6)) &
select_b(5) & (not(select_b(5) and select_b(4)) and select_b(4)) &
select_b(3) & (not(select_b(3) and select_b(2)) and select_b(2)) &
select_b(1) & (not(select_b(1) and select_b(0)) and select_b(0));
select_c_1hot <= select_c(15) & (not(select_c(15) and select_c(14)) and select_c(14)) &
select_c(13) & (not(select_c(13) and select_c(12)) and select_c(12)) &
select_c(11) & (not(select_c(11) and select_c(10)) and select_c(10)) &
select_c(9) & (not(select_c(9) and select_c(8)) and select_c(8)) &
select_c(7) & (not(select_c(7) and select_c(6)) and select_c(6)) &
select_c(5) & (not(select_c(5) and select_c(4)) and select_c(4)) &
select_c(3) & (not(select_c(3) and select_c(2)) and select_c(2)) &
select_c(1) & (not(select_c(1) and select_c(0)) and select_c(0));
select_0_1hot <= select_0(15) & (not(select_0(15) and select_0(14)) and select_0(14)) &
select_0(13) & (not(select_0(13) and select_0(12)) and select_0(12)) &
select_0(11) & (not(select_0(11) and select_0(10)) and select_0(10)) &
select_0(9) & (not(select_0(9) and select_0(8)) and select_0(8)) &
select_0(7) & (not(select_0(7) and select_0(6)) and select_0(6)) &
select_0(5) & (not(select_0(5) and select_0(4)) and select_0(4)) &
select_0(3) & (not(select_0(3) and select_0(2)) and select_0(2)) &
select_0(1) & (not(select_0(1) and select_0(0)) and select_0(0));
select_1_1hot <= select_1(15) & (not(select_1(15) and select_1(14)) and select_1(14)) &
select_1(13) & (not(select_1(13) and select_1(12)) and select_1(12)) &
select_1(11) & (not(select_1(11) and select_1(10)) and select_1(10)) &
select_1(9) & (not(select_1(9) and select_1(8)) and select_1(8)) &
select_1(7) & (not(select_1(7) and select_1(6)) and select_1(6)) &
select_1(5) & (not(select_1(5) and select_1(4)) and select_1(4)) &
select_1(3) & (not(select_1(3) and select_1(2)) and select_1(2)) &
select_1(1) & (not(select_1(1) and select_1(0)) and select_1(0));
route_a : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_a_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_A
);
route_b : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_b_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_B
);
route_c : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_c_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_C
);
route_0 : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_0_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_0
);
route_1 : ROUTE_SIGNAL PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_1_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_1
);
end; |
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`protect end_protected
|
--
-- Copyright (c) ARMadeus Project 2009
--
-- Wishbone component that drive sn74hc594 8 bits shift register
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : industrial_output.vhd
-- Created on : 08/06/2009
-- Author : Fabien Marteau <fabien.marteau@armadeus.com>
--
-- TODO: adding busy bit on data register to inform operating system
-- that component is sending a value -> done but not tested
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity industrial_output is
---------------------------------------------------------------------------
generic(
id : natural := 1; -- identification register value
wb_size : natural := 16; -- Data port size for wishbone
serial_speed : natural := 1000; -- serial speed in kHz (min : 9, max 133000)
clk_freq : natural := 133000 -- fpga clock speed in kHz
);
port
(
-- Syscon signals
reset : in std_logic ; -- reset
clk : in std_logic ; -- general clock
-- Wishbone signals
wbs_add : in std_logic ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- sn74hc594 signals
reset_n : out std_logic;
rclk : out std_logic;
srclk : out std_logic;
ser : out std_logic;
qh : in std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture industrial_output_1 of industrial_output is
---------------------------------------------------------------------------
-- usefull constant
constant ZERO : std_logic_vector(15 downto 0) := x"0000";
-- state machine
type state_type is (out_void, out_init, out_write_value, out_write_pulse, out_out);
signal state_reg : state_type;
signal next_state: state_type;
-- registers addresses
constant CTRL_DATA : std_logic := '0';
constant ID_ADDR : std_logic := '1';
-- registers
signal data : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal ser_reg : std_logic ;
signal spi_count_reg: natural range 0 to 10;
signal busy_reg : std_logic ;
signal busy_next : std_logic ;
signal data_next : std_logic_vector(7 downto 0);
signal ser_next: std_logic ;
-- spi clock
signal spi_clk : std_logic ;
signal spi_clk_rise : std_logic ;
signal spi_clk_fall : std_logic ;
-- state machine signals
signal data_wrote : std_logic ;
--
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal enable_spi_clk : std_logic ;
begin
wbs_ack <= write_ack or read_ack;
-- read process
read_p : process (clk, reset)
begin
if reset = '1' then
wbs_readdata <= ( others => '0');
elsif rising_edge(clk) then
if (wbs_strobe and (not wbs_write) and wbs_cycle) = '1' then
read_ack <= '1';
case wbs_add is
when CTRL_DATA =>
wbs_readdata <= ZERO(15 downto 9)&busy_reg&data;
when ID_ADDR =>
wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
when others =>
wbs_readdata <= (others => '0');
end case;
else
read_ack <= '0';
wbs_readdata <= (others => '0');
end if;
end if;
end process read_p;
-- write process
write_p : process (clk, reset)
variable wrote_v : std_logic;
begin
if reset = '1' then
data <= (others => '0');
wrote_v := '0';
write_ack <= '0';
elsif rising_edge(clk) then
write_ack <= '0';
data_wrote <= '0';
if (wbs_strobe and wbs_write and wbs_cycle) = '1' then
write_ack <= '1';
data <= wbs_writedata(7 downto 0);
wrote_v := '1';
elsif wrote_v = '1' then
data_wrote <= '1';
wrote_v := '0';
end if;
end if;
end process write_p;
-- clock generator
clock_divider : process (clk, reset)
variable count : natural range 0 to (2**14)-1;
begin
if reset = '1' then
count := 0;
spi_clk <= '0';
spi_clk_rise <= '0';
spi_clk_fall <= '0';
spi_count_reg <= 0;
elsif rising_edge(clk) then
if enable_spi_clk = '1' then
if (count <= (clk_freq / (2*serial_speed))) then
count := count + 1;
spi_clk <= spi_clk;
spi_clk_rise <= '0';
spi_clk_fall <= '0';
else
count := 0;
spi_clk <= not spi_clk;
if spi_clk = '0' then
spi_count_reg <= spi_count_reg + 1;
spi_clk_rise <= '1';
spi_clk_fall <= '0';
else
spi_clk_rise <= '0';
spi_clk_fall <= '1';
end if;
end if;
else
spi_count_reg <= 0;
spi_clk <= '0';
spi_clk_fall <= '0';
spi_clk_rise <= '0';
end if;
end if;
end process clock_divider;
--state register
spi_state_register_p : process (clk, reset)
begin
if reset = '1' then
state_reg <= out_void;
data_reg <= (others => '0');
ser_reg <= '0';
busy_reg <= '0';
elsif rising_edge(clk) then
busy_reg <= busy_next;
state_reg <= next_state;
ser_reg <= ser_next;
data_reg <= data_next;
end if;
end process spi_state_register_p;
-- next-state logic
nstate_p : process( state_reg, spi_clk_fall, spi_clk_rise,
data_wrote,spi_count_reg )
begin
next_state <= state_reg;
case state_reg is
when out_void =>
if data_wrote = '1' then
next_state <= out_init;
end if;
when out_init =>
if spi_clk_fall = '1' then
next_state <= out_write_value;
end if;
when out_write_value =>
if spi_clk_rise = '1' then
next_state <= out_write_pulse;
end if;
when out_write_pulse =>
if (spi_count_reg < 9) and spi_clk_fall = '1' then
next_state <= out_write_value;
elsif (spi_count_reg >= 9) then
next_state <= out_out;
end if;
when out_out =>
if spi_count_reg < 10 then
next_state <= out_out;
else
next_state <= out_void;
end if;
when others =>
next_state <= out_void;
end case;
end process nstate_p;
-- output logic
output_p : process (state_reg, spi_clk, data_reg, ser_reg,
spi_count_reg,data,spi_clk_rise,qh)
begin
ser_next <= ser_reg;
data_next <= data_reg;
case state_reg is
when out_void =>
rclk <= '0';
srclk <= '1';
ser_next <= '0';
enable_spi_clk <= '0';
data_next <= data;
busy_next <= '0';
when out_init =>
rclk <= '0';
srclk <= '1';
ser_next <= '0';
enable_spi_clk <= '1';
busy_next <= '1';
when out_write_value =>
rclk <= '0';
srclk <= spi_clk;
ser_next <= data_reg(7);
if spi_clk_rise = '1' then
data_next <= data_reg(6 downto 0)&qh;
end if;
enable_spi_clk <= '1';
busy_next <= '1';
when out_write_pulse =>
rclk <= '0';
srclk <= spi_clk;
ser_next <= ser_reg;
data_next <= data_reg;
enable_spi_clk <= '1';
busy_next <= '1';
when out_out =>
rclk <= '1'; -- refresh output
srclk <= '1';
ser_next <= ser_reg;
data_next <= data_reg;
enable_spi_clk <= '1';
busy_next <= '1';
when others =>
rclk <= '0';
srclk <= '1';
ser_next <= '0';
enable_spi_clk <= '0';
busy_next <= '0';
end case;
end process output_p;
ser <= ser_reg;
reset_n <= '1';
end architecture industrial_output_1;
|
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core Module for position calculation with de-cross, amplitude compensation
-- and delay tuning.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-07-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- BPM cores
use work.bpm_cores_pkg.all;
-- Position Calc
use work.position_calc_core_pkg.all;
entity xwb_position_calc_core is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
g_monit_decim_width : natural := 32;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end xwb_position_calc_core;
architecture rtl of xwb_position_calc_core is
begin
cmp_wb_position_calc_core : wb_position_calc_core
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_with_extra_wb_reg => g_with_extra_wb_reg,
g_rffe_version => g_rffe_version,
-- selection of position_calc stages
g_with_downconv => g_with_downconv,
-- input sizes
g_input_width => g_input_width,
g_mixed_width => g_mixed_width,
g_adc_ratio => g_adc_ratio,
-- mixer
g_dds_width => g_dds_width,
g_dds_points => g_dds_points,
g_sin_file => g_sin_file,
g_cos_file => g_cos_file,
-- CIC setup
g_tbt_cic_delay => g_tbt_cic_delay,
g_tbt_cic_stages => g_tbt_cic_stages,
g_tbt_ratio => g_tbt_ratio,
g_tbt_decim_width => g_tbt_decim_width,
g_fofb_cic_delay => g_fofb_cic_delay,
g_fofb_cic_stages => g_fofb_cic_stages,
g_fofb_ratio => g_fofb_ratio,
g_fofb_decim_width => g_fofb_decim_width,
g_monit1_cic_delay => g_monit1_cic_delay,
g_monit1_cic_stages => g_monit1_cic_stages,
g_monit1_ratio => g_monit1_ratio,
g_monit1_cic_ratio => g_monit1_cic_ratio,
g_monit2_cic_delay => g_monit2_cic_delay,
g_monit2_cic_stages => g_monit2_cic_stages,
g_monit2_ratio => g_monit2_ratio,
g_monit2_cic_ratio => g_monit2_cic_ratio,
g_monit_decim_width => g_monit_decim_width,
-- Cordic setup
g_tbt_cordic_stages => g_tbt_cordic_stages,
g_tbt_cordic_iter_per_clk => g_tbt_cordic_iter_per_clk,
g_tbt_cordic_ratio => g_tbt_cordic_ratio,
g_fofb_cordic_stages => g_fofb_cordic_stages,
g_fofb_cordic_iter_per_clk => g_fofb_cordic_iter_per_clk,
g_fofb_cordic_ratio => g_fofb_cordic_ratio,
-- width of K constants
g_k_width => g_k_width,
--width for IQ output
g_IQ_width => g_IQ_width,
-- Swap/de-swap setup
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width
)
port map
(
rst_n_i => rst_n_i,
clk_i => clk_i,
fs_rst_n_i => fs_rst_n_i,
fs_rst2x_n_i => fs_rst2x_n_i,
fs_clk_i => fs_clk_i, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i => fs_clk2x_i, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => adc_ch0_i,
adc_ch1_i => adc_ch1_i,
adc_ch2_i => adc_ch2_i,
adc_ch3_i => adc_ch3_i,
adc_valid_i => adc_valid_i,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o => adc_ch0_swap_o,
adc_ch1_swap_o => adc_ch1_swap_o,
adc_ch2_swap_o => adc_ch2_swap_o,
adc_ch3_swap_o => adc_ch3_swap_o,
adc_tag_o => adc_tag_o,
adc_swap_valid_o => adc_swap_valid_o,
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o => mix_ch0_i_o,
mix_ch0_q_o => mix_ch0_q_o,
mix_ch1_i_o => mix_ch1_i_o,
mix_ch1_q_o => mix_ch1_q_o,
mix_ch2_i_o => mix_ch2_i_o,
mix_ch2_q_o => mix_ch2_q_o,
mix_ch3_i_o => mix_ch3_i_o,
mix_ch3_q_o => mix_ch3_q_o,
mix_valid_o => mix_valid_o,
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o,
tbt_decim_valid_o => tbt_decim_valid_o,
tbt_amp_ch0_o => tbt_amp_ch0_o,
tbt_amp_ch1_o => tbt_amp_ch1_o,
tbt_amp_ch2_o => tbt_amp_ch2_o,
tbt_amp_ch3_o => tbt_amp_ch3_o,
tbt_amp_valid_o => tbt_amp_valid_o,
tbt_pha_ch0_o => tbt_pha_ch0_o,
tbt_pha_ch1_o => tbt_pha_ch1_o,
tbt_pha_ch2_o => tbt_pha_ch2_o,
tbt_pha_ch3_o => tbt_pha_ch3_o,
tbt_pha_valid_o => tbt_pha_valid_o,
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o,
fofb_decim_valid_o => fofb_decim_valid_o,
fofb_amp_ch0_o => fofb_amp_ch0_o,
fofb_amp_ch1_o => fofb_amp_ch1_o,
fofb_amp_ch2_o => fofb_amp_ch2_o,
fofb_amp_ch3_o => fofb_amp_ch3_o,
fofb_amp_valid_o => fofb_amp_valid_o,
fofb_pha_ch0_o => fofb_pha_ch0_o,
fofb_pha_ch1_o => fofb_pha_ch1_o,
fofb_pha_ch2_o => fofb_pha_ch2_o,
fofb_pha_ch3_o => fofb_pha_ch3_o,
fofb_pha_valid_o => fofb_pha_valid_o,
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o => monit1_amp_ch0_o,
monit1_amp_ch1_o => monit1_amp_ch1_o,
monit1_amp_ch2_o => monit1_amp_ch2_o,
monit1_amp_ch3_o => monit1_amp_ch3_o,
monit1_amp_valid_o => monit1_amp_valid_o,
monit_amp_ch0_o => monit_amp_ch0_o,
monit_amp_ch1_o => monit_amp_ch1_o,
monit_amp_ch2_o => monit_amp_ch2_o,
monit_amp_ch3_o => monit_amp_ch3_o,
monit_amp_valid_o => monit_amp_valid_o,
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o => tbt_pos_x_o,
tbt_pos_y_o => tbt_pos_y_o,
tbt_pos_q_o => tbt_pos_q_o,
tbt_pos_sum_o => tbt_pos_sum_o,
tbt_pos_valid_o => tbt_pos_valid_o,
fofb_pos_x_o => fofb_pos_x_o,
fofb_pos_y_o => fofb_pos_y_o,
fofb_pos_q_o => fofb_pos_q_o,
fofb_pos_sum_o => fofb_pos_sum_o,
fofb_pos_valid_o => fofb_pos_valid_o,
monit1_pos_x_o => monit1_pos_x_o,
monit1_pos_y_o => monit1_pos_y_o,
monit1_pos_q_o => monit1_pos_q_o,
monit1_pos_sum_o => monit1_pos_sum_o,
monit1_pos_valid_o => monit1_pos_valid_o,
monit_pos_x_o => monit_pos_x_o,
monit_pos_y_o => monit_pos_y_o,
monit_pos_q_o => monit_pos_q_o,
monit_pos_sum_o => monit_pos_sum_o,
monit_pos_valid_o => monit_pos_valid_o,
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o => rffe_swclk_o,
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i => sync_trig_slow_i,
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o => dbg_cur_address_o,
dbg_adc_ch0_cond_o => dbg_adc_ch0_cond_o,
dbg_adc_ch1_cond_o => dbg_adc_ch1_cond_o,
dbg_adc_ch2_cond_o => dbg_adc_ch2_cond_o,
dbg_adc_ch3_cond_o => dbg_adc_ch3_cond_o
);
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; |
------------------------------------------------------------------------------
---- ----
---- gmZPU core
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
---- medium version, the PHI I/O basic layout, a program BRAM and a. ----
---- wishbone controller. ----
---- ----
---- To Do: ----
---- - Add interrupt controller. ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: gmZPU ----
---- File name: gmzpu.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: gmzpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
library gmzpu;
use gmzpu.zwishbone.all;
use gmzpu.soc.all;
library zetaio;
use zetaio.pic.all;
use zetaio.tim.all;
-- RAM declaration
library work;
use work.zpu_memory.all;
entity gmZPU is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='X'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=9600; -- RS232 baudrate
ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
interrupt_i: in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end entity gmZPU;
architecture Structural of gmZPU is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- 0 = memory, 1= I/O
constant ZW_BIT : integer:=ADDR_W-2; -- Address bit to determine zwishbone from phiIO
-- 0 = phiIO, 1 = zwishbone
constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
-- zwishbone
constant CS_WIDTH : natural:=4;
-- devices on the bus
constant WB_CS_PIC : natural:=0;
-- PIC interrupt mapping
--constant PIC_INT_EXT : natural:=0;
--constant PIC_INT_ZWC : natural:=1;
--constant PIC_INT_UNUSED : natural:=2;
-- I/O & memory (ZPU)
signal mem_busy : std_logic;
signal mem_read : unsigned(WORD_SIZE-1 downto 0);
signal mem_write : unsigned(WORD_SIZE-1 downto 0);
signal mem_addr : unsigned(ADDR_W-1 downto 0);
signal mem_we : std_logic;
signal mem_re : std_logic;
-- Memory (SinglePort_RAM)
signal ram_busy : std_logic;
signal ram_read : unsigned(WORD_SIZE-1 downto 0);
signal ram_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram_we : std_logic;
signal ram_re : std_logic;
signal ram_ready_r : std_logic:='0';
-- I/O (ZPU_IO)
signal phi_io_busy : std_logic;
signal phi_io_re : std_logic;
signal phi_io_we : std_logic;
signal phi_io_read : unsigned(WORD_SIZE-1 downto 0);
signal phi_io_ready : std_logic;
signal phi_io_reading_r : std_logic:='0';
signal phi_io_addr : unsigned(2 downto 0);
-- I/O (zwishbone)
signal zw_busy : std_logic;
signal zw_ready : std_logic;
signal zw_addr : unsigned(ADDR_W-3 downto 0);
signal zw_re : std_logic;
signal zw_we : std_logic;
signal zw_dat_i : unsigned(WORD_SIZE-1 downto 0);
signal zw_dat_o : unsigned(WORD_SIZE-1 downto 0);
--
signal wb_dat_i : unsigned(WORD_SIZE-1 downto 0);
signal wb_dat_o : unsigned(WORD_SIZE-1 downto 0);
signal wb_tgd_i : unsigned(WORD_SIZE-1 downto 0);
signal wb_tgd_o : unsigned(WORD_SIZE-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_adr_o : unsigned(ADDR_W-4-CS_WIDTH downto 0);
signal wb_cyc_o : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_lock_o : std_logic;
signal wb_rty_i : std_logic;
signal wb_sel_o : std_logic_vector(WORD_SIZE-1 downto 0);
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_tga_o : unsigned(ADDR_W-4-CS_WIDTH downto 0);
signal wb_tgc_o : unsigned(WORD_SIZE-1 downto 0); -- size correct?
signal wb_we_o : std_logic;
-- interrupt
signal irq_r : std_logic;
begin
memory: SinglePortRAM
generic map(
WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
port map(
clk_i => clk_i,
we_i => ram_we, re_i => ram_re, addr_i => ram_addr,
write_i => mem_write, read_o => ram_read, busy_o => ram_busy);
ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS);
ram_we <= mem_we and not(mem_addr(IO_BIT));
ram_re <= mem_re and not(mem_addr(IO_BIT));
-- I/O: Phi layout
io_map: ZPUPhiIO
generic map(
BRDIVISOR => BRDIVISOR,
LOG_FILE => "zpu_med1_io.log"
)
port map(
clk_i => clk_i,
reset_i => rst_i,
busy_o => phi_io_busy,
we_i => phi_io_we,
re_i => phi_io_re,
data_i => mem_write,
data_o => phi_io_read,
addr_i => phi_io_addr,
rs232_rx_i => rs232_rx_i,
rs232_tx_o => rs232_tx_o,
br_clk_i => '1',
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir
);
phi_io_addr <= mem_addr(4 downto 2);
-- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
-- Note: We define the address space as 256 kB, so writing to 0x80A00xx
-- will be as wrting to 0x200xx and hence we decode it as I/O space.
phi_io_we <= mem_we and mem_addr(IO_BIT) and not mem_addr(ZW_BIT);
phi_io_re <= mem_re and mem_addr(IO_BIT) and not mem_addr(ZW_BIT);
phi_io_ready <= (phi_io_reading_r or phi_io_re) and not phi_io_busy;
-- I/O: zwishbone
zwc0: zwc
generic map(
DATA_WIDTH => WORD_SIZE, ADR_WIDTH => ADDR_W-2, CS_WIDTH => 4
)
port map(
clk_i => clk_i, rst_i => rst_i, re_i => zw_re, busy_o => zw_busy, ready_o => zw_ready, irq_o => irq_r,
adr_i => zw_addr, we_i => zw_we, dat_i => zw_dat_i, dat_o => zw_dat_o,
int_i => interrupt_i
);
-- ADDR_W = 18, IO_BIT = 17, ZW_BIT = 16
zw_we <= mem_we and mem_addr(IO_BIT) and mem_addr(ZW_BIT);
zw_re <= mem_re and mem_addr(IO_BIT) and mem_addr(ZW_BIT);
zw_addr <= mem_addr(ADDR_W-3 downto 0);
zw_dat_i <= mem_write;
-- interrupt line connect
--int_r(WORD_SIZE-1 downto PIC_INT_UNUSED) <= (others => '0');
--int_r(PIC_INT_EXT) <= interrupt_i;
--int_r(PIC_INT_ZWC) <= zwc_irq_r;
zpu : ZPUMediumCore
generic map(
WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
D_CARE_VAL => D_CARE_VAL)
port map(
clk_i => clk_i, reset_i => rst_i, interrupt_i => irq_r, enable_i => '1',
break_o => break_o, dbg_o => dbg_o,
-- Memory
mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write,
addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re);
mem_busy <= (phi_io_busy or ram_busy) or zw_busy;
-- Memory reads either come from IO or DRAM. We need to pick the right one.
memory_control:
process (ram_read, ram_ready_r, phi_io_ready, phi_io_read, zw_dat_o, zw_ready)
begin
mem_read <= (others => '0');
if ram_ready_r='1' then
mem_read <= ram_read;
end if;
if phi_io_ready='1' then
mem_read <= phi_io_read;
end if;
if zw_ready='1' then
mem_read <= unsigned(zw_dat_o);
end if;
end process memory_control;
memory_control_sync:
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i='1' then
phi_io_reading_r <= '0';
ram_ready_r <= '0';
else
phi_io_reading_r <= phi_io_busy or phi_io_re;
ram_ready_r <= ram_re;
end if;
end if;
end process memory_control_sync;
end architecture Structural; -- Entity: gmZPU
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2831.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RECORD is
end RECORD;
ENTITY c13s09b00x00p99n01i02831ent IS
END c13s09b00x00p99n01i02831ent;
ARCHITECTURE c13s09b00x00p99n01i02831arch OF c13s09b00x00p99n01i02831ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02831 - Reserved word RECORD can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02831arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2831.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RECORD is
end RECORD;
ENTITY c13s09b00x00p99n01i02831ent IS
END c13s09b00x00p99n01i02831ent;
ARCHITECTURE c13s09b00x00p99n01i02831arch OF c13s09b00x00p99n01i02831ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02831 - Reserved word RECORD can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02831arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2831.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RECORD is
end RECORD;
ENTITY c13s09b00x00p99n01i02831ent IS
END c13s09b00x00p99n01i02831ent;
ARCHITECTURE c13s09b00x00p99n01i02831arch OF c13s09b00x00p99n01i02831ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02831 - Reserved word RECORD can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02831arch;
|
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vidreg_module_64.vhd
--
-- Description: This entity is the top level for the dual register blocks,
-- i.e. video register set and sg register set and provides
-- indication of valid parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module_64.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module_64.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vidreg_module_64 is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Start Address Width
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Register update control --
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
ftch_idle : in std_logic ; --
tailpntr_updated : in std_logic ; --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Register swap control/status --
frame_sync : in std_logic ; --
ftch_complete : in std_logic ; --
ftch_complete_clr : out std_logic ; --
parameter_update : out std_logic ; --
video_prmtrs_valid : out std_logic ; --
prmtr_update_complete : out std_logic ; -- CR605424
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
-- Descriptor data/control from sg interface --
desc_data_wren : in std_logic ; --
--
desc_strtaddress : in std_logic_vector --
(C_ADDR_WIDTH-1 downto 0) ; --
desc_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
desc_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
desc_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
desc_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
--
-- Scatter Gather register Bank --
crnt_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
crnt_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
crnt_stride : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
crnt_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vidreg_module_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vidreg_module_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Control
signal video_parameter_updt : std_logic := '0';
signal video_prmtrs_valid_i : std_logic := '0';
signal ftch_complete_clr_i : std_logic := '0';
signal run_stop_re : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal video_reg_updated : std_logic := '0';
signal video_reg_update : std_logic := '0';
signal update_complete : std_logic := '0';
-- Scatter Gather Side Video Register Bank
--signal vsize_sg : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal hsize_sg : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal stride_sg : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
--signal frmdly_sg : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
signal start_address_vid : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES - 1);
--signal start_address_sg : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- If Scatter Gather engine is included then instantiate SG register block
GEN_SG_REGISTER : if C_INCLUDE_SG = 1 generate
begin
-- Flag for updating video parameters on descriptor fetch
-- Used to enable vsize, hsize, stride, frmdly update on first desc
-- fetchted
REG_UPDATE_VIDEO_PRMTRS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_parameter_updt <= '0';
-- if new tailpointer and sg fetch engine idle or if new start then
-- set flag to capture video parameters
elsif((tailpntr_updated = '1' and ftch_idle = '1') or run_stop_re = '1')then
video_parameter_updt <= '1';
-- clear flag when parameters written to video_register module.
elsif(desc_data_wren = '1')then
video_parameter_updt <= '0';
end if;
end if;
end process REG_UPDATE_VIDEO_PRMTRS;
-- Register run stop to generate rising edge pulse
-- Used to force start address counter reset on shutdown
REG_RUN_STOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP;
run_stop_re <= run_stop and not run_stop_d1;
-- Scatter Gather Start Address Register Block (LUTRAM)
SG_ADDREG_I : entity axi_vdma_v6_2_8.axi_vdma_sgregister
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH ,
C_SELECT_XPM => C_SELECT_XPM ,
C_FAMILY => C_FAMILY
)
port map (
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Update Control
video_reg_update => video_reg_update ,
video_parameter_updt => video_parameter_updt ,
video_parameter_valid => video_prmtrs_valid_i ,
dmasr_halt => dmasr_halt ,
strt_addr_clr => run_stop_re ,
desc_data_wren => desc_data_wren ,
frame_number => frame_number ,
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr_i ,
update_complete => update_complete ,
num_fstore_minus1 => num_fstore_minus1 , -- CR607089
-- Video Start Address / Parameters In from Scatter Gather Engine
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly ,
desc_strtaddress => desc_strtaddress ,
-- Video Start Address / Parameters Out to DMA Controller
crnt_vsize => crnt_vsize ,
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride ,
crnt_frmdly => crnt_frmdly ,
crnt_start_address => crnt_start_address
);
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
--video_reg_update <= '1' when (frame_sync = '1' and ftch_complete = '1')
-- or (video_prmtrs_valid_i = '0' and ftch_complete = '1')
-- else '0';
video_reg_update <= '1' when (frame_sync = '1' and update_complete = '1')
or (video_prmtrs_valid_i = '0' and update_complete = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= update_complete;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
ftch_complete_clr_i <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
--elsif(frame_sync = '1' and ftch_complete = '1')then
elsif(frame_sync = '1' and update_complete = '1')then
video_prmtrs_valid_i <= '1';
ftch_complete_clr_i <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
ftch_complete_clr_i <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- When video register block update drive out parameter update flag
-- for generation of ****_prmtr_update output
parameter_update <= ftch_complete_clr_i;
-- Clear fetch flag in sg interface
ftch_complete_clr <= ftch_complete_clr_i;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
end generate GEN_SG_REGISTER;
-- If Scatter Gather engine is excluded then instantiate register direct block
GEN_REGISTER_DIRECT : if C_INCLUDE_SG = 0 generate
begin
GEN_REGDIRECT_DRES : if C_DYNAMIC_RESOLUTION = 1 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Register Direct Mode - Video Register Block
------- REGDIR_REGBLOCK_I : entity axi_vdma_v6_2_8.axi_vdma_vregister
------- generic map(
------- C_NUM_FSTORES => C_NUM_FSTORES ,
------- C_ADDR_WIDTH => C_ADDR_WIDTH
-------
------- )
------- port map(
------- prmry_aclk => prmry_aclk ,
------- prmry_resetn => prmry_resetn ,
-------
------- -- Video Register Update control
------- video_reg_update => ftch_complete ,
-------
------- dmasr_halt => dmasr_halt ,
-------
------- -- Scatter Gather register Bank
------- vsize_sg => reg_module_vsize ,
------- hsize_sg => reg_module_hsize ,
------- stride_sg => reg_module_stride ,
------- frmdly_sg => reg_module_frmdly ,
------- start_address_sg => reg_module_strt_addr ,
-------
------- -- Video Register Bank
------- vsize_vid => vsize_sg ,
------- hsize_vid => hsize_sg ,
------- stride_vid => stride_sg ,
------- frmdly_vid => frmdly_sg ,
------- start_address_vid => start_address_sg
------- );
-------
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
video_reg_update <= '1' when (frame_sync = '1' and video_reg_updated = '1')
or (video_prmtrs_valid_i = '0' and video_reg_updated = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
-- Video Register Block
VIDREGISTER_I : entity axi_vdma_v6_2_8.axi_vdma_vregister_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Video Register Update control
video_reg_update => video_reg_update ,
dmasr_halt => dmasr_halt ,
-- Scatter Gather register Bank
-- vsize_sg => vsize_sg ,
-- hsize_sg => hsize_sg ,
-- stride_sg => stride_sg ,
-- frmdly_sg => frmdly_sg ,
-- start_address_sg => start_address_sg ,
vsize_sg => reg_module_vsize ,
hsize_sg => reg_module_hsize ,
stride_sg => reg_module_stride ,
frmdly_sg => reg_module_frmdly ,
start_address_sg => reg_module_strt_addr ,
-- Video Register Bank
vsize_vid => crnt_vsize ,
hsize_vid => crnt_hsize ,
stride_vid => crnt_stride ,
frmdly_vid => crnt_frmdly ,
start_address_vid => start_address_vid
);
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_DRES;
GEN_REGDIRECT_NO_DRES : if C_DYNAMIC_RESOLUTION = 0 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
crnt_vsize <= reg_module_vsize;
crnt_hsize <= reg_module_hsize;
crnt_stride <= reg_module_stride;
crnt_frmdly <= reg_module_frmdly;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
start_address_vid(i) <= reg_module_strt_addr(i);
end generate GEN_START_ADDR_REG;
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_NO_DRES;
end generate GEN_REGISTER_DIRECT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vidreg_module_64.vhd
--
-- Description: This entity is the top level for the dual register blocks,
-- i.e. video register set and sg register set and provides
-- indication of valid parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module_64.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module_64.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vidreg_module_64 is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Start Address Width
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Register update control --
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
ftch_idle : in std_logic ; --
tailpntr_updated : in std_logic ; --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Register swap control/status --
frame_sync : in std_logic ; --
ftch_complete : in std_logic ; --
ftch_complete_clr : out std_logic ; --
parameter_update : out std_logic ; --
video_prmtrs_valid : out std_logic ; --
prmtr_update_complete : out std_logic ; -- CR605424
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
-- Descriptor data/control from sg interface --
desc_data_wren : in std_logic ; --
--
desc_strtaddress : in std_logic_vector --
(C_ADDR_WIDTH-1 downto 0) ; --
desc_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
desc_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
desc_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
desc_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
--
-- Scatter Gather register Bank --
crnt_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
crnt_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
crnt_stride : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
crnt_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vidreg_module_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vidreg_module_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Control
signal video_parameter_updt : std_logic := '0';
signal video_prmtrs_valid_i : std_logic := '0';
signal ftch_complete_clr_i : std_logic := '0';
signal run_stop_re : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal video_reg_updated : std_logic := '0';
signal video_reg_update : std_logic := '0';
signal update_complete : std_logic := '0';
-- Scatter Gather Side Video Register Bank
--signal vsize_sg : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal hsize_sg : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal stride_sg : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
--signal frmdly_sg : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
signal start_address_vid : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES - 1);
--signal start_address_sg : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- If Scatter Gather engine is included then instantiate SG register block
GEN_SG_REGISTER : if C_INCLUDE_SG = 1 generate
begin
-- Flag for updating video parameters on descriptor fetch
-- Used to enable vsize, hsize, stride, frmdly update on first desc
-- fetchted
REG_UPDATE_VIDEO_PRMTRS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_parameter_updt <= '0';
-- if new tailpointer and sg fetch engine idle or if new start then
-- set flag to capture video parameters
elsif((tailpntr_updated = '1' and ftch_idle = '1') or run_stop_re = '1')then
video_parameter_updt <= '1';
-- clear flag when parameters written to video_register module.
elsif(desc_data_wren = '1')then
video_parameter_updt <= '0';
end if;
end if;
end process REG_UPDATE_VIDEO_PRMTRS;
-- Register run stop to generate rising edge pulse
-- Used to force start address counter reset on shutdown
REG_RUN_STOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP;
run_stop_re <= run_stop and not run_stop_d1;
-- Scatter Gather Start Address Register Block (LUTRAM)
SG_ADDREG_I : entity axi_vdma_v6_2_8.axi_vdma_sgregister
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH ,
C_SELECT_XPM => C_SELECT_XPM ,
C_FAMILY => C_FAMILY
)
port map (
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Update Control
video_reg_update => video_reg_update ,
video_parameter_updt => video_parameter_updt ,
video_parameter_valid => video_prmtrs_valid_i ,
dmasr_halt => dmasr_halt ,
strt_addr_clr => run_stop_re ,
desc_data_wren => desc_data_wren ,
frame_number => frame_number ,
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr_i ,
update_complete => update_complete ,
num_fstore_minus1 => num_fstore_minus1 , -- CR607089
-- Video Start Address / Parameters In from Scatter Gather Engine
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly ,
desc_strtaddress => desc_strtaddress ,
-- Video Start Address / Parameters Out to DMA Controller
crnt_vsize => crnt_vsize ,
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride ,
crnt_frmdly => crnt_frmdly ,
crnt_start_address => crnt_start_address
);
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
--video_reg_update <= '1' when (frame_sync = '1' and ftch_complete = '1')
-- or (video_prmtrs_valid_i = '0' and ftch_complete = '1')
-- else '0';
video_reg_update <= '1' when (frame_sync = '1' and update_complete = '1')
or (video_prmtrs_valid_i = '0' and update_complete = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= update_complete;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
ftch_complete_clr_i <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
--elsif(frame_sync = '1' and ftch_complete = '1')then
elsif(frame_sync = '1' and update_complete = '1')then
video_prmtrs_valid_i <= '1';
ftch_complete_clr_i <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
ftch_complete_clr_i <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- When video register block update drive out parameter update flag
-- for generation of ****_prmtr_update output
parameter_update <= ftch_complete_clr_i;
-- Clear fetch flag in sg interface
ftch_complete_clr <= ftch_complete_clr_i;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
end generate GEN_SG_REGISTER;
-- If Scatter Gather engine is excluded then instantiate register direct block
GEN_REGISTER_DIRECT : if C_INCLUDE_SG = 0 generate
begin
GEN_REGDIRECT_DRES : if C_DYNAMIC_RESOLUTION = 1 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Register Direct Mode - Video Register Block
------- REGDIR_REGBLOCK_I : entity axi_vdma_v6_2_8.axi_vdma_vregister
------- generic map(
------- C_NUM_FSTORES => C_NUM_FSTORES ,
------- C_ADDR_WIDTH => C_ADDR_WIDTH
-------
------- )
------- port map(
------- prmry_aclk => prmry_aclk ,
------- prmry_resetn => prmry_resetn ,
-------
------- -- Video Register Update control
------- video_reg_update => ftch_complete ,
-------
------- dmasr_halt => dmasr_halt ,
-------
------- -- Scatter Gather register Bank
------- vsize_sg => reg_module_vsize ,
------- hsize_sg => reg_module_hsize ,
------- stride_sg => reg_module_stride ,
------- frmdly_sg => reg_module_frmdly ,
------- start_address_sg => reg_module_strt_addr ,
-------
------- -- Video Register Bank
------- vsize_vid => vsize_sg ,
------- hsize_vid => hsize_sg ,
------- stride_vid => stride_sg ,
------- frmdly_vid => frmdly_sg ,
------- start_address_vid => start_address_sg
------- );
-------
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
video_reg_update <= '1' when (frame_sync = '1' and video_reg_updated = '1')
or (video_prmtrs_valid_i = '0' and video_reg_updated = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
-- Video Register Block
VIDREGISTER_I : entity axi_vdma_v6_2_8.axi_vdma_vregister_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Video Register Update control
video_reg_update => video_reg_update ,
dmasr_halt => dmasr_halt ,
-- Scatter Gather register Bank
-- vsize_sg => vsize_sg ,
-- hsize_sg => hsize_sg ,
-- stride_sg => stride_sg ,
-- frmdly_sg => frmdly_sg ,
-- start_address_sg => start_address_sg ,
vsize_sg => reg_module_vsize ,
hsize_sg => reg_module_hsize ,
stride_sg => reg_module_stride ,
frmdly_sg => reg_module_frmdly ,
start_address_sg => reg_module_strt_addr ,
-- Video Register Bank
vsize_vid => crnt_vsize ,
hsize_vid => crnt_hsize ,
stride_vid => crnt_stride ,
frmdly_vid => crnt_frmdly ,
start_address_vid => start_address_vid
);
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_DRES;
GEN_REGDIRECT_NO_DRES : if C_DYNAMIC_RESOLUTION = 0 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
crnt_vsize <= reg_module_vsize;
crnt_hsize <= reg_module_hsize;
crnt_stride <= reg_module_stride;
crnt_frmdly <= reg_module_frmdly;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
start_address_vid(i) <= reg_module_strt_addr(i);
end generate GEN_START_ADDR_REG;
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_NO_DRES;
end generate GEN_REGISTER_DIRECT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vidreg_module_64.vhd
--
-- Description: This entity is the top level for the dual register blocks,
-- i.e. video register set and sg register set and provides
-- indication of valid parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module_64.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module_64.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vidreg_module_64 is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Start Address Width
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Register update control --
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
ftch_idle : in std_logic ; --
tailpntr_updated : in std_logic ; --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Register swap control/status --
frame_sync : in std_logic ; --
ftch_complete : in std_logic ; --
ftch_complete_clr : out std_logic ; --
parameter_update : out std_logic ; --
video_prmtrs_valid : out std_logic ; --
prmtr_update_complete : out std_logic ; -- CR605424
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
-- Descriptor data/control from sg interface --
desc_data_wren : in std_logic ; --
--
desc_strtaddress : in std_logic_vector --
(C_ADDR_WIDTH-1 downto 0) ; --
desc_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
desc_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
desc_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
desc_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
--
-- Scatter Gather register Bank --
crnt_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
crnt_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
crnt_stride : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
crnt_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vidreg_module_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vidreg_module_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Control
signal video_parameter_updt : std_logic := '0';
signal video_prmtrs_valid_i : std_logic := '0';
signal ftch_complete_clr_i : std_logic := '0';
signal run_stop_re : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal video_reg_updated : std_logic := '0';
signal video_reg_update : std_logic := '0';
signal update_complete : std_logic := '0';
-- Scatter Gather Side Video Register Bank
--signal vsize_sg : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal hsize_sg : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal stride_sg : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
--signal frmdly_sg : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
signal start_address_vid : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES - 1);
--signal start_address_sg : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- If Scatter Gather engine is included then instantiate SG register block
GEN_SG_REGISTER : if C_INCLUDE_SG = 1 generate
begin
-- Flag for updating video parameters on descriptor fetch
-- Used to enable vsize, hsize, stride, frmdly update on first desc
-- fetchted
REG_UPDATE_VIDEO_PRMTRS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_parameter_updt <= '0';
-- if new tailpointer and sg fetch engine idle or if new start then
-- set flag to capture video parameters
elsif((tailpntr_updated = '1' and ftch_idle = '1') or run_stop_re = '1')then
video_parameter_updt <= '1';
-- clear flag when parameters written to video_register module.
elsif(desc_data_wren = '1')then
video_parameter_updt <= '0';
end if;
end if;
end process REG_UPDATE_VIDEO_PRMTRS;
-- Register run stop to generate rising edge pulse
-- Used to force start address counter reset on shutdown
REG_RUN_STOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP;
run_stop_re <= run_stop and not run_stop_d1;
-- Scatter Gather Start Address Register Block (LUTRAM)
SG_ADDREG_I : entity axi_vdma_v6_2_8.axi_vdma_sgregister
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH ,
C_SELECT_XPM => C_SELECT_XPM ,
C_FAMILY => C_FAMILY
)
port map (
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Update Control
video_reg_update => video_reg_update ,
video_parameter_updt => video_parameter_updt ,
video_parameter_valid => video_prmtrs_valid_i ,
dmasr_halt => dmasr_halt ,
strt_addr_clr => run_stop_re ,
desc_data_wren => desc_data_wren ,
frame_number => frame_number ,
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr_i ,
update_complete => update_complete ,
num_fstore_minus1 => num_fstore_minus1 , -- CR607089
-- Video Start Address / Parameters In from Scatter Gather Engine
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly ,
desc_strtaddress => desc_strtaddress ,
-- Video Start Address / Parameters Out to DMA Controller
crnt_vsize => crnt_vsize ,
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride ,
crnt_frmdly => crnt_frmdly ,
crnt_start_address => crnt_start_address
);
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
--video_reg_update <= '1' when (frame_sync = '1' and ftch_complete = '1')
-- or (video_prmtrs_valid_i = '0' and ftch_complete = '1')
-- else '0';
video_reg_update <= '1' when (frame_sync = '1' and update_complete = '1')
or (video_prmtrs_valid_i = '0' and update_complete = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= update_complete;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
ftch_complete_clr_i <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
--elsif(frame_sync = '1' and ftch_complete = '1')then
elsif(frame_sync = '1' and update_complete = '1')then
video_prmtrs_valid_i <= '1';
ftch_complete_clr_i <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
ftch_complete_clr_i <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- When video register block update drive out parameter update flag
-- for generation of ****_prmtr_update output
parameter_update <= ftch_complete_clr_i;
-- Clear fetch flag in sg interface
ftch_complete_clr <= ftch_complete_clr_i;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
end generate GEN_SG_REGISTER;
-- If Scatter Gather engine is excluded then instantiate register direct block
GEN_REGISTER_DIRECT : if C_INCLUDE_SG = 0 generate
begin
GEN_REGDIRECT_DRES : if C_DYNAMIC_RESOLUTION = 1 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Register Direct Mode - Video Register Block
------- REGDIR_REGBLOCK_I : entity axi_vdma_v6_2_8.axi_vdma_vregister
------- generic map(
------- C_NUM_FSTORES => C_NUM_FSTORES ,
------- C_ADDR_WIDTH => C_ADDR_WIDTH
-------
------- )
------- port map(
------- prmry_aclk => prmry_aclk ,
------- prmry_resetn => prmry_resetn ,
-------
------- -- Video Register Update control
------- video_reg_update => ftch_complete ,
-------
------- dmasr_halt => dmasr_halt ,
-------
------- -- Scatter Gather register Bank
------- vsize_sg => reg_module_vsize ,
------- hsize_sg => reg_module_hsize ,
------- stride_sg => reg_module_stride ,
------- frmdly_sg => reg_module_frmdly ,
------- start_address_sg => reg_module_strt_addr ,
-------
------- -- Video Register Bank
------- vsize_vid => vsize_sg ,
------- hsize_vid => hsize_sg ,
------- stride_vid => stride_sg ,
------- frmdly_vid => frmdly_sg ,
------- start_address_vid => start_address_sg
------- );
-------
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
video_reg_update <= '1' when (frame_sync = '1' and video_reg_updated = '1')
or (video_prmtrs_valid_i = '0' and video_reg_updated = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
-- Video Register Block
VIDREGISTER_I : entity axi_vdma_v6_2_8.axi_vdma_vregister_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Video Register Update control
video_reg_update => video_reg_update ,
dmasr_halt => dmasr_halt ,
-- Scatter Gather register Bank
-- vsize_sg => vsize_sg ,
-- hsize_sg => hsize_sg ,
-- stride_sg => stride_sg ,
-- frmdly_sg => frmdly_sg ,
-- start_address_sg => start_address_sg ,
vsize_sg => reg_module_vsize ,
hsize_sg => reg_module_hsize ,
stride_sg => reg_module_stride ,
frmdly_sg => reg_module_frmdly ,
start_address_sg => reg_module_strt_addr ,
-- Video Register Bank
vsize_vid => crnt_vsize ,
hsize_vid => crnt_hsize ,
stride_vid => crnt_stride ,
frmdly_vid => crnt_frmdly ,
start_address_vid => start_address_vid
);
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_DRES;
GEN_REGDIRECT_NO_DRES : if C_DYNAMIC_RESOLUTION = 0 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
crnt_vsize <= reg_module_vsize;
crnt_hsize <= reg_module_hsize;
crnt_stride <= reg_module_stride;
crnt_frmdly <= reg_module_frmdly;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
start_address_vid(i) <= reg_module_strt_addr(i);
end generate GEN_START_ADDR_REG;
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_NO_DRES;
end generate GEN_REGISTER_DIRECT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vidreg_module_64.vhd
--
-- Description: This entity is the top level for the dual register blocks,
-- i.e. video register set and sg register set and provides
-- indication of valid parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module_64.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module_64.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vidreg_module_64 is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Start Address Width
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Register update control --
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
ftch_idle : in std_logic ; --
tailpntr_updated : in std_logic ; --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Register swap control/status --
frame_sync : in std_logic ; --
ftch_complete : in std_logic ; --
ftch_complete_clr : out std_logic ; --
parameter_update : out std_logic ; --
video_prmtrs_valid : out std_logic ; --
prmtr_update_complete : out std_logic ; -- CR605424
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
-- Descriptor data/control from sg interface --
desc_data_wren : in std_logic ; --
--
desc_strtaddress : in std_logic_vector --
(C_ADDR_WIDTH-1 downto 0) ; --
desc_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
desc_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
desc_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
desc_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
--
-- Scatter Gather register Bank --
crnt_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
crnt_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
crnt_stride : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
crnt_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vidreg_module_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vidreg_module_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Control
signal video_parameter_updt : std_logic := '0';
signal video_prmtrs_valid_i : std_logic := '0';
signal ftch_complete_clr_i : std_logic := '0';
signal run_stop_re : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal video_reg_updated : std_logic := '0';
signal video_reg_update : std_logic := '0';
signal update_complete : std_logic := '0';
-- Scatter Gather Side Video Register Bank
--signal vsize_sg : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal hsize_sg : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal stride_sg : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
--signal frmdly_sg : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
signal start_address_vid : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES - 1);
--signal start_address_sg : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- If Scatter Gather engine is included then instantiate SG register block
GEN_SG_REGISTER : if C_INCLUDE_SG = 1 generate
begin
-- Flag for updating video parameters on descriptor fetch
-- Used to enable vsize, hsize, stride, frmdly update on first desc
-- fetchted
REG_UPDATE_VIDEO_PRMTRS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_parameter_updt <= '0';
-- if new tailpointer and sg fetch engine idle or if new start then
-- set flag to capture video parameters
elsif((tailpntr_updated = '1' and ftch_idle = '1') or run_stop_re = '1')then
video_parameter_updt <= '1';
-- clear flag when parameters written to video_register module.
elsif(desc_data_wren = '1')then
video_parameter_updt <= '0';
end if;
end if;
end process REG_UPDATE_VIDEO_PRMTRS;
-- Register run stop to generate rising edge pulse
-- Used to force start address counter reset on shutdown
REG_RUN_STOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP;
run_stop_re <= run_stop and not run_stop_d1;
-- Scatter Gather Start Address Register Block (LUTRAM)
SG_ADDREG_I : entity axi_vdma_v6_2_8.axi_vdma_sgregister
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH ,
C_SELECT_XPM => C_SELECT_XPM ,
C_FAMILY => C_FAMILY
)
port map (
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Update Control
video_reg_update => video_reg_update ,
video_parameter_updt => video_parameter_updt ,
video_parameter_valid => video_prmtrs_valid_i ,
dmasr_halt => dmasr_halt ,
strt_addr_clr => run_stop_re ,
desc_data_wren => desc_data_wren ,
frame_number => frame_number ,
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr_i ,
update_complete => update_complete ,
num_fstore_minus1 => num_fstore_minus1 , -- CR607089
-- Video Start Address / Parameters In from Scatter Gather Engine
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly ,
desc_strtaddress => desc_strtaddress ,
-- Video Start Address / Parameters Out to DMA Controller
crnt_vsize => crnt_vsize ,
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride ,
crnt_frmdly => crnt_frmdly ,
crnt_start_address => crnt_start_address
);
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
--video_reg_update <= '1' when (frame_sync = '1' and ftch_complete = '1')
-- or (video_prmtrs_valid_i = '0' and ftch_complete = '1')
-- else '0';
video_reg_update <= '1' when (frame_sync = '1' and update_complete = '1')
or (video_prmtrs_valid_i = '0' and update_complete = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= update_complete;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
ftch_complete_clr_i <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
--elsif(frame_sync = '1' and ftch_complete = '1')then
elsif(frame_sync = '1' and update_complete = '1')then
video_prmtrs_valid_i <= '1';
ftch_complete_clr_i <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
ftch_complete_clr_i <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- When video register block update drive out parameter update flag
-- for generation of ****_prmtr_update output
parameter_update <= ftch_complete_clr_i;
-- Clear fetch flag in sg interface
ftch_complete_clr <= ftch_complete_clr_i;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
end generate GEN_SG_REGISTER;
-- If Scatter Gather engine is excluded then instantiate register direct block
GEN_REGISTER_DIRECT : if C_INCLUDE_SG = 0 generate
begin
GEN_REGDIRECT_DRES : if C_DYNAMIC_RESOLUTION = 1 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Register Direct Mode - Video Register Block
------- REGDIR_REGBLOCK_I : entity axi_vdma_v6_2_8.axi_vdma_vregister
------- generic map(
------- C_NUM_FSTORES => C_NUM_FSTORES ,
------- C_ADDR_WIDTH => C_ADDR_WIDTH
-------
------- )
------- port map(
------- prmry_aclk => prmry_aclk ,
------- prmry_resetn => prmry_resetn ,
-------
------- -- Video Register Update control
------- video_reg_update => ftch_complete ,
-------
------- dmasr_halt => dmasr_halt ,
-------
------- -- Scatter Gather register Bank
------- vsize_sg => reg_module_vsize ,
------- hsize_sg => reg_module_hsize ,
------- stride_sg => reg_module_stride ,
------- frmdly_sg => reg_module_frmdly ,
------- start_address_sg => reg_module_strt_addr ,
-------
------- -- Video Register Bank
------- vsize_vid => vsize_sg ,
------- hsize_vid => hsize_sg ,
------- stride_vid => stride_sg ,
------- frmdly_vid => frmdly_sg ,
------- start_address_vid => start_address_sg
------- );
-------
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
video_reg_update <= '1' when (frame_sync = '1' and video_reg_updated = '1')
or (video_prmtrs_valid_i = '0' and video_reg_updated = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
-- Video Register Block
VIDREGISTER_I : entity axi_vdma_v6_2_8.axi_vdma_vregister_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Video Register Update control
video_reg_update => video_reg_update ,
dmasr_halt => dmasr_halt ,
-- Scatter Gather register Bank
-- vsize_sg => vsize_sg ,
-- hsize_sg => hsize_sg ,
-- stride_sg => stride_sg ,
-- frmdly_sg => frmdly_sg ,
-- start_address_sg => start_address_sg ,
vsize_sg => reg_module_vsize ,
hsize_sg => reg_module_hsize ,
stride_sg => reg_module_stride ,
frmdly_sg => reg_module_frmdly ,
start_address_sg => reg_module_strt_addr ,
-- Video Register Bank
vsize_vid => crnt_vsize ,
hsize_vid => crnt_hsize ,
stride_vid => crnt_stride ,
frmdly_vid => crnt_frmdly ,
start_address_vid => start_address_vid
);
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_DRES;
GEN_REGDIRECT_NO_DRES : if C_DYNAMIC_RESOLUTION = 0 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
crnt_vsize <= reg_module_vsize;
crnt_hsize <= reg_module_hsize;
crnt_stride <= reg_module_stride;
crnt_frmdly <= reg_module_frmdly;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
start_address_vid(i) <= reg_module_strt_addr(i);
end generate GEN_START_ADDR_REG;
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_NO_DRES;
end generate GEN_REGISTER_DIRECT;
end implementation;
|
-- Template for VGA output by: Rene Kristensen
-- This design template uses gated clocks which generally are bad design practice.
-- This implies that the template design is not optimized for speed and will only serve for educational purpose.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga is
port (clk,reset : in std_logic;
red, green, blue : out std_logic_vector(9 downto 0);
hsync, vsync, clockOut, blank, compSync: out std_logic);
end vga;
architecture testGenerator of vga is
-- horizontal Timing constants for 640 x 480 @ 60Hz
constant hFrontPorch : natural := 16; -- units are number of 25 MHz clocks
constant hBackPorch : natural := 48;
constant hDataLen : natural := 640;
constant hSynWidth : natural := 96;
-- vertical Timing constants for 640 x 480 @ 60Hz
constant vFrontPorch : natural := 10; -- units are number of lines
constant vBackPorch : natural := 33;
constant vDataLen : natural := 480;
constant vSynWidth : natural := 2;
-- signal declaration
signal hSyncCounter, vSyncCounter : integer range 0 to 1023; -- contrain integer to 10 bit.
signal hSyncOut,vSyncOut,clk25,vBlank,hBlank : std_logic;
-- attributes ensuring the signals defined below are not reduced away before simulation.
attribute keep: boolean; -- don't reduce vSyncCounter and hSyncCounter signals away, so we can watch these signals i simulator
attribute keep of vSyncCounter : signal is true; -- || --
attribute keep of hSyncCounter: signal is true; -- || --
-- INSERT YOUR PROCEDURE HERE.
-- Your procedure should circular increment syncCounter, produce blanking and sync output.
procedure syncGenerator(
signal syncCounter : inout integer range 0 to 1023;
signal syncOut : out std_logic;
signal blankOut : out std_logic;
constant frontPorch : in natural;
constant backPorch : in natural;
constant dataLen : in natural;
constant syncWidth : in natural) is
begin
syncCounter <= syncCounter + 1;
if syncCounter <= backPorch then -- left side black area
blankOut <= '1';
syncOut <= '1';
elsif syncCounter <= (backPorch + dataLen) then -- Data area
blankOut <= '0';
syncOut <= '1';
elsif syncCounter < (backPorch + dataLen + frontPorch) then -- right side black area
blankOut <= '1';
syncOut <= '1';
elsif syncCounter = (backPorch + dataLen + frontPorch + syncWidth) then -- reset line
blankOut <= '1';
syncOut <= '0';
syncCounter <= 0;
elsif syncCounter > (backPorch + dataLen + frontPorch) then -- sync area
blankOut <= '1';
syncOut <= '0';
else
syncOut <= '1';
blankOut <= '0';
end if;
end procedure;
begin
clkdiv: process (reset,clk) -- creates a 25 MHz pixel clock (clk25) from a 50 MHz input (clk).
begin
if (reset = '0') then
clk25 <= '0';
elsif rising_edge(clk) then
clk25 <= not clk25;
end if;
end process;
-- horizontal process using the generic syncGenerator function to generate a proper hsync pulse.
hsyn: process (reset,clk25) -- reacts on reset and 25 MHz clock.
begin
if reset = '0' then
hSyncCounter <= 0;
elsif rising_edge(clk25) then
syncGenerator(hSyncCounter,hSyncOut,hBlank,hFrontPorch,hBackPorch,hDataLen,hSynWidth); -- generates active low pulse after every line
end if;
end process;
-- vertical process using the generic syncGenerator function to generate a proper vsync pulse.
vsyn: process (reset,hSyncOut) -- reacts on reset and hsync (meaning every line).
begin
if reset = '0' then
vSyncCounter <= 0;
elsif rising_edge(hSyncOut) then
syncGenerator(vSyncCounter,vSyncOut,vBlank,vFrontPorch,vBackPorch,vDataLen,vSynWidth); -- generates active low pulse after every picture
end if;
end process;
color: process (reset, hSyncCounter,vSyncCounter) -- draws italian flag color scheme
begin
if ((hSyncCounter > hBackPorch) and (hSyncCounter <= hBackPorch+213)) then
red <= (others => '0'); -- Green
green <= (others => '1');
blue <= (others => '0');
elsif ((hSyncCounter > hBackPorch+213) and (hSyncCounter <= hBackPorch+426)) then
red <= (others => '1'); -- White
green <= (others => '1');
blue <= (others => '1');
else
red <= (others => '1'); -- Red
green <= (others => '0');
blue <= (others => '0');
end if;
end process;
vsync <= vSyncOut; -- connect vsync to entity
hsync <= hSyncOut; -- connect hsync to entity
clockOut <= clk25; -- 25 MHz clock for DAC
blank <= not (vBlank or hBlank); -- active low blanking.
compSync <= '1'; -- Never perform any composite sync.
end testGenerator;
|
package Config is
constant CfgClkGating : boolean := false;
end Config;
package body Config is
end Config;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:33 03/21/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/MII_test2.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MII_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MII_test2 IS
END MII_test2;
ARCHITECTURE behavior OF MII_test2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MII_RX
PORT(
recv_data : IN std_logic_vector(3 downto 0);
recv_strobe : IN std_logic;
recv_clock : IN std_logic;
recv_error : IN std_logic;
next_frame : IN std_logic;
data_received : OUT std_logic;
clk : IN std_logic;
reset : IN std_logic;
busy : OUT std_logic;
ram_clk : IN std_logic;
ram_enable : IN std_logic;
ram_output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal recv_data : std_logic_vector(3 downto 0) := (others => '0');
signal recv_strobe : std_logic := '0';
signal recv_clock : std_logic := '0';
signal recv_error : std_logic := '0';
signal next_frame : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ram_clk : std_logic := '0';
signal ram_enable : std_logic := '0';
--Outputs
signal data_received : std_logic;
signal busy : std_logic;
signal ram_output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant recv_clock_period : time := 100 ns;
constant clk_period : time := 20 ns;
constant ram_clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MII_RX PORT MAP (
recv_data => recv_data,
recv_strobe => recv_strobe,
recv_clock => recv_clock,
recv_error => recv_error,
next_frame => next_frame,
data_received => data_received,
clk => clk,
reset => reset,
busy => busy,
ram_clk => ram_clk,
ram_enable => ram_enable,
ram_output => ram_output
);
-- Clock process definitions
recv_clock_process :process
begin
recv_clock <= '0';
wait for recv_clock_period/2;
recv_clock <= '1';
wait for recv_clock_period/2;
end process;
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ram_clk_process :process
begin
ram_clk <= '0';
wait for ram_clk_period/2;
ram_clk <= '1';
wait for ram_clk_period/2;
end process;
recv_data <= "1001";
recv_strobe <= '1', '0' after 100000 ns;
END;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5008)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5008)
`protect data_block
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a6AiNrrfd0LXSrydNrtiQXcrI6hFAb5Jfphftkm1HcgCyJ1mHcrKKkENNU95MSzbIw==
`protect end_protected
|
-- NEED RESULT: ARCH00577: Can declare entities with same name as entities declared in a use'd pkg passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00577
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.4 (1)
-- 10.4 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00574_577
-- PKG00574_577/BODY
-- ENT00577_Test_Bench(ARCH00577_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00574_577 is
type T1 is (one, two, three, four) ;
type T2 is (one, two, three, four) ;
type T3 is (one, two, three, four) ;
type T4 is (one, two, three, four) ;
subtype S1 is INTEGER;
subtype S2 is INTEGER;
subtype S3 is INTEGER;
subtype S4 is INTEGER;
function F1 return REAL ;
function F2 return REAL ;
function F3 return REAL ;
function F4 return REAL ;
end PKG00574_577 ;
package body PKG00574_577 is
function F1 return REAL is begin
return 0.0; end;
function F2 return REAL is begin
return 0.0; end;
function F3 return REAL is begin
return 0.0; end;
function F4 return REAL is begin
return 0.0; end;
end PKG00574_577 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00577_Test_Bench is
end ENT00577_Test_Bench ;
architecture ARCH00577_Test_Bench of ENT00577_Test_Bench is
begin
L_X_1 : block
use WORK.PKG00574_577; use PKG00574_577.all;
type T1 is record -- should be able to define new type T1
TE : BOOLEAN;
end record;
subtype T2 is REAL range 0.0 to 256.0; -- ditto for subtype called T2
attribute T3 : PKG00574_577.T3 ; -- ditto for attribute calle
signal T4 : PKG00574_577.T1; -- ditto for object called T
type S1 is record -- should be able to define new type S1
SE : BOOLEAN;
end record;
subtype S2 is REAL range 0.0 to 256.0; -- ditto for subtype called S2
attribute S3 : PKG00574_577.T3 ; -- ditto for attribute calle
signal S4 : PKG00574_577.T1; -- ditto for object called
type F1 is record -- should be able to define new type F1
FE : BOOLEAN;
end record;
subtype F2 is REAL range 0.0 to 256.0; -- ditto for subtype called F2
attribute F3 : PKG00574_577.T3 ; -- ditto for attribute calle
signal F4 : PKG00574_577.T1; -- ditto for object called F
begin
process
use PKG00574_577.all; -- This isn't necessary, but should be ok
variable T1 : PKG00574_577.T1; -- ditto for object called
variable F1 : PKG00574_577.T1; -- ditto for object called
variable S1 : PKG00574_577.T1; -- ditto for object called
begin
test_report ( "ARCH00577" ,
"Can declare entities with same name as entities "&
"declared in a use'd pkg" ,
True ) ;
wait ;
end process;
end block;
end ARCH00577_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: LUTROM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : LUTROM.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 18
-- C_READ_WIDTH_A : 18
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 18
-- C_READ_WIDTH_B : 18
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY LUTROM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END LUTROM_prod;
ARCHITECTURE xilinx OF LUTROM_prod IS
COMPONENT LUTROM_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : LUTROM_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
package std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
);
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string;
------------------------------------------------------------------------------
-- cover_item_set
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package std_ovl_procs;
package body std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string is
variable new_default : ovl_msg_default_type := (others => NUL);
begin
new_default(1 to default'high) := default;
return new_default;
end function ovl_set_msg;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
) is
begin
end procedure ovl_print_init_count_proc;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
) is
begin
end procedure ovl_error_proc;
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
) is
begin
end procedure ovl_init_msg_proc;
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
) is
begin
end procedure ovl_cover_proc;
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
) is
begin
end procedure ovl_finish_proc;
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE);
end function ovl_2state_is_on;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE) and
(property_type_ctrl /= OVL_ASSERT_2STATE) and
(property_type_ctrl /= OVL_ASSUME_2STATE) and
(controls.xcheck_ctrl = OVL_ON) and
((controls.implicit_xcheck_ctrl = OVL_ON) or explicit_x_check);
end function ovl_xcheck_is_on;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural is
begin
if (instance_val = OVL_NOT_SET) then
return default_ctrl_val;
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string is
variable msg_default_width : integer := ovl_msg_default_type'high;
begin
if (instance_val = OVL_MSG_NOT_SET) then
-- get width of msg_default value
for i in 1 to ovl_msg_default_type'high loop
if (default_ctrl_val(i) = NUL) then
msg_default_width := i - 1;
exit;
end if;
end loop;
return default_ctrl_val(1 to msg_default_width);
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- cover_item_set
-- determines if a bit in the level integer is set or not.
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean is
begin
return ((level mod (item * 2)) >= item);
end function cover_item_set;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean is
begin
return false;
end function ovl_is_x;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean is
begin
return false;
end function ovl_is_x;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result or v(i);
end if;
exit when result = '1';
end loop;
return result;
end function or_reduce;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result and v(i);
end if;
exit when result = '0';
end loop;
return result;
end function and_reduce;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result xor v(i);
end if;
end loop;
return result;
end function xor_reduce;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) sll r);
end function "sll";
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) srl r);
end function "srl";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
return unsigned(l) > r;
end function ">";
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
return unsigned(l) < r;
end function "<";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package body std_ovl_procs;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\CPU_Subsystem_8_bit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 1
-- Target subsystem base rate: 1
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 1
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- ext_out ce_out 1
-- hlt ce_out 1
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: CPU_Subsystem_8_bit
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit
-- Hierarchy Level: 0
--
-- Simulink model description for hdlcodercpu_eml:
--
-- An 8-bit RISC Processor using MATLAB(R) Function Blocks
-- This model shows how to use Simulink(R) HDL Coder(TM) to check,
-- generate and verify HDL for an 8-bit CPU implemented using the
-- MATLAB Function Block.
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY CPU_Subsystem_8_bit IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
master_reset : IN std_logic;
ce_out : OUT std_logic;
ext_out : OUT std_logic_vector(7 DOWNTO 0); -- int8
hlt : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END CPU_Subsystem_8_bit;
ARCHITECTURE rtl OF CPU_Subsystem_8_bit IS
-- Component Declarations
COMPONENT PC_Incrementer
PORT( jmp_offset : IN std_logic_vector(7 DOWNTO 0); -- int8
PC_current : IN std_logic_vector(7 DOWNTO 0); -- uint8
PC_next : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END COMPONENT;
COMPONENT Program_Counter
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
func : IN std_logic_vector(1 DOWNTO 0); -- ufix2
addr_in : IN std_logic_vector(7 DOWNTO 0); -- uint8
addr_out : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END COMPONENT;
COMPONENT Instruction_ROM
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0); -- uint8
read : IN std_logic; -- ufix1
instr_out : OUT std_logic_vector(11 DOWNTO 0) -- ufix12
);
END COMPONENT;
COMPONENT Instruction_Register
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
func : IN std_logic_vector(1 DOWNTO 0); -- ufix2
IR_in : IN std_logic_vector(11 DOWNTO 0); -- ufix12
IR_out : OUT std_logic_vector(11 DOWNTO 0) -- ufix12
);
END COMPONENT;
COMPONENT Arithmetic_Logical_Unit_8_bit
PORT( in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
func : IN std_logic_vector(2 DOWNTO 0); -- ufix3
alu_in : IN std_logic_vector(7 DOWNTO 0); -- int8
AC : IN std_logic_vector(7 DOWNTO 0); -- int8
alu_out : OUT std_logic_vector(7 DOWNTO 0); -- int8
out_flags : OUT std_logic_vector(3 DOWNTO 0) -- ufix4
);
END COMPONENT;
COMPONENT Shifter_8_bit
PORT( select_rsvd : IN std_logic_vector(1 DOWNTO 0); -- ufix2
input : IN std_logic_vector(7 DOWNTO 0); -- int8
in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
out_flags : OUT std_logic_vector(3 DOWNTO 0); -- ufix4
shift_out : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END COMPONENT;
COMPONENT Control_Unit
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0); -- int8
in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
master_rst : IN std_logic;
IR_in : IN std_logic_vector(11 DOWNTO 0); -- ufix12
shifter_sel : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
out_flags : OUT std_logic_vector(3 DOWNTO 0); -- ufix4
ALU_func : OUT std_logic_vector(2 DOWNTO 0); -- ufix3
print_data : OUT std_logic;
DM_addr : OUT std_logic_vector(7 DOWNTO 0); -- uint8
DM_r_w : OUT std_logic; -- ufix1
AC_func : OUT std_logic_vector(2 DOWNTO 0); -- ufix3
AC_data : OUT std_logic_vector(7 DOWNTO 0); -- int8
IR_func : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
PC_func : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
addr_inc : OUT std_logic_vector(7 DOWNTO 0); -- int8
IM_read : OUT std_logic; -- ufix1
hlt : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END COMPONENT;
COMPONENT Accumulator
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
func : IN std_logic_vector(2 DOWNTO 0); -- ufix3
AC_in1 : IN std_logic_vector(7 DOWNTO 0); -- int8
AC_in2 : IN std_logic_vector(7 DOWNTO 0); -- int8
AC_out : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END COMPONENT;
COMPONENT SinglePortRAM_Inst0
PORT( clk : IN std_logic;
enb : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0); -- int8
addr : IN std_logic_vector(7 DOWNTO 0); -- uint8
we : IN std_logic;
dout : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END COMPONENT;
COMPONENT output_enable
PORT( u : IN std_logic_vector(7 DOWNTO 0); -- int8
enable : IN std_logic;
y : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : PC_Incrementer
USE ENTITY work.PC_Incrementer(rtl);
FOR ALL : Program_Counter
USE ENTITY work.Program_Counter(rtl);
FOR ALL : Instruction_ROM
USE ENTITY work.Instruction_ROM(rtl);
FOR ALL : Instruction_Register
USE ENTITY work.Instruction_Register(rtl);
FOR ALL : Arithmetic_Logical_Unit_8_bit
USE ENTITY work.Arithmetic_Logical_Unit_8_bit(rtl);
FOR ALL : Shifter_8_bit
USE ENTITY work.Shifter_8_bit(rtl);
FOR ALL : Control_Unit
USE ENTITY work.Control_Unit(rtl);
FOR ALL : Accumulator
USE ENTITY work.Accumulator(rtl);
FOR ALL : SinglePortRAM_Inst0
USE ENTITY work.SinglePortRAM_Inst0(rtl);
FOR ALL : output_enable
USE ENTITY work.output_enable(rtl);
-- Signals
SIGNAL enb : std_logic;
SIGNAL Unit_Delay_7_out1 : std_logic;
SIGNAL shift_out : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL shift_out_signed : signed(7 DOWNTO 0); -- int8
SIGNAL Unit_Delay2_out1 : signed(7 DOWNTO 0); -- int8
SIGNAL addr_out : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL addr_out_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Unit_Delay_4_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL addr_inc : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL PC_next : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL PC_func : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL IM_read : std_logic; -- ufix1
SIGNAL instr_out : std_logic_vector(11 DOWNTO 0); -- ufix12
SIGNAL IR_func : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL IR_out : std_logic_vector(11 DOWNTO 0); -- ufix12
SIGNAL IR_out_unsigned : unsigned(11 DOWNTO 0); -- ufix12
SIGNAL Unit_Delay_1_out1 : unsigned(11 DOWNTO 0); -- ufix12
SIGNAL out_flags : std_logic_vector(3 DOWNTO 0); -- ufix4
SIGNAL ALU_func : std_logic_vector(2 DOWNTO 0); -- ufix3
SIGNAL Data_Memory_out1 : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL AC_out : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL alu_out : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL out_flags_1 : std_logic_vector(3 DOWNTO 0); -- ufix4
SIGNAL shifter_sel : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL out_flags_2 : std_logic_vector(3 DOWNTO 0); -- ufix4
SIGNAL out_flags_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Unit_Delay_3_out1 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Data_Memory_out1_signed : signed(7 DOWNTO 0); -- int8
SIGNAL feedback_for_indirect_addressing : signed(7 DOWNTO 0); -- int8
SIGNAL print_data : std_logic;
SIGNAL DM_addr : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL DM_r_w : std_logic; -- ufix1
SIGNAL AC_func : std_logic_vector(2 DOWNTO 0); -- ufix3
SIGNAL AC_data : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL hlt_tmp : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL y : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL y_signed : signed(7 DOWNTO 0); -- int8
SIGNAL Unit_Delay_6_out1 : signed(7 DOWNTO 0); -- int8
BEGIN
-- loading into AC
--
-- writing computation back into AC
--
-- Instruction to be executed
-- <S1>/PC Incrementer
u_PC_Incrementer : PC_Incrementer
PORT MAP( jmp_offset => addr_inc, -- int8
PC_current => std_logic_vector(Unit_Delay_4_out1), -- uint8
PC_next => PC_next -- uint8
);
-- <S1>/Program Counter
u_Program_Counter : Program_Counter
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
func => PC_func, -- ufix2
addr_in => PC_next, -- uint8
addr_out => addr_out -- uint8
);
-- <S1>/Instruction ROM
u_Instruction_ROM : Instruction_ROM
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
addr => addr_out, -- uint8
read => IM_read, -- ufix1
instr_out => instr_out -- ufix12
);
-- <S1>/Instruction Register
u_Instruction_Register : Instruction_Register
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
func => IR_func, -- ufix2
IR_in => instr_out, -- ufix12
IR_out => IR_out -- ufix12
);
-- <S1>/Arithmetic Logical Unit (8-bit)
u_Arithmetic_Logical_Unit_8_bit : Arithmetic_Logical_Unit_8_bit
PORT MAP( in_flags => out_flags, -- ufix4
func => ALU_func, -- ufix3
alu_in => Data_Memory_out1, -- int8
AC => AC_out, -- int8
alu_out => alu_out, -- int8
out_flags => out_flags_1 -- ufix4
);
-- <S1>/Shifter (8-bit)
u_Shifter_8_bit : Shifter_8_bit
PORT MAP( select_rsvd => shifter_sel, -- ufix2
input => alu_out, -- int8
in_flags => out_flags_1, -- ufix4
out_flags => out_flags_2, -- ufix4
shift_out => shift_out -- int8
);
-- <S1>/Control Unit
--
-- <S1>/Data Type Conversion
u_Control_Unit : Control_Unit
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
data_in => std_logic_vector(feedback_for_indirect_addressing), -- int8
in_flags => std_logic_vector(Unit_Delay_3_out1), -- ufix4
master_rst => Unit_Delay_7_out1,
IR_in => std_logic_vector(Unit_Delay_1_out1), -- ufix12
shifter_sel => shifter_sel, -- ufix2
out_flags => out_flags, -- ufix4
ALU_func => ALU_func, -- ufix3
print_data => print_data,
DM_addr => DM_addr, -- uint8
DM_r_w => DM_r_w, -- ufix1
AC_func => AC_func, -- ufix3
AC_data => AC_data, -- int8
IR_func => IR_func, -- ufix2
PC_func => PC_func, -- ufix2
addr_inc => addr_inc, -- int8
IM_read => IM_read, -- ufix1
hlt => hlt_tmp -- uint8
);
-- <S1>/Accumulator
u_Accumulator : Accumulator
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
func => AC_func, -- ufix3
AC_in1 => AC_data, -- int8
AC_in2 => std_logic_vector(Unit_Delay2_out1), -- int8
AC_out => AC_out -- int8
);
-- <S1>/Data Memory
u_SinglePortRAM_Inst0 : SinglePortRAM_Inst0
PORT MAP( clk => clk,
enb => clk_enable,
din => AC_out, -- int8
addr => DM_addr, -- uint8
we => DM_r_w,
dout => Data_Memory_out1 -- int8
);
-- <S1>/output_enable
u_output_enable : output_enable
PORT MAP( u => Data_Memory_out1, -- int8
enable => print_data,
y => y -- int8
);
enb <= clk_enable;
-- <S1>/Unit Delay 7
Unit_Delay_7_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Unit_Delay_7_out1 <= '0';
ELSIF enb = '1' THEN
Unit_Delay_7_out1 <= master_reset;
END IF;
END IF;
END PROCESS Unit_Delay_7_process;
shift_out_signed <= signed(shift_out);
-- <S1>/Unit Delay2
Unit_Delay2_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Unit_Delay2_out1 <= to_signed(2#00000000#, 8);
ELSIF enb = '1' THEN
Unit_Delay2_out1 <= shift_out_signed;
END IF;
END IF;
END PROCESS Unit_Delay2_process;
addr_out_unsigned <= unsigned(addr_out);
-- <S1>/Unit Delay 4
Unit_Delay_4_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Unit_Delay_4_out1 <= to_unsigned(2#00000000#, 8);
ELSIF enb = '1' THEN
Unit_Delay_4_out1 <= addr_out_unsigned;
END IF;
END IF;
END PROCESS Unit_Delay_4_process;
IR_out_unsigned <= unsigned(IR_out);
-- <S1>/Unit Delay 1
Unit_Delay_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Unit_Delay_1_out1 <= to_unsigned(2#000000000000#, 12);
ELSIF enb = '1' THEN
Unit_Delay_1_out1 <= IR_out_unsigned;
END IF;
END IF;
END PROCESS Unit_Delay_1_process;
out_flags_unsigned <= unsigned(out_flags_2);
-- <S1>/Unit Delay 3
Unit_Delay_3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Unit_Delay_3_out1 <= to_unsigned(2#0000#, 4);
ELSIF enb = '1' THEN
Unit_Delay_3_out1 <= out_flags_unsigned;
END IF;
END IF;
END PROCESS Unit_Delay_3_process;
Data_Memory_out1_signed <= signed(Data_Memory_out1);
-- <S1>/Unit Delay 5
Unit_Delay_5_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
feedback_for_indirect_addressing <= to_signed(2#00000000#, 8);
ELSIF enb = '1' THEN
feedback_for_indirect_addressing <= Data_Memory_out1_signed;
END IF;
END IF;
END PROCESS Unit_Delay_5_process;
y_signed <= signed(y);
-- <S1>/Unit Delay 6
Unit_Delay_6_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Unit_Delay_6_out1 <= to_signed(2#00000000#, 8);
ELSIF enb = '1' THEN
Unit_Delay_6_out1 <= y_signed;
END IF;
END IF;
END PROCESS Unit_Delay_6_process;
ext_out <= std_logic_vector(Unit_Delay_6_out1);
ce_out <= clk_enable;
-- <S1>/Scope
hlt <= hlt_tmp;
END rtl;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_spea2_entity;
ARCHITECTURE hal_spea2_description OF hal_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "00101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_spea2_description; |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_2 is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_2 is
signal sig : std_logic := '0';
begin
end architecture;
|
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_2 is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_2 is
signal sig : std_logic := '0';
begin
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
entity tb_rec04 is
end tb_rec04;
library ieee;
use ieee.std_logic_1164.all;
use work.rec04_pkg.all;
architecture behav of tb_rec04 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec04
port map (inp => inp, o => r);
process
begin
inp.a <= "0000";
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= "0010";
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= "1101";
inp.b <= '0';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= "1101";
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: scanregi, scanrego, scanregio
-- File: scanreg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Technology wrapper for boundary scan registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregi is
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregi is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregi_inf generic map (intesten) port map (pad,core,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
iten: if intesten /= 0 generate
m1 : grmux2 generic map (tech) port map (pad, q1, bsdrive, core);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
end generate;
itdis: if intesten = 0 generate
core <= pad;
q1 <= '0';
d1 <= '0';
end generate;
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, o1o, bscapt, m3i);
o1 : gror2 generic map (tech) port map (pad, bshighz, o1o);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanrego is
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic
);
end;
architecture tmap of scanrego is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanrego_inf port map (pad,core,samp,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive);
end generate;
map0: if tech /= 0 generate
m1 : grmux2 generic map (tech) port map (core, q1, bsdrive, pad);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, samp, bscapt, m3i);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregto is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregto is
signal tdo1, padoenx : std_ulogic;
begin
x1: scanrego generic map (tech)
port map (pado, coreo, samp, tck, tckn, tdo1, tdo, bsshft, bscapt, bsupdo, bsdrive);
x2: scanrego generic map (tech)
port map (padoenx, coreoen, coreoen, tck, tckn, tdi, tdo1, bsshft, bscapt, bsupdo, bsdrive);
hz : if hzsup = 1 generate
x3 : if oepol = 0 generate
x33 : gror2 generic map (tech) port map (padoenx, bshighz, padoen);
end generate;
x4 : if oepol = 1 generate
x33 : grand12 generic map (tech) port map (padoenx, bshighz, padoen);
end generate;
end generate;
nohz : if hzsup = 0 generate
padoen <= padoenx;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregio is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregio is
signal tdo1, tdo2, padoenx : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregio_inf
generic map (hzsup,intesten)
port map (pado,padoen,padi,coreo,coreoen,corei,tck,tckn,tdi,tdo,
bsshft,bscapt,bsupdi,bsupdo,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
x0: scanregi generic map (tech,intesten)
port map (padi, corei, tck, tckn, tdo1, tdo, bsshft, bscapt, bsupdi, bsdrive, bshighz);
x1: scanregto generic map (tech, hzsup, oepol)
port map (pado, padoen, coreo, coreo, coreoen,
tck, tckn, tdi, tdo1, bsshft, bscapt, bsupdo, bsdrive, bshighz);
end generate;
end;
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- A pseudo noise generator.
--
-- The relationship of input d to output q should be fairly random.
-- More input bits (dBits) improve the randomness. This can be a counter
-- or something dependend on (random) input.
-- For the same input it always generates the same output. So it can be
-- used as building block in a texture generator (e.g. perlin noise)
--
-- -----------------------------------------------------------------------
-- d - input
-- q - hashed / randomized output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity fractal_noise is
generic (
dBits : integer := 24;
qBits : integer := 24;
-- Some extra bits guarding against early round-down.
guardBits : integer := 4
);
port (
d : in unsigned(dBits-1 downto 0);
q : out unsigned(qBits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of fractal_noise is
signal xa : unsigned(q'high+guardBits downto 0);
signal xb : unsigned(q'high+guardBits downto 0);
signal xc : unsigned(q'high+guardBits downto 0);
signal xd : unsigned(q'high+guardBits downto 0);
begin
process(d) is
variable ta : std_logic;
variable tb : std_logic;
variable tc : std_logic;
variable td : std_logic;
begin
-- Generate 4 scrambled xor tables
for i in 0 to xa'high loop
ta := '0';
tb := '1';
tc := '0';
td := '1';
for j in 0 to d'high loop
if ((i+j) mod 3) = 0 then
ta := ta xor d(j);
end if;
if ((i+j) mod 5) = 0 then
tb := tb xor d(j);
end if;
if ((i+j) mod 7) = 0 then
tc := tc xor d(j);
end if;
if ((i+j) mod 11) = 0 then
td := td xor d(j);
end if;
end loop;
xa(i) <= ta;
xb(i) <= tb;
xc(i) <= tc;
xd(i) <= td;
end loop;
end process;
process(xa, xb, xc, xd) is
variable xt : unsigned(xa'high downto 0);
begin
-- Add the 4 scrambled values together to create more randomness
xt := xa + xb + xc + xd;
-- Assign result to output
q <= xt(xt'high downto guardBits);
end process;
end architecture;
|
library ieee ;
entity mytestbench is
end mytestbench;
architecture arch of mytestbench is
signal zero_length_array : bit_vector(-1 downto 0);
begin
-- Just here so we get a meaningful dump.
main_process: process
begin
wait for 10 ns;
wait;
end process;
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
entity LIFO is
generic(
-- address bus
m: integer := 5;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- write/read operation type
WR: in std_logic;
-- read data bus
RB: out std_logic_vector(n-1 downto 0);
-- write data bus
WB: in std_logic_vector(n-1 downto 0)
);
end LIFO;
architecture Beh of LIFO is
-- word type
subtype word is std_logic_vector (n-1 downto 0);
-- storage
type tRam is array (0 to 2**m - 1) of word;
signal sRAM: tRam := (
(others => (others => '0'))
);
signal head: unsigned(m - 1 downto 0) := (others => '0');
signal data_rb: std_logic_vector(n-1 downto 0);
signal data_wb: std_logic_vector(n-1 downto 0);
constant Limit: unsigned(m - 1 downto 0) := to_unsigned(2 ** m -1, m);
Begin
SH: process (CLK)
begin
if (EN = '1') then
if rising_edge(CLK) then
if (WR = '0') then
if (head = Limit) then
head <= (others => '0');
else
head <= head + 1;
end if;
elsif (WR = '1') then
if (head = 0) then
head <= Limit;
else
head <= head - 1;
end if;
end if;
end if;
end if;
end process;
data_wb <= WB;
WRP: process (CLK, head, data_wb)
begin
if (EN = '1') then
if rising_edge(CLK) then
if WR = '0' then
sRAM(to_integer(head)) <= data_wb;
end if;
end if;
end if;
end process;
RDP: process(CLK, head)
begin
if (EN = '1') then
if rising_edge(CLK) then
if WR = '1' then
if (head = 0) then
data_rb <= sRAM (to_integer(Limit));
else
data_rb <= sRAM (to_integer(head - 1));
end if;
end if;
end if;
end if;
end process;
RB <= data_rb;
end Beh; |
------------------------------------------------------------------------------------------
---------------------------- Global PCI --------------------------------------------
------------------------------------------------------------------------------------------
package GLOBAL_PCI_CONFIG is
-- Clocks until Master has to assign IRDY after FRAME is set and GNT is given
constant c_MasterTimeOut : integer := 8;
-- Clocks until Target has to assign DEVSEL after FRAME
constant c_DevselTimeOut : integer := 4;
end GLOBAL_PCI_CONFIG;
------------------------------------------------------------------------------------------
---------------------------- Arbiter -----------------------------------------------
------------------------------------------------------------------------------------------
package ARBITER_CONFIG is
-- number of agents attached to the bus
constant c_Agents : integer := 4;
-- number of clocks master gets maximal priority
constant c_AckTimer : integer := 8;
end ARBITER_CONFIG;
|
-- This example was provided by:
-- Bruce Cockburn and Jie Han
-- However it was a collaboration between Qiushi Jiang and myself
-- to modify it and fix up changes
library IEEE;
using IEEE.STD_LOGIC_1164.all;
entity NBitAdder is
generic(width: integer := 16);
Port (
A: in STD_LOGIC_VECTOR(width - 1 downto 0);
B: in STD_LOGIC_VECTOR(width - 1 downto 0);
Sum: out STD_LOGIC_VECTOR(width downto 0);
);
end NBitAdder;
architecture Behavioral of NBitAdder is
component fullAdder is
Port(
A: in STD_LOGIC;
B: in STD_LOGIC;
Sum: out STD_LOGIC;
Cout: out STD_LOGIC;
);
end component fullAdder;
signal carries: STD_LOGIC_VECTOR(width downto 0);
begin:
FAs: for i in 0 to width - 1 generate
aFA: fullAdder port map(
A => A(i),
B => B(i),
Cin => carries(i),
Sum => Sum(i);
Cout => carries(i+1)
);
end generate;
carries(0) <= '0';
sum(width) <= carries(width);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Title : or3
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : or3.vhd
-- Generated : Fri Oct 3 18:47:17 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {or3} architecture {or3}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity or3 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Z : out STD_LOGIC
);
end or3;
--}} End of automatically maintained section
architecture or3 of or3 is
begin
Z <= A or B or C;
end or3;
|
-------------------------------------------------------------------------------
--
-- Title : or3
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : or3.vhd
-- Generated : Fri Oct 3 18:47:17 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {or3} architecture {or3}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity or3 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Z : out STD_LOGIC
);
end or3;
--}} End of automatically maintained section
architecture or3 of or3 is
begin
Z <= A or B or C;
end or3;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:10:16 07/01/2015
-- Design Name:
-- Module Name: keyMatrixLED - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keyMatrixLED is
Port ( keyMatrix : in STD_LOGIC_VECTOR (31 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0));
end keyMatrixLED;
architecture Behavioral of keyMatrixLED is
begin
led <= (keyMatrix(31 downto 24) xor keyMatrix(23 downto 16) xor keyMatrix(15 downto 8) xor keyMatrix(7 downto 0));
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.constants.all;
entity test_shifter is
end test_shifter;
architecture testbench of test_shifter is
component bshift
port (
direction : in std_logic; -- '1' for left, '0' for right
logical : in std_logic; -- '1' for logical, '0' for arithmetic
shift : in std_logic_vector(4 downto 0); -- shift count
input : in std_logic_vector (31 downto 0);
output : out std_logic_vector (31 downto 0)
);
end component;
signal A,output : std_logic_vector (31 downto 0);
signal B : std_logic_vector(4 downto 0);
signal AL : std_logic;
signal LR : std_logic;
begin
INIT: bshift port map(LR,AL,B,A,output);
A <= x"0000000F",not x"0000000F" after 15 ns;
B <= "00001", "00010" after 5 ns,"00011" after 10 ns,"00001" after 15 ns,"00010" after 20 ns,"00011" after 25 ns;
LR <= '1', '0' after 15 ns,'1' after 35 ns;
AL <= '1', '0' after 15 ns,'1' after 20 ns;
end testbench; |
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_avr is port(
alu_data_r_in : in std_logic_vector(7 downto 0);
alu_data_d_in : in std_logic_vector(7 downto 0);
alu_c_flag_in : in std_logic;
alu_z_flag_in : in std_logic;
-- OPERATION SIGNALS INPUTS
idc_add :in std_logic;
idc_adc :in std_logic;
idc_adiw :in std_logic;
idc_sub :in std_logic;
idc_subi :in std_logic;
idc_sbc :in std_logic;
idc_sbci :in std_logic;
idc_sbiw :in std_logic;
adiw_st : in std_logic;
sbiw_st : in std_logic;
idc_and :in std_logic;
idc_andi :in std_logic;
idc_or :in std_logic;
idc_ori :in std_logic;
idc_eor :in std_logic;
idc_com :in std_logic;
idc_neg :in std_logic;
idc_inc :in std_logic;
idc_dec :in std_logic;
idc_cp :in std_logic;
idc_cpc :in std_logic;
idc_cpi :in std_logic;
idc_cpse :in std_logic;
idc_lsr :in std_logic;
idc_ror :in std_logic;
idc_asr :in std_logic;
idc_swap :in std_logic;
-- DATA OUTPUT
alu_data_out : out std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : out std_logic;
alu_z_flag_out : out std_logic;
alu_n_flag_out : out std_logic;
alu_v_flag_out : out std_logic;
alu_s_flag_out : out std_logic;
alu_h_flag_out : out std_logic
);
end alu_avr;
architecture rtl of alu_avr is
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
signal alu_data_out_int : std_logic_vector (7 downto 0);
-- ALU FLAGS (INTERNAL)
signal alu_z_flag_out_int : std_logic;
signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
signal alu_n_flag_out_int : std_logic;
signal alu_v_flag_out_int : std_logic;
signal alu_c_flag_out_int : std_logic;
-- ADDER SIGNALS --
signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
signal adder_v_flag_out : std_logic;
signal adder_carry : std_logic_vector(8 downto 0);
signal adder_d_in : std_logic_vector(8 downto 0);
signal adder_r_in : std_logic_vector(8 downto 0);
signal adder_out : std_logic_vector(8 downto 0);
-- NEG OPERATOR SIGNALS
signal neg_op_in : std_logic_vector(7 downto 0);
signal neg_op_carry : std_logic_vector(8 downto 0);
signal neg_op_out : std_logic_vector(8 downto 0);
-- INC, DEC OPERATOR SIGNALS
signal incdec_op_in : std_logic_vector (7 downto 0);
signal incdec_op_carry : std_logic_vector(7 downto 0);
signal incdec_op_out : std_logic_vector(7 downto 0);
signal com_op_out : std_logic_vector(7 downto 0);
signal and_op_out : std_logic_vector(7 downto 0);
signal or_op_out : std_logic_vector(7 downto 0);
signal eor_op_out : std_logic_vector(7 downto 0);
-- SHIFT SIGNALS
signal right_shift_out : std_logic_vector(7 downto 0);
-- SWAP SIGNALS
signal swap_out : std_logic_vector(7 downto 0);
begin
-- ########################################################################
-- ############### ALU
-- ########################################################################
adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or
idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-'
-- SREG C FLAG (ALU INPUT)
alu_c_flag_in_int <= alu_c_flag_in and
(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
idc_cpc or
idc_ror);
-- SREG Z FLAG ()
-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st or idc_cpc or idc_sbc or idc_sbci)) or
((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st))or
(alu_z_flag_in and alu_z_flag_out_int and(idc_cpc or idc_sbc or idc_sbci)); -- Previous value (for CPC/SBC/SBCI instructions)
-- SREG N FLAG
alu_n_flag_out <= alu_n_flag_out_int;
-- SREG V FLAG
alu_v_flag_out <= alu_v_flag_out_int;
alu_c_flag_out <= alu_c_flag_out_int;
alu_data_out <= alu_data_out_int;
-- #########################################################################################
adder_d_in <= '0'&alu_data_d_in;
adder_r_in <= '0'&alu_data_r_in;
--########################## ADDEER ###################################
adder_out(0) <= adder_d_in(0) xor adder_r_in(0) xor alu_c_flag_in_int;
adder_carry(0) <= ((adder_d_in(0) xor adder_nadd_sub) and adder_r_in(0)) or
(((adder_d_in(0) xor adder_nadd_sub) or adder_r_in(0)) and alu_c_flag_in_int);
summator:for i in 1 to 8 generate
adder_out(i) <= adder_d_in(i) xor adder_r_in(i) xor adder_carry(i-1);
adder_carry(i) <= ((adder_d_in(i) xor adder_nadd_sub) and adder_r_in(i)) or
(((adder_d_in(i) xor adder_nadd_sub) or adder_r_in(i)) and adder_carry(i-1));
end generate;
-- FLAGS FOR ADDER INSTRUCTIONS:
-- CARRY FLAG (C) -> adder_out(8)
-- HALF CARRY FLAG (H) -> adder_carry(3)
-- TOW'S COMPLEMENT OVERFLOW (V) ->
adder_v_flag_out <= (((adder_d_in(7) and adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and not adder_r_in(7) and adder_out(7))) and not adder_nadd_sub) or -- ADD
(((adder_d_in(7) and not adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and adder_r_in(7) and adder_out(7))) and adder_nadd_sub);
-- SUB
--#####################################################################
-- LOGICAL OPERATIONS FOR ONE OPERAND
--########################## NEG OPERATION ####################
neg_op_out(0) <= not alu_data_d_in(0) xor '1';
neg_op_carry(0) <= not alu_data_d_in(0) and '1';
neg_op:for i in 1 to 7 generate
neg_op_out(i) <= not alu_data_d_in(i) xor neg_op_carry(i-1);
neg_op_carry(i) <= not alu_data_d_in(i) and neg_op_carry(i-1);
end generate;
neg_op_out(8) <= neg_op_carry(7) xor '1';
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
-- CARRY FLAGS FOR NEG INSTRUCTION:
-- CARRY FLAG -> neg_op_out(8)
-- HALF CARRY FLAG -> neg_op_carry(3)
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
--############################################################################
--########################## INC, DEC OPERATIONS ####################
incdec_op_out(0) <= alu_data_d_in(0) xor '1';
incdec_op_carry(0) <= alu_data_d_in(0) xor idc_dec;
inc_dec:for i in 1 to 7 generate
incdec_op_out(i) <= alu_data_d_in(i) xor incdec_op_carry(i-1);
incdec_op_carry(i) <= (alu_data_d_in(i) xor idc_dec) and incdec_op_carry(i-1);
end generate;
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
--####################################################################
--########################## COM OPERATION ###################################
com_op_out <= not alu_data_d_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
-- CARRY FLAG (C) -> '1'
--############################################################################
-- LOGICAL OPERATIONS FOR TWO OPERANDS
--########################## AND OPERATION ###################################
and_op_out <= alu_data_d_in and alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## OR OPERATION ###################################
or_op_out <= alu_data_d_in or alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## EOR OPERATION ###################################
eor_op_out <= alu_data_d_in xor alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
-- SHIFT OPERATIONS
-- ########################## RIGHT(LSR, ROR, ASR) #######################
right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
shift_right:for i in 6 downto 0 generate
right_shift_out(i) <= alu_data_d_in(i+1);
end generate;
-- FLAGS
-- CARRY FLAG (C) -> alu_data_d_in(0)
-- NEGATIVE FLAG (N) -> right_shift_out(7)
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
-- #######################################################################
-- ################################## SWAP ###############################
swap_h:for i in 7 downto 4 generate
swap_out(i) <= alu_data_d_in(i-4);
end generate;
swap_l:for i in 3 downto 0 generate
swap_out(i) <= alu_data_d_in(i+4);
end generate;
-- #######################################################################
-- ALU OUTPUT MUX
alu_data_out_mux:for i in alu_data_out_int'range generate
alu_data_out_int(i) <= (adder_out(i) and (idc_add or idc_adc or (idc_adiw or adiw_st) or -- !!!!!
idc_sub or idc_subi or idc_sbc or idc_sbci or
(idc_sbiw or sbiw_st) or -- !!!!!
idc_cpse or idc_cp or idc_cpc or idc_cpi)) or
(neg_op_out(i) and idc_neg) or -- NEG
(incdec_op_out(i) and (idc_inc or idc_dec)) or -- INC/DEC
(com_op_out(i) and idc_com) or -- COM
(and_op_out(i) and (idc_and or idc_andi)) or -- AND/ANDI
(or_op_out(i) and (idc_or or idc_ori)) or -- OR/ORI
(eor_op_out(i) and idc_eor) or -- EOR
(right_shift_out(i) and (idc_lsr or idc_ror or idc_asr)) or -- LSR/ROR/ASR
(swap_out(i) and idc_swap); -- SWAP
end generate;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
alu_h_flag_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_cp or idc_cpc or idc_cpi)) or
(not neg_op_carry(3) and idc_neg); -- H-flag problem with NEG instruction fixing -- NEG
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
alu_v_flag_out_int <= (adder_v_flag_out and
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or adiw_st or sbiw_st or idc_cp or idc_cpi or idc_cpc)) or
((alu_data_d_in(7) and neg_op_carry(6)) and idc_neg) or -- NEG
(not alu_data_d_in(7) and incdec_op_carry(6) and idc_inc) or -- INC
(alu_data_d_in(7) and incdec_op_carry(6) and idc_dec) or -- DEC
((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr or idc_ror or idc_asr)); -- LSR,ROR,ASR
alu_n_flag_out_int <= alu_data_out_int(7);
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
alu_c_flag_out_int <= (adder_out(8) and
(idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi)) or -- ADDER
(not alu_z_flag_out_int and idc_neg) or -- NEG
(alu_data_d_in(0) and (idc_lsr or idc_ror or idc_asr)) or idc_com;
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
end rtl;
|
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_avr is port(
alu_data_r_in : in std_logic_vector(7 downto 0);
alu_data_d_in : in std_logic_vector(7 downto 0);
alu_c_flag_in : in std_logic;
alu_z_flag_in : in std_logic;
-- OPERATION SIGNALS INPUTS
idc_add :in std_logic;
idc_adc :in std_logic;
idc_adiw :in std_logic;
idc_sub :in std_logic;
idc_subi :in std_logic;
idc_sbc :in std_logic;
idc_sbci :in std_logic;
idc_sbiw :in std_logic;
adiw_st : in std_logic;
sbiw_st : in std_logic;
idc_and :in std_logic;
idc_andi :in std_logic;
idc_or :in std_logic;
idc_ori :in std_logic;
idc_eor :in std_logic;
idc_com :in std_logic;
idc_neg :in std_logic;
idc_inc :in std_logic;
idc_dec :in std_logic;
idc_cp :in std_logic;
idc_cpc :in std_logic;
idc_cpi :in std_logic;
idc_cpse :in std_logic;
idc_lsr :in std_logic;
idc_ror :in std_logic;
idc_asr :in std_logic;
idc_swap :in std_logic;
-- DATA OUTPUT
alu_data_out : out std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : out std_logic;
alu_z_flag_out : out std_logic;
alu_n_flag_out : out std_logic;
alu_v_flag_out : out std_logic;
alu_s_flag_out : out std_logic;
alu_h_flag_out : out std_logic
);
end alu_avr;
architecture rtl of alu_avr is
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
signal alu_data_out_int : std_logic_vector (7 downto 0);
-- ALU FLAGS (INTERNAL)
signal alu_z_flag_out_int : std_logic;
signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
signal alu_n_flag_out_int : std_logic;
signal alu_v_flag_out_int : std_logic;
signal alu_c_flag_out_int : std_logic;
-- ADDER SIGNALS --
signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
signal adder_v_flag_out : std_logic;
signal adder_carry : std_logic_vector(8 downto 0);
signal adder_d_in : std_logic_vector(8 downto 0);
signal adder_r_in : std_logic_vector(8 downto 0);
signal adder_out : std_logic_vector(8 downto 0);
-- NEG OPERATOR SIGNALS
signal neg_op_in : std_logic_vector(7 downto 0);
signal neg_op_carry : std_logic_vector(8 downto 0);
signal neg_op_out : std_logic_vector(8 downto 0);
-- INC, DEC OPERATOR SIGNALS
signal incdec_op_in : std_logic_vector (7 downto 0);
signal incdec_op_carry : std_logic_vector(7 downto 0);
signal incdec_op_out : std_logic_vector(7 downto 0);
signal com_op_out : std_logic_vector(7 downto 0);
signal and_op_out : std_logic_vector(7 downto 0);
signal or_op_out : std_logic_vector(7 downto 0);
signal eor_op_out : std_logic_vector(7 downto 0);
-- SHIFT SIGNALS
signal right_shift_out : std_logic_vector(7 downto 0);
-- SWAP SIGNALS
signal swap_out : std_logic_vector(7 downto 0);
begin
-- ########################################################################
-- ############### ALU
-- ########################################################################
adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or
idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-'
-- SREG C FLAG (ALU INPUT)
alu_c_flag_in_int <= alu_c_flag_in and
(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
idc_cpc or
idc_ror);
-- SREG Z FLAG ()
-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st or idc_cpc or idc_sbc or idc_sbci)) or
((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st))or
(alu_z_flag_in and alu_z_flag_out_int and(idc_cpc or idc_sbc or idc_sbci)); -- Previous value (for CPC/SBC/SBCI instructions)
-- SREG N FLAG
alu_n_flag_out <= alu_n_flag_out_int;
-- SREG V FLAG
alu_v_flag_out <= alu_v_flag_out_int;
alu_c_flag_out <= alu_c_flag_out_int;
alu_data_out <= alu_data_out_int;
-- #########################################################################################
adder_d_in <= '0'&alu_data_d_in;
adder_r_in <= '0'&alu_data_r_in;
--########################## ADDEER ###################################
adder_out(0) <= adder_d_in(0) xor adder_r_in(0) xor alu_c_flag_in_int;
adder_carry(0) <= ((adder_d_in(0) xor adder_nadd_sub) and adder_r_in(0)) or
(((adder_d_in(0) xor adder_nadd_sub) or adder_r_in(0)) and alu_c_flag_in_int);
summator:for i in 1 to 8 generate
adder_out(i) <= adder_d_in(i) xor adder_r_in(i) xor adder_carry(i-1);
adder_carry(i) <= ((adder_d_in(i) xor adder_nadd_sub) and adder_r_in(i)) or
(((adder_d_in(i) xor adder_nadd_sub) or adder_r_in(i)) and adder_carry(i-1));
end generate;
-- FLAGS FOR ADDER INSTRUCTIONS:
-- CARRY FLAG (C) -> adder_out(8)
-- HALF CARRY FLAG (H) -> adder_carry(3)
-- TOW'S COMPLEMENT OVERFLOW (V) ->
adder_v_flag_out <= (((adder_d_in(7) and adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and not adder_r_in(7) and adder_out(7))) and not adder_nadd_sub) or -- ADD
(((adder_d_in(7) and not adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and adder_r_in(7) and adder_out(7))) and adder_nadd_sub);
-- SUB
--#####################################################################
-- LOGICAL OPERATIONS FOR ONE OPERAND
--########################## NEG OPERATION ####################
neg_op_out(0) <= not alu_data_d_in(0) xor '1';
neg_op_carry(0) <= not alu_data_d_in(0) and '1';
neg_op:for i in 1 to 7 generate
neg_op_out(i) <= not alu_data_d_in(i) xor neg_op_carry(i-1);
neg_op_carry(i) <= not alu_data_d_in(i) and neg_op_carry(i-1);
end generate;
neg_op_out(8) <= neg_op_carry(7) xor '1';
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
-- CARRY FLAGS FOR NEG INSTRUCTION:
-- CARRY FLAG -> neg_op_out(8)
-- HALF CARRY FLAG -> neg_op_carry(3)
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
--############################################################################
--########################## INC, DEC OPERATIONS ####################
incdec_op_out(0) <= alu_data_d_in(0) xor '1';
incdec_op_carry(0) <= alu_data_d_in(0) xor idc_dec;
inc_dec:for i in 1 to 7 generate
incdec_op_out(i) <= alu_data_d_in(i) xor incdec_op_carry(i-1);
incdec_op_carry(i) <= (alu_data_d_in(i) xor idc_dec) and incdec_op_carry(i-1);
end generate;
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
--####################################################################
--########################## COM OPERATION ###################################
com_op_out <= not alu_data_d_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
-- CARRY FLAG (C) -> '1'
--############################################################################
-- LOGICAL OPERATIONS FOR TWO OPERANDS
--########################## AND OPERATION ###################################
and_op_out <= alu_data_d_in and alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## OR OPERATION ###################################
or_op_out <= alu_data_d_in or alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## EOR OPERATION ###################################
eor_op_out <= alu_data_d_in xor alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
-- SHIFT OPERATIONS
-- ########################## RIGHT(LSR, ROR, ASR) #######################
right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
shift_right:for i in 6 downto 0 generate
right_shift_out(i) <= alu_data_d_in(i+1);
end generate;
-- FLAGS
-- CARRY FLAG (C) -> alu_data_d_in(0)
-- NEGATIVE FLAG (N) -> right_shift_out(7)
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
-- #######################################################################
-- ################################## SWAP ###############################
swap_h:for i in 7 downto 4 generate
swap_out(i) <= alu_data_d_in(i-4);
end generate;
swap_l:for i in 3 downto 0 generate
swap_out(i) <= alu_data_d_in(i+4);
end generate;
-- #######################################################################
-- ALU OUTPUT MUX
alu_data_out_mux:for i in alu_data_out_int'range generate
alu_data_out_int(i) <= (adder_out(i) and (idc_add or idc_adc or (idc_adiw or adiw_st) or -- !!!!!
idc_sub or idc_subi or idc_sbc or idc_sbci or
(idc_sbiw or sbiw_st) or -- !!!!!
idc_cpse or idc_cp or idc_cpc or idc_cpi)) or
(neg_op_out(i) and idc_neg) or -- NEG
(incdec_op_out(i) and (idc_inc or idc_dec)) or -- INC/DEC
(com_op_out(i) and idc_com) or -- COM
(and_op_out(i) and (idc_and or idc_andi)) or -- AND/ANDI
(or_op_out(i) and (idc_or or idc_ori)) or -- OR/ORI
(eor_op_out(i) and idc_eor) or -- EOR
(right_shift_out(i) and (idc_lsr or idc_ror or idc_asr)) or -- LSR/ROR/ASR
(swap_out(i) and idc_swap); -- SWAP
end generate;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
alu_h_flag_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_cp or idc_cpc or idc_cpi)) or
(not neg_op_carry(3) and idc_neg); -- H-flag problem with NEG instruction fixing -- NEG
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
alu_v_flag_out_int <= (adder_v_flag_out and
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or adiw_st or sbiw_st or idc_cp or idc_cpi or idc_cpc)) or
((alu_data_d_in(7) and neg_op_carry(6)) and idc_neg) or -- NEG
(not alu_data_d_in(7) and incdec_op_carry(6) and idc_inc) or -- INC
(alu_data_d_in(7) and incdec_op_carry(6) and idc_dec) or -- DEC
((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr or idc_ror or idc_asr)); -- LSR,ROR,ASR
alu_n_flag_out_int <= alu_data_out_int(7);
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
alu_c_flag_out_int <= (adder_out(8) and
(idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi)) or -- ADDER
(not alu_z_flag_out_int and idc_neg) or -- NEG
(alu_data_d_in(0) and (idc_lsr or idc_ror or idc_asr)) or idc_com;
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
end rtl;
|
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_avr is port(
alu_data_r_in : in std_logic_vector(7 downto 0);
alu_data_d_in : in std_logic_vector(7 downto 0);
alu_c_flag_in : in std_logic;
alu_z_flag_in : in std_logic;
-- OPERATION SIGNALS INPUTS
idc_add :in std_logic;
idc_adc :in std_logic;
idc_adiw :in std_logic;
idc_sub :in std_logic;
idc_subi :in std_logic;
idc_sbc :in std_logic;
idc_sbci :in std_logic;
idc_sbiw :in std_logic;
adiw_st : in std_logic;
sbiw_st : in std_logic;
idc_and :in std_logic;
idc_andi :in std_logic;
idc_or :in std_logic;
idc_ori :in std_logic;
idc_eor :in std_logic;
idc_com :in std_logic;
idc_neg :in std_logic;
idc_inc :in std_logic;
idc_dec :in std_logic;
idc_cp :in std_logic;
idc_cpc :in std_logic;
idc_cpi :in std_logic;
idc_cpse :in std_logic;
idc_lsr :in std_logic;
idc_ror :in std_logic;
idc_asr :in std_logic;
idc_swap :in std_logic;
-- DATA OUTPUT
alu_data_out : out std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : out std_logic;
alu_z_flag_out : out std_logic;
alu_n_flag_out : out std_logic;
alu_v_flag_out : out std_logic;
alu_s_flag_out : out std_logic;
alu_h_flag_out : out std_logic
);
end alu_avr;
architecture rtl of alu_avr is
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
signal alu_data_out_int : std_logic_vector (7 downto 0);
-- ALU FLAGS (INTERNAL)
signal alu_z_flag_out_int : std_logic;
signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
signal alu_n_flag_out_int : std_logic;
signal alu_v_flag_out_int : std_logic;
signal alu_c_flag_out_int : std_logic;
-- ADDER SIGNALS --
signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
signal adder_v_flag_out : std_logic;
signal adder_carry : std_logic_vector(8 downto 0);
signal adder_d_in : std_logic_vector(8 downto 0);
signal adder_r_in : std_logic_vector(8 downto 0);
signal adder_out : std_logic_vector(8 downto 0);
-- NEG OPERATOR SIGNALS
signal neg_op_in : std_logic_vector(7 downto 0);
signal neg_op_carry : std_logic_vector(8 downto 0);
signal neg_op_out : std_logic_vector(8 downto 0);
-- INC, DEC OPERATOR SIGNALS
signal incdec_op_in : std_logic_vector (7 downto 0);
signal incdec_op_carry : std_logic_vector(7 downto 0);
signal incdec_op_out : std_logic_vector(7 downto 0);
signal com_op_out : std_logic_vector(7 downto 0);
signal and_op_out : std_logic_vector(7 downto 0);
signal or_op_out : std_logic_vector(7 downto 0);
signal eor_op_out : std_logic_vector(7 downto 0);
-- SHIFT SIGNALS
signal right_shift_out : std_logic_vector(7 downto 0);
-- SWAP SIGNALS
signal swap_out : std_logic_vector(7 downto 0);
begin
-- ########################################################################
-- ############### ALU
-- ########################################################################
adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or
idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-'
-- SREG C FLAG (ALU INPUT)
alu_c_flag_in_int <= alu_c_flag_in and
(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
idc_cpc or
idc_ror);
-- SREG Z FLAG ()
-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st or idc_cpc or idc_sbc or idc_sbci)) or
((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st))or
(alu_z_flag_in and alu_z_flag_out_int and(idc_cpc or idc_sbc or idc_sbci)); -- Previous value (for CPC/SBC/SBCI instructions)
-- SREG N FLAG
alu_n_flag_out <= alu_n_flag_out_int;
-- SREG V FLAG
alu_v_flag_out <= alu_v_flag_out_int;
alu_c_flag_out <= alu_c_flag_out_int;
alu_data_out <= alu_data_out_int;
-- #########################################################################################
adder_d_in <= '0'&alu_data_d_in;
adder_r_in <= '0'&alu_data_r_in;
--########################## ADDEER ###################################
adder_out(0) <= adder_d_in(0) xor adder_r_in(0) xor alu_c_flag_in_int;
adder_carry(0) <= ((adder_d_in(0) xor adder_nadd_sub) and adder_r_in(0)) or
(((adder_d_in(0) xor adder_nadd_sub) or adder_r_in(0)) and alu_c_flag_in_int);
summator:for i in 1 to 8 generate
adder_out(i) <= adder_d_in(i) xor adder_r_in(i) xor adder_carry(i-1);
adder_carry(i) <= ((adder_d_in(i) xor adder_nadd_sub) and adder_r_in(i)) or
(((adder_d_in(i) xor adder_nadd_sub) or adder_r_in(i)) and adder_carry(i-1));
end generate;
-- FLAGS FOR ADDER INSTRUCTIONS:
-- CARRY FLAG (C) -> adder_out(8)
-- HALF CARRY FLAG (H) -> adder_carry(3)
-- TOW'S COMPLEMENT OVERFLOW (V) ->
adder_v_flag_out <= (((adder_d_in(7) and adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and not adder_r_in(7) and adder_out(7))) and not adder_nadd_sub) or -- ADD
(((adder_d_in(7) and not adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and adder_r_in(7) and adder_out(7))) and adder_nadd_sub);
-- SUB
--#####################################################################
-- LOGICAL OPERATIONS FOR ONE OPERAND
--########################## NEG OPERATION ####################
neg_op_out(0) <= not alu_data_d_in(0) xor '1';
neg_op_carry(0) <= not alu_data_d_in(0) and '1';
neg_op:for i in 1 to 7 generate
neg_op_out(i) <= not alu_data_d_in(i) xor neg_op_carry(i-1);
neg_op_carry(i) <= not alu_data_d_in(i) and neg_op_carry(i-1);
end generate;
neg_op_out(8) <= neg_op_carry(7) xor '1';
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
-- CARRY FLAGS FOR NEG INSTRUCTION:
-- CARRY FLAG -> neg_op_out(8)
-- HALF CARRY FLAG -> neg_op_carry(3)
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
--############################################################################
--########################## INC, DEC OPERATIONS ####################
incdec_op_out(0) <= alu_data_d_in(0) xor '1';
incdec_op_carry(0) <= alu_data_d_in(0) xor idc_dec;
inc_dec:for i in 1 to 7 generate
incdec_op_out(i) <= alu_data_d_in(i) xor incdec_op_carry(i-1);
incdec_op_carry(i) <= (alu_data_d_in(i) xor idc_dec) and incdec_op_carry(i-1);
end generate;
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
--####################################################################
--########################## COM OPERATION ###################################
com_op_out <= not alu_data_d_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
-- CARRY FLAG (C) -> '1'
--############################################################################
-- LOGICAL OPERATIONS FOR TWO OPERANDS
--########################## AND OPERATION ###################################
and_op_out <= alu_data_d_in and alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## OR OPERATION ###################################
or_op_out <= alu_data_d_in or alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## EOR OPERATION ###################################
eor_op_out <= alu_data_d_in xor alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
-- SHIFT OPERATIONS
-- ########################## RIGHT(LSR, ROR, ASR) #######################
right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
shift_right:for i in 6 downto 0 generate
right_shift_out(i) <= alu_data_d_in(i+1);
end generate;
-- FLAGS
-- CARRY FLAG (C) -> alu_data_d_in(0)
-- NEGATIVE FLAG (N) -> right_shift_out(7)
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
-- #######################################################################
-- ################################## SWAP ###############################
swap_h:for i in 7 downto 4 generate
swap_out(i) <= alu_data_d_in(i-4);
end generate;
swap_l:for i in 3 downto 0 generate
swap_out(i) <= alu_data_d_in(i+4);
end generate;
-- #######################################################################
-- ALU OUTPUT MUX
alu_data_out_mux:for i in alu_data_out_int'range generate
alu_data_out_int(i) <= (adder_out(i) and (idc_add or idc_adc or (idc_adiw or adiw_st) or -- !!!!!
idc_sub or idc_subi or idc_sbc or idc_sbci or
(idc_sbiw or sbiw_st) or -- !!!!!
idc_cpse or idc_cp or idc_cpc or idc_cpi)) or
(neg_op_out(i) and idc_neg) or -- NEG
(incdec_op_out(i) and (idc_inc or idc_dec)) or -- INC/DEC
(com_op_out(i) and idc_com) or -- COM
(and_op_out(i) and (idc_and or idc_andi)) or -- AND/ANDI
(or_op_out(i) and (idc_or or idc_ori)) or -- OR/ORI
(eor_op_out(i) and idc_eor) or -- EOR
(right_shift_out(i) and (idc_lsr or idc_ror or idc_asr)) or -- LSR/ROR/ASR
(swap_out(i) and idc_swap); -- SWAP
end generate;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
alu_h_flag_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_cp or idc_cpc or idc_cpi)) or
(not neg_op_carry(3) and idc_neg); -- H-flag problem with NEG instruction fixing -- NEG
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
alu_v_flag_out_int <= (adder_v_flag_out and
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or adiw_st or sbiw_st or idc_cp or idc_cpi or idc_cpc)) or
((alu_data_d_in(7) and neg_op_carry(6)) and idc_neg) or -- NEG
(not alu_data_d_in(7) and incdec_op_carry(6) and idc_inc) or -- INC
(alu_data_d_in(7) and incdec_op_carry(6) and idc_dec) or -- DEC
((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr or idc_ror or idc_asr)); -- LSR,ROR,ASR
alu_n_flag_out_int <= alu_data_out_int(7);
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
alu_c_flag_out_int <= (adder_out(8) and
(idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi)) or -- ADDER
(not alu_z_flag_out_int and idc_neg) or -- NEG
(alu_data_d_in(0) and (idc_lsr or idc_ror or idc_asr)) or idc_com;
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
end rtl;
|
--************************************************************************************************
-- ALU(internal module) for AVR core
-- Version 1.2
-- Designed by Ruslan Lepetenok
-- Modified 02.08.2003
-- (CPC/SBC/SBCI Z-flag bug found)
-- H-flag with NEG instruction found
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_avr is port(
alu_data_r_in : in std_logic_vector(7 downto 0);
alu_data_d_in : in std_logic_vector(7 downto 0);
alu_c_flag_in : in std_logic;
alu_z_flag_in : in std_logic;
-- OPERATION SIGNALS INPUTS
idc_add :in std_logic;
idc_adc :in std_logic;
idc_adiw :in std_logic;
idc_sub :in std_logic;
idc_subi :in std_logic;
idc_sbc :in std_logic;
idc_sbci :in std_logic;
idc_sbiw :in std_logic;
adiw_st : in std_logic;
sbiw_st : in std_logic;
idc_and :in std_logic;
idc_andi :in std_logic;
idc_or :in std_logic;
idc_ori :in std_logic;
idc_eor :in std_logic;
idc_com :in std_logic;
idc_neg :in std_logic;
idc_inc :in std_logic;
idc_dec :in std_logic;
idc_cp :in std_logic;
idc_cpc :in std_logic;
idc_cpi :in std_logic;
idc_cpse :in std_logic;
idc_lsr :in std_logic;
idc_ror :in std_logic;
idc_asr :in std_logic;
idc_swap :in std_logic;
-- DATA OUTPUT
alu_data_out : out std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : out std_logic;
alu_z_flag_out : out std_logic;
alu_n_flag_out : out std_logic;
alu_v_flag_out : out std_logic;
alu_s_flag_out : out std_logic;
alu_h_flag_out : out std_logic
);
end alu_avr;
architecture rtl of alu_avr is
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
signal alu_data_out_int : std_logic_vector (7 downto 0);
-- ALU FLAGS (INTERNAL)
signal alu_z_flag_out_int : std_logic;
signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
signal alu_n_flag_out_int : std_logic;
signal alu_v_flag_out_int : std_logic;
signal alu_c_flag_out_int : std_logic;
-- ADDER SIGNALS --
signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
signal adder_v_flag_out : std_logic;
signal adder_carry : std_logic_vector(8 downto 0);
signal adder_d_in : std_logic_vector(8 downto 0);
signal adder_r_in : std_logic_vector(8 downto 0);
signal adder_out : std_logic_vector(8 downto 0);
-- NEG OPERATOR SIGNALS
signal neg_op_in : std_logic_vector(7 downto 0);
signal neg_op_carry : std_logic_vector(8 downto 0);
signal neg_op_out : std_logic_vector(8 downto 0);
-- INC, DEC OPERATOR SIGNALS
signal incdec_op_in : std_logic_vector (7 downto 0);
signal incdec_op_carry : std_logic_vector(7 downto 0);
signal incdec_op_out : std_logic_vector(7 downto 0);
signal com_op_out : std_logic_vector(7 downto 0);
signal and_op_out : std_logic_vector(7 downto 0);
signal or_op_out : std_logic_vector(7 downto 0);
signal eor_op_out : std_logic_vector(7 downto 0);
-- SHIFT SIGNALS
signal right_shift_out : std_logic_vector(7 downto 0);
-- SWAP SIGNALS
signal swap_out : std_logic_vector(7 downto 0);
begin
-- ########################################################################
-- ############### ALU
-- ########################################################################
adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or
idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-'
-- SREG C FLAG (ALU INPUT)
alu_c_flag_in_int <= alu_c_flag_in and
(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
idc_cpc or
idc_ror);
-- SREG Z FLAG ()
-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st or idc_cpc or idc_sbc or idc_sbci)) or
((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st))or
(alu_z_flag_in and alu_z_flag_out_int and(idc_cpc or idc_sbc or idc_sbci)); -- Previous value (for CPC/SBC/SBCI instructions)
-- SREG N FLAG
alu_n_flag_out <= alu_n_flag_out_int;
-- SREG V FLAG
alu_v_flag_out <= alu_v_flag_out_int;
alu_c_flag_out <= alu_c_flag_out_int;
alu_data_out <= alu_data_out_int;
-- #########################################################################################
adder_d_in <= '0'&alu_data_d_in;
adder_r_in <= '0'&alu_data_r_in;
--########################## ADDEER ###################################
adder_out(0) <= adder_d_in(0) xor adder_r_in(0) xor alu_c_flag_in_int;
adder_carry(0) <= ((adder_d_in(0) xor adder_nadd_sub) and adder_r_in(0)) or
(((adder_d_in(0) xor adder_nadd_sub) or adder_r_in(0)) and alu_c_flag_in_int);
summator:for i in 1 to 8 generate
adder_out(i) <= adder_d_in(i) xor adder_r_in(i) xor adder_carry(i-1);
adder_carry(i) <= ((adder_d_in(i) xor adder_nadd_sub) and adder_r_in(i)) or
(((adder_d_in(i) xor adder_nadd_sub) or adder_r_in(i)) and adder_carry(i-1));
end generate;
-- FLAGS FOR ADDER INSTRUCTIONS:
-- CARRY FLAG (C) -> adder_out(8)
-- HALF CARRY FLAG (H) -> adder_carry(3)
-- TOW'S COMPLEMENT OVERFLOW (V) ->
adder_v_flag_out <= (((adder_d_in(7) and adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and not adder_r_in(7) and adder_out(7))) and not adder_nadd_sub) or -- ADD
(((adder_d_in(7) and not adder_r_in(7) and not adder_out(7)) or
(not adder_d_in(7) and adder_r_in(7) and adder_out(7))) and adder_nadd_sub);
-- SUB
--#####################################################################
-- LOGICAL OPERATIONS FOR ONE OPERAND
--########################## NEG OPERATION ####################
neg_op_out(0) <= not alu_data_d_in(0) xor '1';
neg_op_carry(0) <= not alu_data_d_in(0) and '1';
neg_op:for i in 1 to 7 generate
neg_op_out(i) <= not alu_data_d_in(i) xor neg_op_carry(i-1);
neg_op_carry(i) <= not alu_data_d_in(i) and neg_op_carry(i-1);
end generate;
neg_op_out(8) <= neg_op_carry(7) xor '1';
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
-- CARRY FLAGS FOR NEG INSTRUCTION:
-- CARRY FLAG -> neg_op_out(8)
-- HALF CARRY FLAG -> neg_op_carry(3)
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
--############################################################################
--########################## INC, DEC OPERATIONS ####################
incdec_op_out(0) <= alu_data_d_in(0) xor '1';
incdec_op_carry(0) <= alu_data_d_in(0) xor idc_dec;
inc_dec:for i in 1 to 7 generate
incdec_op_out(i) <= alu_data_d_in(i) xor incdec_op_carry(i-1);
incdec_op_carry(i) <= (alu_data_d_in(i) xor idc_dec) and incdec_op_carry(i-1);
end generate;
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
--####################################################################
--########################## COM OPERATION ###################################
com_op_out <= not alu_data_d_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
-- CARRY FLAG (C) -> '1'
--############################################################################
-- LOGICAL OPERATIONS FOR TWO OPERANDS
--########################## AND OPERATION ###################################
and_op_out <= alu_data_d_in and alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## OR OPERATION ###################################
or_op_out <= alu_data_d_in or alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
--########################## EOR OPERATION ###################################
eor_op_out <= alu_data_d_in xor alu_data_r_in;
-- FLAGS
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
--############################################################################
-- SHIFT OPERATIONS
-- ########################## RIGHT(LSR, ROR, ASR) #######################
right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
shift_right:for i in 6 downto 0 generate
right_shift_out(i) <= alu_data_d_in(i+1);
end generate;
-- FLAGS
-- CARRY FLAG (C) -> alu_data_d_in(0)
-- NEGATIVE FLAG (N) -> right_shift_out(7)
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
-- #######################################################################
-- ################################## SWAP ###############################
swap_h:for i in 7 downto 4 generate
swap_out(i) <= alu_data_d_in(i-4);
end generate;
swap_l:for i in 3 downto 0 generate
swap_out(i) <= alu_data_d_in(i+4);
end generate;
-- #######################################################################
-- ALU OUTPUT MUX
alu_data_out_mux:for i in alu_data_out_int'range generate
alu_data_out_int(i) <= (adder_out(i) and (idc_add or idc_adc or (idc_adiw or adiw_st) or -- !!!!!
idc_sub or idc_subi or idc_sbc or idc_sbci or
(idc_sbiw or sbiw_st) or -- !!!!!
idc_cpse or idc_cp or idc_cpc or idc_cpi)) or
(neg_op_out(i) and idc_neg) or -- NEG
(incdec_op_out(i) and (idc_inc or idc_dec)) or -- INC/DEC
(com_op_out(i) and idc_com) or -- COM
(and_op_out(i) and (idc_and or idc_andi)) or -- AND/ANDI
(or_op_out(i) and (idc_or or idc_ori)) or -- OR/ORI
(eor_op_out(i) and idc_eor) or -- EOR
(right_shift_out(i) and (idc_lsr or idc_ror or idc_asr)) or -- LSR/ROR/ASR
(swap_out(i) and idc_swap); -- SWAP
end generate;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
alu_h_flag_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or idc_cp or idc_cpc or idc_cpi)) or
(not neg_op_carry(3) and idc_neg); -- H-flag problem with NEG instruction fixing -- NEG
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
alu_v_flag_out_int <= (adder_v_flag_out and
(idc_add or idc_adc or idc_sub or idc_subi or idc_sbc or idc_sbci or adiw_st or sbiw_st or idc_cp or idc_cpi or idc_cpc)) or
((alu_data_d_in(7) and neg_op_carry(6)) and idc_neg) or -- NEG
(not alu_data_d_in(7) and incdec_op_carry(6) and idc_inc) or -- INC
(alu_data_d_in(7) and incdec_op_carry(6) and idc_dec) or -- DEC
((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr or idc_ror or idc_asr)); -- LSR,ROR,ASR
alu_n_flag_out_int <= alu_data_out_int(7);
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
alu_c_flag_out_int <= (adder_out(8) and
(idc_add or idc_adc or (idc_adiw or adiw_st) or idc_sub or idc_subi or idc_sbc or idc_sbci or (idc_sbiw or sbiw_st) or idc_cp or idc_cpc or idc_cpi)) or -- ADDER
(not alu_z_flag_out_int and idc_neg) or -- NEG
(alu_data_d_in(0) and (idc_lsr or idc_ror or idc_asr)) or idc_com;
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
end rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(7 DOWNTO 0) <= WRITE_ADDR(7 DOWNTO 0);
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(7 DOWNTO 0) <= WRITE_ADDR(7 DOWNTO 0);
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2014
-- Module Name: MUX_2to1
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: 2 Select MUX
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_2to1 is
Port ( SEL : in STD_LOGIC;
IN_1 : in STD_LOGIC;
IN_2 : in STD_LOGIC;
MOUT : out STD_LOGIC);
end mux_2to1;
architecture Behavioral of mux_2to1 is
begin
MOUT <= IN_1 when SEL='0' ELSE IN_2;
end Behavioral;
|
----------------------------------------------------------------------------------
--
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Michael J. Wouters
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OneShot is
Port ( trigger : in STD_LOGIC;
clk : in STD_LOGIC;
pulse : out STD_LOGIC);
end OneShot;
architecture Behavioral of OneShot is
signal QA: std_logic := '0';
signal QB: std_logic := '0';
begin
pulse <= QB;
process (trigger, QB)
begin
if QB='1' then
QA <= '0';
elsif (rising_edge(trigger)) then
QA <= '1';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
QB <= QA;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package TRIGGERS is
component OneShot is port (
trigger : in STD_LOGIC;
clk : in STD_LOGIC;
pulse : out STD_LOGIC);
end component;
end TRIGGERS;
|
-------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
library micron;
use micron.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(1 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>4, lddelay => 15 us)
port map (ck => mcb3_dram_ck, cke => mcb3_dram_cke, csn => csb,
rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a,
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux8x2 is
port(
in0: in unsigned(15 downto 0);
in1: in unsigned(15 downto 0);
in2: in unsigned(15 downto 0);
in3: in unsigned(15 downto 0);
in4: in unsigned(15 downto 0);
in5: in unsigned(15 downto 0);
in6: in unsigned(15 downto 0);
in7: in unsigned(15 downto 0);
sel0: in unsigned(2 downto 0);
sel1: in unsigned(2 downto 0);
out0: out unsigned(15 downto 0);
out1: out unsigned(15 downto 0)
);
end entity;
architecture a_mux8x2 of mux8x2 is
begin
out0 <= in0 when sel0="000" else
in1 when sel0="001" else
in2 when sel0="010" else
in3 when sel0="011" else
in4 when sel0="100" else
in5 when sel0="101" else
in6 when sel0="110" else
in7 when sel0="111" else
"----------------";
out1 <= in0 when sel1="000" else
in1 when sel1="001" else
in2 when sel1="010" else
in3 when sel1="011" else
in4 when sel1="100" else
in5 when sel1="101" else
in6 when sel1="110" else
in7 when sel1="111" else
"----------------";
end architecture;
|
-- $Id: tb_tst_rlink_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_n2
-- Description: Configuration for tb_tst_rlink_n2 for tb_nexys2_fusp
--
-- Dependencies: sys_tst_rlink_n2
--
-- To test: sys_tst_rlink_n2
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_n2 of tb_nexys2_fusp is
for sim
for all : nexys2_fusp_aif
use entity work.sys_tst_rlink_n2;
end for;
end for;
end tb_tst_rlink_n2;
|
library verilog;
use verilog.vl_types.all;
entity arm_alu is
port(
alu_or_mac : in vl_logic;
alu_op1 : in vl_logic_vector(31 downto 0);
alu_op2 : in vl_logic_vector(31 downto 0);
alu_sel : in vl_logic_vector(3 downto 0);
alu_cin : in vl_logic;
is_alu_for_mem_addr: in vl_logic;
up_down : in vl_logic;
potential_cout : in vl_logic;
alu_out : out vl_logic_vector(31 downto 0);
alu_cpsr : out vl_logic_vector(3 downto 0)
);
end arm_alu;
|
---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit signal output corresponding to the hex digit
Segments : out std_logic_vector (7 downto 0)
);
end Hex2SSeg;
architecture decode of Hex2SSeg is
begin
with HexChar select
Segments <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"10001000" when "1010", -- A
"10000011" when "1011", -- b
"11000110" when "1100", -- C
"10100001" when "1101", -- d
"10000110" when "1110", -- E
"10001110" when others; -- F
end decode;
|
---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit signal output corresponding to the hex digit
Segments : out std_logic_vector (7 downto 0)
);
end Hex2SSeg;
architecture decode of Hex2SSeg is
begin
with HexChar select
Segments <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"10001000" when "1010", -- A
"10000011" when "1011", -- b
"11000110" when "1100", -- C
"10100001" when "1101", -- d
"10000110" when "1110", -- E
"10001110" when others; -- F
end decode;
|
---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit signal output corresponding to the hex digit
Segments : out std_logic_vector (7 downto 0)
);
end Hex2SSeg;
architecture decode of Hex2SSeg is
begin
with HexChar select
Segments <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"10001000" when "1010", -- A
"10000011" when "1011", -- b
"11000110" when "1100", -- C
"10100001" when "1101", -- d
"10000110" when "1110", -- E
"10001110" when others; -- F
end decode;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tl_car_bench is
port(
db_clk: in std_logic;
db_reset: in std_logic;
db_switches: in std_logic_vector(3 downto 0);
db_leds: out std_logic_vector(7 downto 0);
--
l_lvds_io: inout std_logic;
r_lvds_io: inout std_logic;
--
i2s1_sck: out std_logic;
i2s1_ws: out std_logic;
i2s1_d0: in std_logic;
i2s1_d1: in std_logic;
i2s2_sck: out std_logic;
i2s2_ws: out std_logic;
i2s2_d0: out std_logic;
i2s2_d1: out std_logic;
--
spi1_clk: in std_logic;
spi1_mosi: in std_logic;
spi1_miso: out std_logic;
spi1_cs0: in std_logic;
spi1_cs2: in std_logic;
spi3_clk: in std_logic;
spi3_mosi: in std_logic;
spi3_miso: out std_logic;
spi3_cs0: in std_logic;
spi3_cs3: in std_logic;
--
test_lrst_pre, test_djb_present: out std_logic
);
end entity;
architecture a of tl_car_bench is
component pll_4_usb is
port(
CLKI, RST: in std_logic;
CLKOP: out std_logic
);
end component;
component car_clock_gen is
port(
hr_clk, reset: in std_logic;
main_clk, seq_reset, i2s_ws: out std_logic
);
end component;
component car_core is
port(
main_clk, reset, seq_reset, i2s_ws: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_sclk: out std_logic;
i2s_dspk: in std_logic;
i2s_dmic: out std_logic;
--
spi_sck: in std_logic;
spi_mosi: in std_logic;
spi_miso: out std_logic;
spi_cs0: in std_logic;
spi_cs1: in std_logic;
--
test_lrst_pre, test_djb_present: out std_logic
);
end component;
signal hr_clk, main_clk, int_reset, seq_reset: std_logic;
signal i2s_sck, i2s_ws: std_logic;
begin
db_leds(3 downto 0) <= db_switches;
db_leds(4) <= db_clk;
db_leds(5) <= i2s1_d1;
db_leds(6) <= '0';
db_leds(7) <= '1';
int_reset <= not db_reset;
i2s1_sck <= i2s_sck;
i2s2_sck <= i2s_sck;
i2s1_ws <= i2s_ws;
i2s2_ws <= i2s_ws;
-- 48 kHz sampling * 2 channels * 32 bits = 3.072 MHz I2S bit clock
-- LVDS bit clock = 4x I2S bit clock = 12.288 MHz
-- hr_clk = 4x LVDS bit clock = 49.152 MHz
-- External clock is 12.000 MHz from USB
e_pll_4: pll_4_usb port map (
CLKI => db_clk,
RST => int_reset,
CLKOP => hr_clk
);
e_car_clock_gen: car_clock_gen port map (
hr_clk => hr_clk, reset => int_reset,
main_clk => main_clk, seq_reset => seq_reset, i2s_ws => i2s_ws
);
l_car_core: car_core port map (
main_clk => main_clk, reset => int_reset, seq_reset => seq_reset, i2s_ws => i2s_ws,
lvds_io => l_lvds_io,
i2s_sclk => i2s_sck, i2s_dmic => i2s2_d0, i2s_dspk => i2s1_d0,
spi_sck => spi1_clk,
spi_mosi => spi1_mosi,
spi_miso => spi1_miso,
spi_cs0 => spi1_cs0,
spi_cs1 => spi1_cs2,
test_lrst_pre => open, test_djb_present => open
);
r_car_core: car_core port map (
main_clk => main_clk, reset => int_reset, seq_reset => seq_reset, i2s_ws => i2s_ws,
lvds_io => r_lvds_io,
i2s_sclk => open, i2s_dmic => i2s2_d1, i2s_dspk => i2s1_d0,
spi_sck => spi3_clk,
spi_mosi => spi3_mosi,
spi_miso => spi3_miso,
spi_cs0 => spi3_cs0,
spi_cs1 => spi3_cs3,
test_lrst_pre => test_lrst_pre, test_djb_present => test_djb_present
);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc579.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:49 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:13 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00579ent IS
END c03s04b01x00p01n01i00579ent;
ARCHITECTURE c03s04b01x00p01n01i00579arch OF c03s04b01x00p01n01i00579ent IS
type positive_file is file of positive;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_file open read_mode is "iofile.18";
variable v : positive;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00579"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00579 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00579arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc579.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:49 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:13 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00579ent IS
END c03s04b01x00p01n01i00579ent;
ARCHITECTURE c03s04b01x00p01n01i00579arch OF c03s04b01x00p01n01i00579ent IS
type positive_file is file of positive;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_file open read_mode is "iofile.18";
variable v : positive;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00579"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00579 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00579arch;
|
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