content stringlengths 1 1.04M ⌀ |
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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc579.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:49 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:13 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00579ent IS
END c03s04b01x00p01n01i00579ent;
ARCHITECTURE c03s04b01x00p01n01i00579arch OF c03s04b01x00p01n01i00579ent IS
type positive_file is file of positive;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_file open read_mode is "iofile.18";
variable v : positive;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00579"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00579 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00579arch;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_buffer_addressable - Structural
-- Description: Outputs counterclockwise rotation over time
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity affine_rotation_generator is
port(
clk_25 : in std_logic;
reset : in std_logic;
-- IEEE 754 floating point 2x2 rotation matrix
a00 : out std_logic_vector(31 downto 0);
a01 : out std_logic_vector(31 downto 0);
a10 : out std_logic_vector(31 downto 0);
a11 : out std_logic_vector(31 downto 0)
);
end affine_rotation_generator;
architecture Structural of affine_rotation_generator is
begin
process(clk_25)
variable counter : integer := 0;
variable angle : integer := 0;
variable cosine : std_logic_vector(31 downto 0);
variable sine : std_logic_vector(31 downto 0);
begin
if rising_edge(clk_25) then
if reset = '1' then
counter := 0;
angle := 0;
else
counter := counter + 1;
if counter >= 25000000 then
counter := 0;
angle := angle + 4;
if angle >= 90 then
angle := 0;
end if;
end if;
end if;
if angle = 0 then
cosine := x"00000000";
sine := x"3f800000";
elsif angle = 4 then
cosine := x"3f7f605c";
sine := x"3d8edc7b";
elsif angle = 8 then
cosine := x"3f7d8235";
sine := x"3e0e8365";
elsif angle = 12 then
cosine := x"3f7a67e2";
sine := x"3e54e6cd";
elsif angle = 16 then
cosine := x"3f76153f";
sine := x"3e8d2057";
elsif angle = 20 then
cosine := x"3f708fb2";
sine := x"3eaf1d44";
elsif angle = 24 then
cosine := x"3f69de1d";
sine := x"3ed03fc9";
elsif angle = 28 then
cosine := x"3f6208da";
sine := x"3ef05e94";
elsif angle = 32 then
cosine := x"3f5919ae";
sine := x"3f07a8ca";
elsif angle = 36 then
cosine := x"3f4f1bbd";
sine := x"3f167918";
elsif angle = 40 then
cosine := x"3f441b7d";
sine := x"3f248dbb";
elsif angle = 44 then
cosine := x"3f3826a7";
sine := x"3f31d522";
elsif angle = 48 then
cosine := x"3f2b4c25";
sine := x"3f3e3ebd";
elsif angle = 52 then
cosine := x"3f1d9bfe";
sine := x"3f49bb13";
elsif angle = 56 then
cosine := x"3f0f2744";
sine := x"3f543bce";
elsif angle = 60 then
cosine := x"3f000000";
sine := x"3f5db3d7";
elsif angle = 64 then
cosine := x"3ee0722f";
sine := x"3f66175e";
elsif angle = 68 then
cosine := x"3ebfcc6f";
sine := x"3f6d5bec";
elsif angle = 72 then
cosine := x"3e9e377a";
sine := x"3f737871";
elsif angle = 76 then
cosine := x"3e77ba60";
sine := x"3f78654d";
elsif angle = 80 then
cosine := x"3e31d0d4";
sine := x"3f7c1c5c";
elsif angle = 84 then
cosine := x"3dd61305";
sine := x"3f7e98fd";
elsif angle = 88 then
cosine := x"3d0ef2c6";
sine := x"3f7fd814";
end if;
a00 <= cosine;
a01(31) <= not sine(31);
a01(30 downto 0) <= sine(30 downto 0);
a10 <= sine;
a11 <= cosine;
end if;
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_buffer_addressable - Structural
-- Description: Outputs counterclockwise rotation over time
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity affine_rotation_generator is
port(
clk_25 : in std_logic;
reset : in std_logic;
-- IEEE 754 floating point 2x2 rotation matrix
a00 : out std_logic_vector(31 downto 0);
a01 : out std_logic_vector(31 downto 0);
a10 : out std_logic_vector(31 downto 0);
a11 : out std_logic_vector(31 downto 0)
);
end affine_rotation_generator;
architecture Structural of affine_rotation_generator is
begin
process(clk_25)
variable counter : integer := 0;
variable angle : integer := 0;
variable cosine : std_logic_vector(31 downto 0);
variable sine : std_logic_vector(31 downto 0);
begin
if rising_edge(clk_25) then
if reset = '1' then
counter := 0;
angle := 0;
else
counter := counter + 1;
if counter >= 25000000 then
counter := 0;
angle := angle + 4;
if angle >= 90 then
angle := 0;
end if;
end if;
end if;
if angle = 0 then
cosine := x"00000000";
sine := x"3f800000";
elsif angle = 4 then
cosine := x"3f7f605c";
sine := x"3d8edc7b";
elsif angle = 8 then
cosine := x"3f7d8235";
sine := x"3e0e8365";
elsif angle = 12 then
cosine := x"3f7a67e2";
sine := x"3e54e6cd";
elsif angle = 16 then
cosine := x"3f76153f";
sine := x"3e8d2057";
elsif angle = 20 then
cosine := x"3f708fb2";
sine := x"3eaf1d44";
elsif angle = 24 then
cosine := x"3f69de1d";
sine := x"3ed03fc9";
elsif angle = 28 then
cosine := x"3f6208da";
sine := x"3ef05e94";
elsif angle = 32 then
cosine := x"3f5919ae";
sine := x"3f07a8ca";
elsif angle = 36 then
cosine := x"3f4f1bbd";
sine := x"3f167918";
elsif angle = 40 then
cosine := x"3f441b7d";
sine := x"3f248dbb";
elsif angle = 44 then
cosine := x"3f3826a7";
sine := x"3f31d522";
elsif angle = 48 then
cosine := x"3f2b4c25";
sine := x"3f3e3ebd";
elsif angle = 52 then
cosine := x"3f1d9bfe";
sine := x"3f49bb13";
elsif angle = 56 then
cosine := x"3f0f2744";
sine := x"3f543bce";
elsif angle = 60 then
cosine := x"3f000000";
sine := x"3f5db3d7";
elsif angle = 64 then
cosine := x"3ee0722f";
sine := x"3f66175e";
elsif angle = 68 then
cosine := x"3ebfcc6f";
sine := x"3f6d5bec";
elsif angle = 72 then
cosine := x"3e9e377a";
sine := x"3f737871";
elsif angle = 76 then
cosine := x"3e77ba60";
sine := x"3f78654d";
elsif angle = 80 then
cosine := x"3e31d0d4";
sine := x"3f7c1c5c";
elsif angle = 84 then
cosine := x"3dd61305";
sine := x"3f7e98fd";
elsif angle = 88 then
cosine := x"3d0ef2c6";
sine := x"3f7fd814";
end if;
a00 <= cosine;
a01(31) <= not sine(31);
a01(30 downto 0) <= sine(30 downto 0);
a10 <= sine;
a11 <= cosine;
end if;
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10.02.2017 11:21:03
-- Design Name:
-- Module Name: ClockManager - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ClockManager is
Port ( CLK : in STD_LOGIC;
CLK_btn_fast : in STD_LOGIC;
CLK_btn_once : in STD_LOGIC;
V_sync : in STD_LOGIC;
CLK_gol : out STD_LOGIC);
end ClockManager;
architecture Behavioral of ClockManager is
signal A : integer := 0;
begin
process(V_sync, CLK_btn_fast, CLK_btn_once, CLK, A)
begin
if V_sync = '1' then
if CLK_btn_fast = '1' then
A <= A + 1;
-- elsif CLK_btn_once = '1' then
-- A<=11;
end if;
elsif CLK'event and CLK = '1' then
if A>10 then
A <= 0;
CLK_gol <= '1';
else
CLK_gol <= '0';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v3_00_a;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the L_PicoBlaze namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_TEXTIO.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
package pb is
constant PB_VERBOSE : BOOLEAN := FALSE; -- POC_VERBOSE;
constant PB_REPORT : BOOLEAN := FALSE;
subtype T_PB_ADDRESS is STD_LOGIC_VECTOR(11 downto 0);
subtype T_PB_INSTRUCTION is STD_LOGIC_VECTOR(17 downto 0);
-- PicoBlaze I/O bus
type T_PB_IOBUS_PB_DEV is record
PortID : T_SLV_8;
Data : T_SLV_8;
WriteStrobe : STD_LOGIC;
WriteStrobe_K : STD_LOGIC;
ReadStrobe : STD_LOGIC;
Interrupt_Ack : STD_LOGIC;
end record;
type T_PB_IOBUS_DEV_PB is record
Data : T_SLV_8;
Interrupt : STD_LOGIC;
Message : T_SLV_8;
end record;
type T_PB_IOBUS_PB_DEV_VECTOR is array(NATURAL range <>) of T_PB_IOBUS_PB_DEV;
type T_PB_IOBUS_DEV_PB_VECTOR is array(NATURAL range <>) of T_PB_IOBUS_DEV_PB;
constant T_PB_IOBUS_PB_DEV_Z : T_PB_IOBUS_PB_DEV := ((others => 'Z'), (others => 'Z'), others => 'Z');
constant T_PB_IOBUS_DEV_PB_Z : T_PB_IOBUS_DEV_PB := ((others => 'Z'), 'Z', (others => 'Z'));
-- private functions (must be declared public to be useable in public constants)
-- ===========================================================================
-- constant C_PB_MAX_LONGNAME_LENGTH : POSITIVE := 64;
constant C_PB_MAX_SHORTNAME_LENGTH : POSITIVE := 32;
-- subtype T_PB_LONGNAME is STRING(1 to C_PB_MAX_LONGNAME_LENGTH);
subtype T_PB_SHORTNAME is STRING(1 to C_PB_MAX_SHORTNAME_LENGTH);
type T_PB_SHORTNAME_VECTOR is array(NATURAL range <>) of T_PB_SHORTNAME;
-- constant C_PB_LONGNAME_EMPTY : T_PB_LONGNAME := (others => C_POC_NUL);
constant C_PB_SHORTNAME_EMPTY : T_PB_SHORTNAME := (others => C_POC_NUL);
-- function pb_LongName(name : string) return T_PB_LONGNAME ;
function pb_ShortName(name : string) return T_PB_SHORTNAME;
-- PicoBlaze device description
constant C_PB_MAX_REGISTER_FIELDS : POSITIVE := 32;
constant C_PB_MAX_REGISTERS : POSITIVE := 32;
constant C_PB_MAX_REGISTER_FIELD_MAPPINGS : POSITIVE := 32;
constant C_PB_MAX_MAPPINGS : POSITIVE := 32;
constant C_PB_MAX_DEVICES : POSITIVE := 32;
constant C_PB_MAX_BUSSES : POSITIVE := 12;
subtype T_PB_REGISTER_FIELD_INDEX is NATURAL range 0 to (C_PB_MAX_REGISTER_FIELDS - 1);
subtype T_PB_REGISTER_INDEX is NATURAL range 0 to (C_PB_MAX_REGISTERS - 1);
subtype T_PB_REGISTER_FIELD_MAPPING_INDEX is NATURAL range 0 to (C_PB_MAX_REGISTER_FIELD_MAPPINGS - 1);
subtype T_PB_PORTNUMBER_MAPPING_INDEX is NATURAL range 0 to (C_PB_MAX_MAPPINGS - 1);
subtype T_PB_DEVICE_INSTANCE_INDEX is NATURAL range 0 to (C_PB_MAX_DEVICES - 1);
subtype T_PB_BUS_INDEX is NATURAL range 0 to (C_PB_MAX_BUSSES - 1);
type T_PB_REGISTER_FIELD_KIND is (PB_REGISTER_FIELD_KIND_READ, PB_REGISTER_FIELD_KIND_WRITE, PB_REGISTER_FIELD_KIND_READWRITE);
type T_PB_REGISTER_FIELD is record
FieldID : T_UINT_8;
-- FieldName : T_PB_LONGNAME;
FieldShort : T_PB_SHORTNAME;
Length : T_UINT_8;
AutoClear : BOOLEAN;
FieldKind : T_PB_REGISTER_FIELD_KIND;
Encoding : STRING(1 to 256);
end record;
constant C_PB_REGISTER_FIELD_EMPTY : T_PB_REGISTER_FIELD := (
FieldID => 0,
-- FieldName => C_PB_LONGNAME_EMPTY,
FieldShort => C_PB_SHORTNAME_EMPTY,
Length => 0,
AutoClear => FALSE,
FieldKind => PB_REGISTER_FIELD_KIND_READ,
Encoding => (others => C_POC_NUL)
);
type T_PB_REGISTER_FIELD_VECTOR is array(NATURAL range <>) of T_PB_REGISTER_FIELD;
type T_PB_REGISTER_FIELD_MAPPING_KIND is (PB_REGISTER_FIELD_MAPPING_KIND_READ, PB_REGISTER_FIELD_MAPPING_KIND_WRITE, PB_REGISTER_FIELD_MAPPING_KIND_WRITEK);
type T_PB_REGISTER_FIELD_GROUP is record
FieldShort : T_PB_SHORTNAME;
Offset : T_UINT_8;
MappingKind : T_PB_REGISTER_FIELD_MAPPING_KIND;
end record;
type T_PB_REGISTER_FIELD_GROUP_VECTOR is array(NATURAL range <>) of T_PB_REGISTER_FIELD_GROUP;
type T_PB_REGISTER_FIELD_MAPPING is record
FieldID : T_UINT_8;
Start : T_UINT_8;
Length : T_UINT_8;
MappingKind : T_PB_REGISTER_FIELD_MAPPING_KIND;
end record;
type T_PB_REGISTER_FIELD_MAPPING_VECTOR is array(NATURAL range <>) of T_PB_REGISTER_FIELD_MAPPING;
constant C_PB_REGISTER_FIELD_MAPPING_EMPTY : T_PB_REGISTER_FIELD_MAPPING := (
FieldID => 255,
Start => 0,
Length => 0,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ
);
type T_PB_REGISTER_KIND is (PB_REGISTER_KIND_READ, PB_REGISTER_KIND_WRITE, PB_REGISTER_KIND_READWRITE, PB_REGISTER_KIND_WRITEK);
type T_PB_REGISTER is record
-- RegisterName : T_PB_LONGNAME;
RegisterShort : T_PB_SHORTNAME;
RegisterNumber : T_UINT_8;
RegisterKind : T_PB_REGISTER_KIND;
FieldMappings : T_PB_REGISTER_FIELD_MAPPING_VECTOR(T_PB_REGISTER_FIELD_MAPPING_INDEX);
FieldMappingCount : T_UINT_8;
end record;
constant C_PB_REGISTER_EMPTY : T_PB_REGISTER := (
-- RegisterName => C_PB_LONGNAME_EMPTY,
RegisterShort => C_PB_SHORTNAME_EMPTY,
RegisterNumber => 255,
RegisterKind => PB_REGISTER_KIND_READ,
FieldMappings => (others => C_PB_REGISTER_FIELD_MAPPING_EMPTY),
FieldMappingCount => 0
);
type T_PB_REGISTER_VECTOR is array(NATURAL range <>) of T_PB_REGISTER;
type T_PB_DEVICE is record
-- DeviceName : T_PB_LONGNAME;
DeviceShort : T_PB_SHORTNAME;
Registers : T_PB_REGISTER_VECTOR(T_PB_REGISTER_INDEX);
RegisterCount : T_UINT_8;
RegisterFields : T_PB_REGISTER_FIELD_VECTOR(T_PB_REGISTER_FIELD_INDEX);
RegisterFieldCount : T_UINT_8;
CreatesInterrupt : BOOLEAN;
end record;
type T_PB_DEVICE_VECTOR is array (NATURAL range <>) of T_PB_DEVICE;
constant C_PB_DEVICE_EMPTY : T_PB_DEVICE := (
-- DeviceName => C_PB_LONGNAME_EMPTY,
DeviceShort => C_PB_SHORTNAME_EMPTY,
Registers => (others => C_PB_REGISTER_EMPTY),
RegisterCount => 0,
RegisterFields => (others => C_PB_REGISTER_FIELD_EMPTY),
RegisterFieldCount => 0,
CreatesInterrupt => FALSE
);
type T_PB_MAPPING_KIND is (PB_MAPPING_KIND_EMPTY, PB_MAPPING_KIND_WRITE, PB_MAPPING_KIND_WRITEK, PB_MAPPING_KIND_READ);
type T_PB_PORTNUMBER_MAPPING is record
PortNumber : T_UINT_8;
RegID : T_PB_REGISTER_INDEX;
RegNumber : T_UINT_8;
MappingKind : T_PB_MAPPING_KIND;
end record;
type T_PB_PORTNUMBER_MAPPING_VECTOR is array(NATURAL range <>) of T_PB_PORTNUMBER_MAPPING;
constant C_PB_PORTNUMBER_MAPPING_EMPTY : T_PB_PORTNUMBER_MAPPING := (
PortNumber => 0,
RegID => 0,
RegNumber => 0,
MappingKind => PB_MAPPING_KIND_EMPTY
);
type T_PB_DEVICE_INSTANCE is record
-- DeviceName : T_PB_LONGNAME;
DeviceShort : T_PB_SHORTNAME;
Device : T_PB_DEVICE;
BusShort : T_PB_SHORTNAME;
MappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
end record;
type T_PB_DEVICE_DESCRIPTION is record
DeviceShort : T_PB_SHORTNAME;
BusShort : T_PB_SHORTNAME;
ReadMappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
ReadMappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
WriteMappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
WriteMappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
WriteKMappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
WriteKMappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
end record;
type T_PB_DEVICE_INSTANCE_VECTOR is array (NATURAL range <>) of T_PB_DEVICE_INSTANCE;
constant C_PB_DEVICE_INSTANCE_EMPTY : T_PB_DEVICE_INSTANCE := (
-- DeviceName => C_PB_LONGNAME_EMPTY,
DeviceShort => C_PB_SHORTNAME_EMPTY,
Device => C_PB_DEVICE_EMPTY,
BusShort => C_PB_SHORTNAME_EMPTY,
MappingCount => 0,
Mappings => (others => C_PB_PORTNUMBER_MAPPING_EMPTY)
);
function pb_CreateReadonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD;
function pb_CreateWriteonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD;
function pb_CreateRegisterField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD;
function pb_EnumerateRegisterFields(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR) return T_PB_REGISTER_FIELD_VECTOR;
function pb_GetRegisterFieldID(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_UINT_8;
function pb_GetRegisterField(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_PB_REGISTER_FIELD;
function pb_CreateRegisterRO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER;
function pb_CreateRegisterRW(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR;
function pb_CreateRegisterWO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER;
function pb_CreateRegisterKO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER;
function pb_CreateRegisterWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR;
function pb_CreateRegisterRWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR;
function pb_CreateCombinedRegister(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_GROUP_VECTOR) return T_PB_REGISTER;
function pb_CreateDevice(DeviceName : STRING; DeviceShort : STRING; Registers : T_PB_REGISTER_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_VECTOR; CreatesInterrupt : BOOLEAN := FALSE) return T_PB_DEVICE;
function pb_CreateDeviceAlias(Device : T_PB_DEVICE; AliasName : STRING) return T_PB_DEVICE;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; InstanceNumber : T_UINT_8; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; NameLong : STRING; NameShort : STRING; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE;
function pb_GetDeviceInstance(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; NameShort : STRING) return T_PB_DEVICE_INSTANCE;
subtype T_PB_BUSID is NATURAL range 0 to 31;
subtype T_PB_DEVICEID is NATURAL range 0 to 127;
type T_PB_BUSID_VECTOR is array (NATURAL range <>) of T_PB_BUSID;
type T_PB_DEVICEID_VECTOR is array (NATURAL range <>) of T_PB_DEVICEID;
type T_PB_BUS is record
-- BusName : T_PB_LONGNAME;
BusShort : T_PB_SHORTNAME;
SuperBusShort : T_PB_SHORTNAME;
SuperBusID : T_PB_BUSID;
SubBusses : T_PB_BUSID_VECTOR(0 to 7);
SubBusCount : NATURAL range 0 to 8;
Devices : T_PB_DEVICEID_VECTOR(0 to 31);
DeviceCount : NATURAL range 0 to 32;
TotalDeviceCount : T_UINT_8;
end record;
type T_PB_BUS_VECTOR is array (NATURAL range <>) of T_PB_BUS;
constant C_PB_BUS_EMPTY : T_PB_BUS := (
-- BusName => C_PB_LONGNAME_EMPTY,
BusShort => C_PB_SHORTNAME_EMPTY,
SuperBusShort => C_PB_SHORTNAME_EMPTY,
SuperBusID => 0,
SubBusses => (others => 0),
SubBusCount => 0,
Devices => (others => 0),
DeviceCount => 0,
TotalDeviceCount => 0
);
function pb_CreateBus(BusName : STRING; BusShort : STRING; SuperBusShort : STRING) return T_PB_BUS;
function pb_ConnectBusses(Busses : T_PB_BUS_VECTOR) return T_PB_BUS_VECTOR;
type T_PB_SYSTEM is record
-- SystemName : T_PB_LONGNAME;
SystemShort : T_PB_SHORTNAME;
DeviceInstanceCount : T_PB_DEVICE_INSTANCE_INDEX;
DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR(T_PB_DEVICE_INSTANCE_INDEX);
BusCount : T_PB_BUS_INDEX;
Busses : T_PB_BUS_VECTOR(T_PB_BUS_INDEX);
end record;
function pb_CreateSystem(SystemName : STRING; SystemShort : STRING; Busses : T_PB_BUS_VECTOR; DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR) return T_PB_SYSTEM;
function pb_GetDeviceInstance(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_INSTANCE;
function pb_GetDeviceDescription(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_DESCRIPTION;
function pb_Resize(RegisterMapping : T_PB_REGISTER_FIELD_MAPPING; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR;
function pb_Resize(RegisterField : T_PB_REGISTER_FIELD; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR;
function pb_Resize(Reg : T_PB_REGISTER; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR;
function pb_ResizeVec(RegisterMappings : T_PB_REGISTER_FIELD_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR;
function pb_ResizeVec(RegisterFields : T_PB_REGISTER_FIELD_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR;
function pb_ResizeVec(Registers : T_PB_REGISTER_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR;
function pb_ResizeVec(Busses : T_PB_BUS_VECTOR; Size : NATURAL := 0) return T_PB_BUS_VECTOR;
function pb_ResizeVec(Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_PORTNUMBER_MAPPING_VECTOR;
function pb_ResizeVec(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; Size : NATURAL := 0) return T_PB_DEVICE_INSTANCE_VECTOR;
-- PicoBlaze interrupt functions
function pb_GetInterruptCount(System : T_PB_SYSTEM) return NATURAL;
function pb_GetInterruptPortIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL;
function pb_GetInterruptVector(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return STD_LOGIC_VECTOR;
function pb_GetInterruptMessages(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return T_SLVV_8;
procedure pb_AssignInterruptAck(signal Output : inout T_PB_IOBUS_PB_DEV_VECTOR; Input : STD_LOGIC_VECTOR; System : T_PB_SYSTEM);
-- PicoBlaze AddressDecoder functions
function pb_FilterMappings(DeviceInstance : T_PB_DEVICE_INSTANCE; MappingKind : T_PB_MAPPING_KIND) return T_PB_PORTNUMBER_MAPPING_VECTOR;
-- PicoBlaze bus functions
function pb_GetBusIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL;
function pb_GetBusWidth(System : T_PB_SYSTEM; BusShort : STRING) return NATURAL;
function pb_GetSubOrdinateBus(Input : T_PB_IOBUS_PB_DEV_VECTOR; System : T_PB_SYSTEM; BusShort : STRING) return T_PB_IOBUS_PB_DEV_VECTOR;
procedure pb_AssignSubOrdinateBus(signal Output : inout T_PB_IOBUS_DEV_PB_VECTOR; Input : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM; BusShort : STRING);
impure function pb_PrintAddressMapping(System : T_PB_SYSTEM) return BOOLEAN;
impure function pb_PrintBusses(System : T_PB_SYSTEM) return BOOLEAN;
impure function pb_ExportAddressMappingAsAssemblerConstants(System : T_PB_SYSTEM; psmFileName : STRING) return BOOLEAN;
impure function pb_ExportAddressMappingAsAssemblerInterruptVector(System : T_PB_SYSTEM; psmFileName : STRING; TableRows : POSITIVE) return BOOLEAN;
impure function pb_ExportAddressMappingAsChipScopeTokens(System : T_PB_SYSTEM; tokenFileName : STRING) return BOOLEAN;
end package;
package body pb is
-- private functions (must be declared before public functions)
-- ===========================================================================
-- function pb_LongName(name : STRING) return T_PB_LONGNAME is
-- begin
-- return resize(name, C_PB_MAX_LONGNAME_LENGTH);
-- end function;
function pb_ShortName(name : STRING) return T_PB_SHORTNAME is
begin
return resize(name, C_PB_MAX_SHORTNAME_LENGTH);
end function;
-- public functions
-- ===========================================================================
function pb_CreateReadonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD is
variable Result : T_PB_REGISTER_FIELD;
begin
-- Result.FieldName := pb_LongName(NameLong);
Result.FieldShort := pb_ShortName(NameShort);
Result.Length := Length;
Result.FieldKind := PB_REGISTER_FIELD_KIND_READ;
Result.AutoClear := AutoClear;
Result.Encoding := resize(Encoding, Result.Encoding'length);
return Result;
end function;
function pb_CreateWriteonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD is
variable Result : T_PB_REGISTER_FIELD;
begin
-- Result.FieldName := pb_LongName(NameLong);
Result.FieldShort := pb_ShortName(NameShort);
Result.Length := Length;
Result.FieldKind := PB_REGISTER_FIELD_KIND_WRITE;
Result.AutoClear := AutoClear;
Result.Encoding := resize(Encoding, Result.Encoding'length);
return Result;
end function;
function pb_CreateRegisterField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD is
variable Result : T_PB_REGISTER_FIELD;
begin
-- Result.FieldName := pb_LongName(NameLong);
Result.FieldShort := pb_ShortName(NameShort);
Result.Length := Length;
Result.FieldKind := PB_REGISTER_FIELD_KIND_READWRITE;
Result.AutoClear := AutoClear;
Result.Encoding := resize(Encoding, Result.Encoding'length);
return Result;
end function;
function pb_EnumerateRegisterFields(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR) return T_PB_REGISTER_FIELD_VECTOR is
variable Result : T_PB_REGISTER_FIELD_VECTOR(RegisterFieldList'range);
begin
for i in RegisterFieldList'range loop
Result(i) := RegisterFieldList(i);
Result(i).FieldID := i;
end loop;
return Result;
end function;
function pb_GetRegisterFieldID(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_UINT_8 is
begin
for i in RegisterFieldList'range loop
next when (not str_match(RegisterFieldList(i).FieldShort, NameShort));
return i;
end loop;
report "RegisterField '" & str_trim(NameShort) & "' does not exist!" severity FAILURE;
end function;
function pb_GetRegisterField(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_PB_REGISTER_FIELD is
begin
return RegisterFieldList(pb_GetRegisterFieldID(RegisterFieldList, NameShort));
end function;
function pb_CreateRegisterRO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER;
constant REPORT_PREFIX : STRING := ite((PB_REPORT and not PB_VERBOSE), "pb_CreateRegisterRO: ", " ");
begin
if (RegisterField.FieldKind /= PB_REGISTER_FIELD_KIND_READ) then
report "pb_CreateRegisterRO: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not RO, but should be translated into a READ register." severity FAILURE;
end if;
if (PB_VERBOSE = TRUE) then
report "pb_CreateRegisterRO:" severity NOTE;
report " RegisterFieldList: Count=" & INTEGER'image(RegisterFieldList'length) severity NOTE;
for i in RegisterFields'range loop
report " " & INTEGER'image(i) & ": " & str_trim(RegisterFields(i).FieldShort) severity NOTE;
end loop;
end if;
if (PB_REPORT = TRUE) then
report REPORT_PREFIX & "Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
Result.RegisterKind := PB_REGISTER_KIND_READ;
Result.FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
return Result;
end function;
function pb_CreateRegisterRW(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER_VECTOR(0 to 1);
begin
if (RegisterField.FieldKind /= PB_REGISTER_FIELD_KIND_READWRITE) then
report "pb_CreateRegisterRW: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not RW, but should be translated into a READ and a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterRW: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result(0).RegisterName := pb_LongName(NameShort);
Result(0).RegisterShort := pb_ShortName(NameShort);
Result(0).RegisterNumber := RegisterNumber;
Result(0).RegisterKind := PB_REGISTER_KIND_READ;
Result(0).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
-- Result(1).RegisterName := pb_LongName(NameShort);
Result(1).RegisterShort := pb_ShortName(NameShort);
Result(1).RegisterNumber := RegisterNumber;
Result(1).RegisterKind := PB_REGISTER_KIND_WRITE;
Result(1).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITE));
return Result;
end function;
function pb_CreateRegisterWO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER;
begin
if (RegisterField.FieldKind /= PB_REGISTER_FIELD_KIND_WRITE) then
report "pb_CreateRegisterRO: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not WO, but shall be translated into a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterWO: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
Result.RegisterKind := PB_REGISTER_KIND_WRITE;
Result.FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
return Result;
end function;
function pb_CreateRegisterKO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER;
begin
if (RegisterField.FieldKind = PB_REGISTER_FIELD_KIND_READ) then
report "pb_CreateRegisterK: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not WO or RW, but should be translated into a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterKO: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
Result.RegisterKind := PB_REGISTER_KIND_WRITEK;
Result.FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITEK));
return Result;
end function;
function pb_CreateRegisterWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER_VECTOR(0 to 1);
begin
if (RegisterField.FieldKind = PB_REGISTER_FIELD_KIND_READ) then
report "pb_CreateRegisterRW: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not WO, but should be translated into a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterWK: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result(0).RegisterName := pb_LongName(NameShort);
Result(0).RegisterShort := pb_ShortName(NameShort);
Result(0).RegisterNumber := RegisterNumber;
Result(0).RegisterKind := PB_REGISTER_KIND_WRITE;
Result(0).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITE));
-- Result(1).RegisterName := pb_LongName(NameShort);
Result(1).RegisterShort := pb_ShortName(NameShort);
Result(1).RegisterNumber := RegisterNumber;
Result(1).RegisterKind := PB_REGISTER_KIND_WRITEK;
Result(1).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITEK));
return Result;
end function;
function pb_CreateRegisterRWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER_VECTOR(0 to 2);
begin
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterRWK: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result(0).RegisterName := pb_LongName(NameShort);
Result(0).RegisterShort := pb_ShortName(NameShort);
Result(0).RegisterNumber := RegisterNumber;
Result(0).RegisterKind := PB_REGISTER_KIND_READ;
Result(0).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
-- Result(1).RegisterName := pb_LongName(NameShort);
Result(1).RegisterShort := pb_ShortName(NameShort);
Result(1).RegisterNumber := RegisterNumber;
Result(1).RegisterKind := PB_REGISTER_KIND_WRITE;
Result(1).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITE));
-- Result(2).RegisterName := pb_LongName(NameShort);
Result(2).RegisterShort := pb_ShortName(NameShort);
Result(2).RegisterNumber := RegisterNumber;
Result(2).RegisterKind := PB_REGISTER_KIND_WRITEK;
Result(2).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITEK));
return Result;
end function;
function pb_CreateCombinedRegister(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_GROUP_VECTOR) return T_PB_REGISTER is
variable Result : T_PB_REGISTER;
variable RegisterField : T_PB_REGISTER_FIELD;
begin
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
for i in RegisterFields'range loop
RegisterField := pb_GetRegisterField(RegisterFieldList, RegisterFields(i).FieldShort);
Result.FieldMappings(i) := (
FieldID => pb_GetRegisterFieldID(RegisterFieldList, RegisterField.FieldShort),
Start => RegisterFields(i).Offset,
Length => RegisterField.Length,
MappingKind => RegisterFields(i).MappingKind);
Result.FieldMappingCount := RegisterFields'length;
if (Result.RegisterKind = PB_REGISTER_KIND_READ) then
if (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_WRITE) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
elsif (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_WRITEK) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
end if;
elsif (Result.RegisterKind = PB_REGISTER_KIND_WRITE) then
if (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_READ) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
end if;
elsif (Result.RegisterKind = PB_REGISTER_KIND_WRITEK) then
if (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_READ) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
end if;
end if;
end loop;
return Result;
end function;
-- private function
function pb_CreateMapping(Device : T_PB_DEVICE; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_PORTNUMBER_MAPPING_VECTOR is
variable Result : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
variable Reg : T_PB_REGISTER;
variable j : T_UINT_8;
begin
Result := (others => C_PB_PORTNUMBER_MAPPING_EMPTY);
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "Creating PortNumber mapping for device " & str_trim(Device.DeviceShort) & " with " & INTEGER'image(Device.RegisterCount) & " registers:" severity NOTE;
end if;
j := 0;
for i in 0 to Device.RegisterCount - 1 loop
Reg := Device.Registers(i);
case Reg.RegisterKind is
when PB_REGISTER_KIND_READ =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(MappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as readable" severity NOTE;
end if;
Result(j) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_READ
);
j := j + 1;
when PB_REGISTER_KIND_READWRITE =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(MappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as read/writeable" severity NOTE;
end if;
Result(j) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_READ
);
Result(j + 1) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_WRITE
);
j := j + 2;
when PB_REGISTER_KIND_WRITE =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(MappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as writeable" severity NOTE;
end if;
Result(j) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_WRITE
);
j := j + 1;
when PB_REGISTER_KIND_WRITEK =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(KMappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as K-writeable" severity NOTE;
end if;
Result(j) := (
PortNumber => KMappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_WRITEK
);
j := j + 1;
if (j > C_PB_MAX_MAPPINGS) then
report "pb_CreateMapping: Too many mappings created." severity FAILURE;
end if;
end case;
end loop;
return Result(0 to j - 1);
end function;
function pb_CreateDevice(DeviceName : STRING; DeviceShort : STRING; Registers : T_PB_REGISTER_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_VECTOR; CreatesInterrupt : BOOLEAN := FALSE) return T_PB_DEVICE is
variable Result : T_PB_DEVICE;
begin
-- Result.DeviceName := pb_LongName(DeviceName);
Result.DeviceShort := pb_ShortName(DeviceShort);
Result.Registers := pb_ResizeVec(Registers);
Result.RegisterCount := Registers'length;
Result.RegisterFields := pb_ResizeVec(RegisterFields);
Result.RegisterFieldCount := RegisterFields'length;
Result.CreatesInterrupt := CreatesInterrupt;
return Result;
end function;
function pb_CreateDeviceAlias(Device : T_PB_DEVICE; AliasName : STRING) return T_PB_DEVICE is
variable Result : T_PB_DEVICE;
begin
Result := Device;
Result.DeviceShort := pb_ShortName(AliasName);
return Result;
end function;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE is
constant Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_CreateMapping(Device, MappingStart, KMappingStart);
variable Result : T_PB_DEVICE_INSTANCE;
begin
-- Result.DeviceName := Device.DeviceName;
Result.DeviceShort := Device.DeviceShort;
Result.Device := Device;
Result.BusShort := pb_ShortName(BusShort);
Result.MappingCount := Mappings'length;
Result.Mappings := pb_ResizeVec(Mappings);
return Result;
end function;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; InstanceNumber : T_UINT_8; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE is
constant Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_CreateMapping(Device, MappingStart, KMappingStart);
variable Result : T_PB_DEVICE_INSTANCE;
begin
-- Result.DeviceName := pb_LongName(str_trim(Device.DeviceName) & INTEGER'image(InstanceNumber));
Result.DeviceShort := pb_ShortName(str_trim(Device.DeviceShort) & INTEGER'image(InstanceNumber));
Result.Device := Device;
Result.BusShort := pb_ShortName(BusShort);
Result.MappingCount := Mappings'length;
Result.Mappings := pb_ResizeVec(Mappings);
return Result;
end function;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; NameLong : STRING; NameShort : STRING; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE is
constant Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_CreateMapping(Device, MappingStart, KMappingStart);
variable Result : T_PB_DEVICE_INSTANCE;
begin
-- Result.DeviceName := pb_LongName(NameLong);
Result.DeviceShort := pb_ShortName(NameShort);
Result.Device := Device;
Result.BusShort := pb_ShortName(BusShort);
Result.MappingCount := Mappings'length;
Result.Mappings := pb_ResizeVec(Mappings);
return Result;
end function;
function pb_GetDeviceInstanceID(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; NameShort : STRING) return T_PB_DEVICE_INSTANCE_INDEX is
begin
for i in DeviceInstances'range loop
next when (not str_match(DeviceInstances(i).DeviceShort, NameShort));
return i;
end loop;
report "Device '" & str_trim(NameShort) & "' does not exist!" severity FAILURE;
end function;
function pb_GetDeviceInstanceID(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_INSTANCE_INDEX is
begin
for i in 0 to System.DeviceInstanceCount - 1 loop
next when (not str_match(System.DeviceInstances(i).DeviceShort, NameShort));
return i;
end loop;
report "Device '" & str_trim(NameShort) & "' does not exist!" severity FAILURE;
end function;
function pb_GetDeviceInstance(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; NameShort : STRING) return T_PB_DEVICE_INSTANCE is
begin
return DeviceInstances(pb_GetDeviceInstanceID(DeviceInstances, NameShort));
end function;
function pb_GetDeviceInstance(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_INSTANCE is
begin
return System.DeviceInstances(pb_GetDeviceInstanceID(System, NameShort));
end function;
function pb_GetDeviceDescription(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_DESCRIPTION is
constant DeviceInstance : T_PB_DEVICE_INSTANCE := System.DeviceInstances(pb_GetDeviceInstanceID(System, NameShort));
constant ReadMappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_FilterMappings(DeviceInstance, PB_MAPPING_KIND_READ);
constant WriteMappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_FilterMappings(DeviceInstance, PB_MAPPING_KIND_WRITE);
constant WriteKMappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_FilterMappings(DeviceInstance, PB_MAPPING_KIND_WRITEK);
variable Result : T_PB_DEVICE_DESCRIPTION;
begin
Result.DeviceShort := DeviceInstance.DeviceShort;
Result.BusShort := DeviceInstance.BusShort;
Result.ReadMappings := pb_ResizeVec(ReadMappings);
Result.ReadMappingCount := ReadMappings'length;
Result.WriteMappings := pb_ResizeVec(ReadMappings);
Result.WriteMappingCount := WriteMappings'length;
Result.WriteKMappings := pb_ResizeVec(WriteKMappings);
Result.WriteKMappingCount := WriteKMappings'length;
return Result;
end function;
function pb_CreateBus(BusName : STRING; BusShort : STRING; SuperBusShort : STRING) return T_PB_BUS is
variable Result : T_PB_BUS;
begin
-- Result.BusName := pb_LongName(BusName);
Result.BusShort := pb_ShortName(BusShort);
Result.SuperBusShort := pb_ShortName(SuperBusShort);
Result.SuperBusID := 0;
Result.SubBusses := (others => 0);
Result.SubBusCount := 0;
Result.Devices := (others => 0);
Result.DeviceCount := 0;
Result.TotalDeviceCount := 0;
return Result;
end function;
function pb_GetBusID(Busses : T_PB_BUS_VECTOR; BusShort : T_PB_SHORTNAME) return NATURAL is
begin
for i in Busses'range loop
next when (Busses(i).BusShort /= BusShort);
return i;
end loop;
report "Unknown bus name '" & str_trim(BusShort) & "'" severity failure;
end function;
function pb_GetBusID(System : T_PB_SYSTEM; BusShort : T_PB_SHORTNAME) return NATURAL is
begin
return pb_GetBusID(System.Busses(0 to System.BusCount - 1), BusShort);
end function;
function pb_ConnectBusses(Busses : T_PB_BUS_VECTOR) return T_PB_BUS_VECTOR is
variable Result : T_PB_BUS_VECTOR(Busses'range);
variable SuperBusID : T_PB_BUSID;
variable j : T_UINT_8;
begin
for i in Busses'range loop
if (PB_VERBOSE = TRUE) then
report "pb_ConnectBusses: Connecting bus '" & str_trim(Busses(i).BusShort) & "' to '" & str_trim(Busses(i).SuperBusShort) & "'" severity NOTE;
end if;
if (str_length(Busses(i).SuperBusShort) /= 0) then
SuperBusID := pb_GetBusID(Busses, Busses(i).SuperBusShort);
else
SuperBusID := T_PB_BUSID'high;
end if;
-- Result(i).BusName := Busses(i).BusName;
Result(i).BusShort := Busses(i).BusShort;
Result(i).SuperBusShort := Busses(i).SuperBusShort;
Result(i).SuperBusID := SuperBusID;
if (SuperBusID /= T_PB_BUSID'high) then
j := Result(SuperBusID).SubBusCount;
Result(SuperBusID).SubBusses(j) := i;
Result(SuperBusID).SubBusCount := j + 1;
end if;
end loop;
return Result;
end function;
function pb_GetTotalDeviceCount(Busses : T_PB_BUS_VECTOR; BusID : T_PB_BUSID) return T_UINT_8 is
variable Result : T_UINT_8;
begin
Result := 0;
-- report "pb_GetTotalDeviceCount: BusID=" & INTEGER'image(BusID) severity NOTE;
for i in 0 to Busses(BusID).SubBusCount - 1 loop
Result := Result + pb_GetTotalDeviceCount(Busses, Busses(BusID).SubBusses(i));
end loop;
return Result + Busses(BusID).DeviceCount;
end function;
function pb_CreateSystem(SystemName : STRING; SystemShort : STRING; Busses : T_PB_BUS_VECTOR; DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR) return T_PB_SYSTEM is
variable Result : T_PB_SYSTEM;
variable BusID : T_PB_BUSID;
variable j : T_UINT_8;
begin
-- Result.SystemName := pb_LongName(SystemName);
Result.SystemShort := pb_ShortName(SystemShort);
Result.DeviceInstances := pb_ResizeVec(DeviceInstances);
Result.DeviceInstanceCount := DeviceInstances'length;
Result.Busses := pb_ResizeVec(Busses);
Result.BusCount := Busses'length;
-- connect devices to busses
for i in DeviceInstances'range loop
BusID := pb_GetBusID(Busses, DeviceInstances(i).BusShort);
j := Result.Busses(BusID).DeviceCount;
Result.Busses(BusID).Devices(j) := i;
Result.Busses(BusID).DeviceCount := j + 1;
end loop;
-- count devices on a bus
-- TODO: rewrite recursion to local loops
for i in 0 to Result.BusCount - 1 loop
Result.Busses(i).TotalDeviceCount := pb_GetTotalDeviceCount(Result.Busses(0 to Result.BusCount - 1), i);
end loop;
return Result;
end function;
function pb_Resize(RegisterMapping : T_PB_REGISTER_FIELD_MAPPING; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_MAPPING_INDEX'high);
begin
return RegisterMapping & T_PB_REGISTER_FIELD_MAPPING_VECTOR'(1 to high => C_PB_REGISTER_FIELD_MAPPING_EMPTY);
end function;
function pb_Resize(RegisterField : T_PB_REGISTER_FIELD; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_INDEX'high);
begin
return RegisterField & T_PB_REGISTER_FIELD_VECTOR'(1 to high => C_PB_REGISTER_FIELD_EMPTY);
end function;
function pb_Resize(Reg : T_PB_REGISTER; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_INDEX'high);
begin
return Reg & T_PB_REGISTER_VECTOR'(1 to high => C_PB_REGISTER_EMPTY);
end function;
function pb_ResizeVec(RegisterMappings : T_PB_REGISTER_FIELD_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_MAPPING_INDEX'high);
begin
return RegisterMappings & T_PB_REGISTER_FIELD_MAPPING_VECTOR'(RegisterMappings'length to high => C_PB_REGISTER_FIELD_MAPPING_EMPTY);
end function;
function pb_ResizeVec(RegisterFields : T_PB_REGISTER_FIELD_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_INDEX'high);
begin
return RegisterFields & T_PB_REGISTER_FIELD_VECTOR'(RegisterFields'length to high => C_PB_REGISTER_FIELD_EMPTY);
end function;
function pb_ResizeVec(Registers : T_PB_REGISTER_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_INDEX'high);
begin
return Registers & T_PB_REGISTER_VECTOR'(Registers'length to high => C_PB_REGISTER_EMPTY);
end function;
function pb_ResizeVec(Busses : T_PB_BUS_VECTOR; Size : NATURAL := 0) return T_PB_BUS_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_BUS_INDEX'high);
begin
return Busses & T_PB_BUS_VECTOR'(Busses'length to high => C_PB_BUS_EMPTY);
end function;
function pb_ResizeVec(Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_PORTNUMBER_MAPPING_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_PORTNUMBER_MAPPING_INDEX'high);
begin
return Mappings & T_PB_PORTNUMBER_MAPPING_VECTOR'(Mappings'length to high => C_PB_PORTNUMBER_MAPPING_EMPTY);
end function;
function pb_ResizeVec(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; Size : NATURAL := 0) return T_PB_DEVICE_INSTANCE_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_DEVICE_INSTANCE_INDEX'high);
begin
return DeviceInstances & T_PB_DEVICE_INSTANCE_VECTOR'(DeviceInstances'length to high => C_PB_DEVICE_INSTANCE_EMPTY);
end function;
-- PicoBlaze interrupt functions
function pb_GetInterruptCount(System : T_PB_SYSTEM) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
if (System.DeviceInstances(i).Device.CreatesInterrupt = TRUE) then
Result := Result + 1;
end if;
end loop;
return Result;
end function;
function pb_GetInterruptPortIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
exit when str_match(System.DeviceInstances(i).DeviceShort, DeviceShort);
Result := Result + 1;
end loop;
return Result;
end function;
function pb_GetInterruptVector(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return STD_LOGIC_VECTOR is
variable Result : STD_LOGIC_VECTOR(System.DeviceInstanceCount - 1 downto 0);
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable BusIndex : T_PB_BUSID;
variable InterruptPortID : T_UINT_8;
begin
InterruptPortID := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
BusIndex := pb_GetBusIndex(System, DeviceInstance.DeviceShort);
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
Result(InterruptPortID) := PicoBlazeBus(BusIndex).Interrupt;
InterruptPortID := InterruptPortID + 1;
end if;
end loop;
return Result(InterruptPortID - 1 downto 0);
end function;
function pb_GetInterruptMessages(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return T_SLVV_8 is
variable Result : T_SLVV_8(System.DeviceInstanceCount - 1 downto 0);
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable BusIndex : T_PB_BUSID;
variable InterruptPortID : T_UINT_8;
begin
InterruptPortID := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
BusIndex := pb_GetBusIndex(System, DeviceInstance.DeviceShort);
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
Result(InterruptPortID) := PicoBlazeBus(BusIndex).Message;
InterruptPortID := InterruptPortID + 1;
end if;
end loop;
return Result(InterruptPortID - 1 downto 0);
end function;
procedure pb_AssignInterruptAck(signal Output : inout T_PB_IOBUS_PB_DEV_VECTOR; Input : STD_LOGIC_VECTOR; System : T_PB_SYSTEM) is
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable BusIndex : T_PB_BUSID;
variable InterruptPortID : NATURAL;
begin
InterruptPortID := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
BusIndex := pb_GetBusIndex(System, DeviceInstance.DeviceShort);
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
Output(i).Interrupt_Ack <= Input(InterruptPortID);
InterruptPortID := InterruptPortID + 1;
else
Output(i).Interrupt_Ack <= '0';
end if;
end loop;
end procedure;
-- PicoBlaze AddressDecoder functions
function pb_FilterMappings(DeviceInstance : T_PB_DEVICE_INSTANCE; MappingKind : T_PB_MAPPING_KIND) return T_PB_PORTNUMBER_MAPPING_VECTOR is
variable Result : T_PB_PORTNUMBER_MAPPING_VECTOR(0 to DeviceInstance.MappingCount - 1);
variable ResultCount : NATURAL;
begin
Result := (others => C_PB_PORTNUMBER_MAPPING_EMPTY);
ResultCount := 0;
for i in 0 to DeviceInstance.MappingCount - 1 loop
if (DeviceInstance.Mappings(i).MappingKind = MappingKind) then
Result(ResultCount) := DeviceInstance.Mappings(i);
ResultCount := ResultCount + 1;
end if;
end loop;
return Result(0 to ResultCount - 1);
end function;
-- PicoBlaze bus functions
function pb_GetBusWidth(System : T_PB_SYSTEM; BusShort : STRING) return NATURAL is
constant BUSID : T_PB_BUSID := pb_GetBusID(System, pb_ShortName(BusShort));
begin
return System.Busses(BUSID).TotalDeviceCount;
end function;
function pb_GetBusIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL is
constant DeviceInstance : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(System, DeviceShort);
constant DeviceInstanceID : T_PB_DEVICE_INSTANCE_INDEX := pb_GetDeviceInstanceID(System, DeviceShort);
constant BusID : T_PB_BUSID := pb_GetBusID(System, DeviceInstance.BusShort);
constant MyBus : T_PB_BUS := System.Busses(BusID);
variable Result : NATURAL;
begin
-- report "pb_GetBusIndex: DevInstID=" & INTEGER'image(DeviceInstanceID) severity NOTE;
Result := MyBus.TotalDeviceCount - MyBus.DeviceCount;
for i in 0 to MyBus.DeviceCount - 1 loop
-- report "pb_GetBusIndex: Devices(i)=" & INTEGER'image(MyBus.Devices(i)) severity NOTE;
exit when (MyBus.Devices(i) = DeviceInstanceID);
Result := Result + 1;
end loop;
return Result;
end function;
function pb_GetSubBusOffset(System : T_PB_SYSTEM; BusShort : T_PB_SHORTNAME) return NATURAL is
constant BusID : T_PB_BUSID := pb_GetBusID(System, BusShort);
constant SuperBusID : T_PB_BUSID := System.Busses(BusID).SuperBusID;
variable Result : NATURAL;
begin
Result := 0;
for i in 0 to System.Busses(SuperBusID).SubBusCount - 1 loop
if (System.Busses(SuperBusID).SubBusses(i) = BusID) then
return Result;
else
Result := Result + System.Busses(System.Busses(SuperBusID).SubBusses(i)).TotalDeviceCount;
end if;
end loop;
-- report error
end function;
function pb_GetSubOrdinateBus(Input : T_PB_IOBUS_PB_DEV_VECTOR; System : T_PB_SYSTEM; BusShort : STRING) return T_PB_IOBUS_PB_DEV_VECTOR is
constant BusWidth : NATURAL := pb_GetBusWidth(System, BusShort);
constant Offset : NATURAL := pb_GetSubBusOffset(System, pb_ShortName(BusShort));
variable Result : T_PB_IOBUS_PB_DEV_VECTOR(BusWidth - 1 downto 0);
begin
for i in Result'range loop
Result(i) := Input(Offset + i);
end loop;
return Result;
end function;
procedure pb_AssignSubOrdinateBus(signal Output : inout T_PB_IOBUS_DEV_PB_VECTOR; Input : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM; BusShort : STRING) is
constant Offset : NATURAL := pb_GetSubBusOffset(System, pb_ShortName(BusShort));
begin
for i in Input'range loop
Output(Offset + i) <= Input(i);
end loop;
end procedure;
impure function pb_PrintAddressMapping(System : T_PB_SYSTEM) return BOOLEAN is
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Device : T_PB_DEVICE;
variable Reg : T_PB_REGISTER;
variable Field : T_PB_REGISTER_FIELD_MAPPING;
begin
if (not (PB_VERBOSE or PB_REPORT)) then
return FALSE;
end if;
report "Printing PicoBlaze address mappings..." severity NOTE;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
Device := DeviceInstance.Device;
report "DeviceInstance " & INTEGER'image(i) & ":" severity NOTE;
report " DeviceInstance: " & str_trim(DeviceInstance.DeviceShort) severity NOTE;
report " Device: " & str_trim(Device.DeviceShort) severity NOTE;
report " Registers: " severity NOTE;
for j in 0 to Device.RegisterCount - 1 loop
Reg := Device.Registers(j);
report " " & INTEGER'image(j) & ": " & str_trim(Reg.RegisterShort) & " Reg#=" & INTEGER'image(Reg.RegisterNumber) & " " &
ite((Reg.RegisterKind = PB_REGISTER_KIND_READ), "RD",
ite((Reg.RegisterKind = PB_REGISTER_KIND_READWRITE), "RW",
ite((Reg.RegisterKind = PB_REGISTER_KIND_WRITE), "WR", "K ")))
severity NOTE;
for k in 0 to Reg.FieldMappingCount - 1 loop
Field := Reg.FieldMappings(k);
report " " & INTEGER'image(k) & ": FieldID=" & INTEGER'image(Field.FieldID) & " (" & str_trim(Device.RegisterFields(Field.FieldID).FieldShort) & ")"
severity NOTE;
end loop;
end loop;
end loop;
return TRUE;
end function;
impure function pb_PrintBusses(System : T_PB_SYSTEM) return BOOLEAN is
variable CurBus : T_PB_BUS;
begin
if (not (PB_VERBOSE or PB_REPORT)) then
return FALSE;
end if;
report "pb_PrintBusses: Count=" & INTEGER'image(System.BusCount) severity NOTE;
for i in 0 to System.BusCount - 1 loop
CurBus := System.Busses(i);
report "BusID " & INTEGER'image(i) & "(" & str_trim(CurBus.BusShort) & ")" severity NOTE;
report " SuperBusID " & INTEGER'image(CurBus.SuperBusID) & "(" & ite((CurBus.SuperBusID /= T_PB_BUSID'high), str_trim(System.Busses(System.Busses(imax(i, T_PB_BUS_INDEX'high)).SuperBusID).BusShort), "----") & ")" severity NOTE;
report " SubBusCount " & INTEGER'image(CurBus.SubBusCount) severity NOTE;
for j in 0 to CurBus.SubBusCount - 1 loop
report " SubBusID " & INTEGER'image(CurBus.SubBusses(j)) & "(" & str_trim(System.Busses(CurBus.SubBusses(j)).BusShort) & ")" severity NOTE;
end loop;
report " DeviceCount " & INTEGER'image(CurBus.DeviceCount) severity NOTE;
for j in 0 to CurBus.DeviceCount - 1 loop
report " DeviceID " & INTEGER'image(CurBus.Devices(j)) & "(" & str_trim(System.DeviceInstances(CurBus.Devices(j)).DeviceShort) & ")" severity NOTE;
end loop;
end loop;
return TRUE;
end function;
impure function pb_ExportAddressMappingAsAssemblerConstants(System : T_PB_SYSTEM; psmFileName : STRING) return BOOLEAN is
file psmFile : TEXT open WRITE_MODE is psmFileName;
variable psmLine : LINE;
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Mapping : T_PB_PORTNUMBER_MAPPING;
type T_USAGE_TRACKING is record
DeviceInstanceID : T_UINT_8;
MappingID : T_UINT_8;
end record;
type T_ERROR_DETECT is array (NATURAL range <>) of T_USAGE_TRACKING;
variable AddressMapRead : T_ERROR_DETECT(0 to 255);
variable AddressMapWrite : T_ERROR_DETECT(0 to 255);
variable AddressMapWriteK : T_ERROR_DETECT(0 to 15);
variable MappingID : T_UINT_8;
variable DeviceInstanceID : T_UINT_8;
variable RegID : T_UINT_8;
variable Reg : T_PB_REGISTER;
begin
AddressMapRead := (others => (0, 255));
AddressMapWrite := (others => (0, 255));
AddressMapWriteK := (others => (0, 255));
report "Exporting PicoBlaze address mappings as psm-file to '" & psmFileName & "' ..." severity note;
-- psm-file: write file header
write(psmLine, STRING'("; Generate by synthesis for '" & str_trim(System.SystemShort) & "'")); writeline(psmFile, psmLine);
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; This file contains the PicoBlaze PortNumber to DeviceRegister mappings.")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; =======================================================================")); writeline(psmFile, psmLine);
-- write per device entires
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; ") & str_trim(DeviceInstance.DeviceShort)); writeline(psmFile, psmLine);
for j in 0 to DeviceInstance.MappingCount - 1 loop
Mapping := DeviceInstance.Mappings(j);
if (Mapping.MappingKind /= PB_MAPPING_KIND_EMPTY) then
if (PB_VERBOSE = TRUE) then
report " Map PortNumber " & INTEGER'image(Mapping.PortNumber) &
" to device " & INTEGER'image(i) &
" (" & str_trim(DeviceInstance.DeviceShort) &
") register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity NOTE;
end if;
end if;
-- tokenFile content for INPUT address space
if (Mapping.MappingKind = PB_MAPPING_KIND_READ) then
if (AddressMapRead(Mapping.PortNumber).MappingID = 255) then
AddressMapRead(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j); -- save used MappingID for a PortNumber
write(psmLine, "CONSTANT " & resize(
"IPORT_" & str_toUpper(str_trim(DeviceInstance.DeviceShort)) &
"_" & str_toUpper(str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort)) &
", ", 40, ' ') &
ite((Mapping.PortNumber < 10), " ", "") &
ite((Mapping.PortNumber < 100), " ", "") &
INTEGER'image(Mapping.PortNumber) & "'d ; " &
str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "(");
write(psmLine, STRING'("dummy[3:0]"));
for k in 1 to 1 loop
write(psmLine, STRING'(",dummy[7:4]"));
end loop;
write(psmLine, STRING'(")"));
writeline(psmFile, psmLine);
else
DeviceInstanceID := AddressMapRead(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapRead(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsAssemblerConstants:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUT address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITE) then
if (AddressMapWrite(Mapping.PortNumber).MappingID = 255) then
AddressMapWrite(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
write(psmLine, "CONSTANT " & resize(
"OPORT_" & str_toUpper(str_trim(DeviceInstance.DeviceShort)) &
"_" & str_toUpper(str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort)) &
", ", 40, ' ') &
ite((Mapping.PortNumber < 10), " ", "") &
ite((Mapping.PortNumber < 100), " ", "") &
INTEGER'image(Mapping.PortNumber) & "'d ; " &
str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort));
writeline(psmFile, psmLine);
else
DeviceInstanceID := AddressMapWrite(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWrite(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsAssemblerConstants:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUTK address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITEK) then
if (AddressMapWriteK(Mapping.PortNumber).MappingID = 255) then
AddressMapWriteK(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
write(psmLine, "CONSTANT " & resize(
"KPORT_" & str_toUpper(str_trim(DeviceInstance.DeviceShort)) &
"_" & str_toUpper(str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort)) &
", ", 40, ' ') &
ite((Mapping.PortNumber < 10), " ", "") &
ite((Mapping.PortNumber < 100), " ", "") &
INTEGER'image(Mapping.PortNumber) & "'d ; " &
str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort));
writeline(psmFile, psmLine);
else
DeviceInstanceID := AddressMapWriteK(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWriteK(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsAssemblerConstants:" & LF & "K PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
end if;
end loop;
end loop;
file_close(psmFile);
return true;
end function;
impure function pb_ExportAddressMappingAsAssemblerInterruptVector(System : T_PB_SYSTEM; psmFileName : STRING; TableRows : POSITIVE) return BOOLEAN is
file psmFile : TEXT open WRITE_MODE is psmFileName;
variable psmLine : LINE;
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable j : NATURAL := 0;
begin
report "Exporting PicoBlaze interrupt vector table as psm-file to '" & psmFileName & "' ..." severity note;
-- psm-file: write file header
write(psmLine, STRING'("; Generate by synthesis for '" & str_trim(System.SystemShort) & "'")); writeline(psmFile, psmLine);
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; This file contains the PicoBlaze InterruptVector table.")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; =======================================================")); writeline(psmFile, psmLine);
-- write per device entires
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
-- tokenFile content for existing interrupt
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
write(psmLine, STRING'("JUMP __ISR_") & resize(str_trim(DeviceInstance.DeviceShort), 16, ' ') &
STRING'("; ") & ite((j < 10), STRING'(" "), "") & INTEGER'image(j) &
STRING'(": ") & str_trim(DeviceInstance.DeviceShort));
writeline(psmFile, psmLine);
j := j + 1;
end if;
-- assert not PB_VERBOSE report "pb_ExportAddressMapping: Map PortNumber " & INTEGER'image(Mapping.PortNumber) &
-- " to device " & INTEGER'image(-1) &
-- " (" & str_trim(DeviceInstance.DeviceShort) &
-- ") register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
-- " (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
-- severity NOTE;
end loop;
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; catch undefined ISR routines")); writeline(psmFile, psmLine);
for i in j to TableRows - 1 loop
write(psmLine, STRING'("JUMP __ISR_Error ; ") & INTEGER'image(i) & STRING'(": "));
writeline(psmFile, psmLine);
end loop;
file_close(psmFile);
return true;
end function;
impure function pb_ExportAddressMappingAsChipScopeTokens(System : T_PB_SYSTEM; tokenFileName : STRING) return BOOLEAN is
file tokenFile : TEXT open WRITE_MODE is tokenFileName;
variable tokenLine : LINE;
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Device : T_PB_DEVICE;
variable Mapping : T_PB_PORTNUMBER_MAPPING;
variable PortNumber_slv : T_SLV_8;
type T_USAGE_TRACKING is record
DeviceInstanceID : T_UINT_8;
MappingID : T_UINT_8;
end record;
type T_ERROR_DETECT is array (NATURAL range <>) of T_USAGE_TRACKING;
variable AddressMapRead : T_ERROR_DETECT(0 to 255);
variable AddressMapWrite : T_ERROR_DETECT(0 to 255);
variable AddressMapWriteK : T_ERROR_DETECT(0 to 15);
variable MappingID : T_UINT_8;
variable DeviceInstanceID : T_UINT_8;
variable RegID : T_UINT_8;
variable Reg : T_PB_REGISTER;
begin
AddressMapRead := (others => (0, 255));
AddressMapWrite := (others => (0, 255));
AddressMapWriteK := (others => (0, 255));
report "Exporting PicoBlaze address mappings as token-file to '" & tokenFileName & "'..." severity note;
-- token-file: write file header
write(tokenLine, STRING'("# " & str_trim(System.SystemShort) & " - PortNumbers")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# ChipScope Token File Version")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("@FILE_VERSION=1.0.0")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# Default token value")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("@DEFAULT_TOKEN=")); writeline(tokenFile, tokenLine);
-- write per device entires
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# ") & str_trim(DeviceInstance.DeviceShort)); writeline(tokenFile, tokenLine);
for j in 0 to DeviceInstance.MappingCount - 1 loop
Mapping := DeviceInstance.Mappings(j);
if (PB_VERBOSE = TRUE) then
report " Map PortNumber " & INTEGER'image(Mapping.PortNumber) &
" to device " & INTEGER'image(i) &
" (" & str_trim(DeviceInstance.DeviceShort) &
") register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity NOTE;
end if;
-- tokenFile content for INPUT address space
if (Mapping.MappingKind = PB_MAPPING_KIND_READ) then
if (AddressMapRead(Mapping.PortNumber).MappingID = 255) then
PortNumber_slv := to_slv(Mapping.PortNumber, 8);
AddressMapRead(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j); -- save used MappingID for a PortNumber
write(tokenLine, "RD_" & str_trim(DeviceInstance.DeviceShort) & "_" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "=2" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
else
DeviceInstanceID := AddressMapRead(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapRead(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsChipScopeTokens:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUT address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITE) then
PortNumber_slv := to_slv(Mapping.PortNumber, 8);
if (AddressMapWrite(Mapping.PortNumber).MappingID = 255) then
AddressMapWrite(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
write(tokenLine, "WR_" & str_trim(DeviceInstance.DeviceShort) & "_" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "=1" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
else
DeviceInstanceID := AddressMapWrite(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWrite(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsChipScopeTokens:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUTK address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITEK) then
if (AddressMapWriteK(Mapping.PortNumber).MappingID = 255) then
AddressMapWriteK(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
for k in 0 to 15 loop
PortNumber_slv := to_slv(k, 4) & to_slv(Mapping.PortNumber, 4);
write(tokenLine, STRING'("WK_" & str_trim(DeviceInstance.DeviceShort) & "_" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "=4" & to_string(PortNumber_slv, 'h', 2)));
writeline(tokenFile, tokenLine);
end loop;
else
DeviceInstanceID := AddressMapWriteK(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWriteK(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsChipScopeTokens:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
end if;
end loop;
end loop;
-- write tokens for unused PortNumbers
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# unused PortNumbers")); writeline(tokenFile, tokenLine);
for i in AddressMapWrite'range loop
PortNumber_slv := to_slv(i, 8);
if (AddressMapWrite(i).MappingID = 255) then
write(tokenLine, "WR_ERR" & "=1" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
end if;
end loop;
for i in AddressMapRead'range loop
PortNumber_slv := to_slv(i, 8);
if (AddressMapRead(i).MappingID = 255) then
write(tokenLine, "RD_ERR" & "=2" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
end if;
end loop;
for i in AddressMapWriteK'range loop
if (AddressMapWriteK(i).MappingID = 255) then
for k in 0 to 15 loop
PortNumber_slv := to_slv(k, 4) & to_slv(i, 4);
write(tokenLine, "WK_ERR" & "=4" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
end loop;
end if;
end loop;
file_close(tokenFile);
return true;
end function;
end package body;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_keycode is
port(
address : in vl_logic_vector(1 downto 0);
chipselect : in vl_logic;
clk : in vl_logic;
reset_n : in vl_logic;
write_n : in vl_logic;
writedata : in vl_logic_vector(31 downto 0);
out_port : out vl_logic_vector(7 downto 0);
readdata : out vl_logic_vector(31 downto 0)
);
end usb_system_keycode;
|
-------------------------------------------------------------------
--! @file
--! @author Stephan Doll
--! @brief Package for VHDL text output, from Stephan Doll's VHDL verification course.
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
--! @brief Allows for text output in simulation
package txt_util is
--! prints a message to the screen
procedure print(text: string);
--! @brief prints the message when active
--
-- useful for debug switches
procedure print(active: boolean; text: string);
--! converts std_logic into a character
function chr(sl: std_logic) return character;
--! converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
--! converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
--! converts boolean into a string
function str(b: boolean) return string;
--! @brief converts an integer into a single character
--
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
--! converts integer into string using specified base
function str(int: integer; base: integer) return string;
--! converts integer to string, using base 10
function str(int: integer) return string;
--! convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
--! convert a character to upper case
function to_upper(c: character) return character;
--! convert a character to lower case
function to_lower(c: character) return character;
--! convert a string to upper case
function to_upper(s: string) return string;
--! convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
--! converts a character into std_logic
function to_std_logic(c: character) return std_logic;
--! converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
--! read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
--! print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
--! print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
--! prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
--! prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
--! converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
--! converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
--! @brief converts std_logic_vector into a string (binary base)
--
-- @detailed (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
--! @brief converts boolean into a string
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
--! @brief converts an integer into a character
--
-- @detailed for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
--! @brief convert integer to string using specified base
--
-- @detailed (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
--! convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
--! converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
--! convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
--! convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
--! convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
--! convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
--! converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
--! converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
--! read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
--! print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
--! print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
--! @brief appends contents of a string to a file until line feed occurs
--
-- @detailed (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
type ram_type is array (0 to 3) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111110001100010000", "11111111111111111111100110110000", "00000000000000000001110011110000", "00000000000000000000011001010000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
type ram_type is array (0 to 3) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111110001100010000", "11111111111111111111100110110000", "00000000000000000001110011110000", "00000000000000000000011001010000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
type ram_type is array (0 to 3) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111110001100010000", "11111111111111111111100110110000", "00000000000000000001110011110000", "00000000000000000000011001010000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
--------------------------------------------------------------------------------
-- Programmable Interval Timer --
--------------------------------------------------------------------------------
-- Simplest implementation of a programmable interval timer. The timer is --
-- Wishbone compliant and functions on two instructions: --
-- --
-- o Start the timer with a Wb write. The data to be sent contains the --
-- inverall length. --
-- --
-- o After the set limit is reached, the timer issues an interrupt and waits --
-- for a WB write. It returns back to initial state afterwards and waits --
-- for a new WB write. --
-- --
-- The timer supports pulse timing only. --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
package ipit is
component pit is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
intr : out std_logic
);
end component;
end ipit; |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_random_entity;
ARCHITECTURE mpegmv_random_description OF mpegmv_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 * 9;
WHEN "00000010" =>
register10 := input10 * 10;
WHEN "00000011" =>
register10 := register10 + 12;
WHEN "00000100" =>
register9 := register9 + register10;
register10 := input11 * 13;
register11 := input12 * 14;
register12 := input13 * 15;
WHEN "00000101" =>
register11 := register11 + 17;
register3 := register3 + 19;
register4 := register4 + 21;
register13 := input14 * 22;
register6 := register6 + register9;
WHEN "00000110" =>
register2 := register2 + register11;
register4 := register10 + register4;
WHEN "00000111" =>
register2 := register5 + register2;
register5 := register12 + 24;
register1 := register1 + register4;
register3 := register7 + register3;
WHEN "00001000" =>
output1 <= register13 + register5;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001001" =>
output2 <= register1(0 TO 15) & register6(0 TO 15);
register1 := register8 + register3;
WHEN "00001010" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001011" =>
output3 <= register1(0 TO 15) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_random_description; |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_loader.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_loader is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end rx_fifo_loader;
------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_loader is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
type STATES_TYPE is (
IPG,
PREAMBLE,
PREAMBLE_10,
RX100,
RX10
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal rx_cary_sense_i : std_logic;
signal rx_data_valid_i : std_logic;
signal rx_end_of_packet_i : std_logic;
signal repeated_data_cnt : integer range 0 to 63;
signal phy2rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal phy2rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal dibit_cnt : std_logic_vector(3 downto 0);
signal sample_rxd_cnt : std_logic_vector(4 downto 0);
signal sample_rxd : std_logic;
signal rxd_is_idle : std_logic;
signal rxd_is_preamble : std_logic;
signal rxd_is_preamble10 : std_logic;
signal rxd_10_i : std_logic;
signal rxd_100_i : std_logic;
begin
------------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
------------------------------------------------------------------------------
--RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
--begin
-- if (Ref_Clk'event and Ref_Clk = '1') then
-- if (Sync_rst_n = '0') then
-- phy2Rmii_crs_dv_sr <= (others => '0');
-- else
-- phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
-- Phy2Rmii_crs_dv;
-- end if;
-- end if;
--end process;
------------------------------------------------------------------------------
-- RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_error <= '0';
Rx_cary_sense <= '0';
rx_cary_sense_i <= '0';
rx_end_of_packet_i <= '0';
Rx_data_valid <= '0';
phy2Rmii_crs_dv_sr <= (others => '0');
else
Rx_error <= Phy2Rmii_rx_er;
Rx_cary_sense <= rx_cary_sense_i;
Rx_data_valid <= rx_data_valid_i;
rx_end_of_packet_i <= (rxd_100_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(0)) or
(rxd_10_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(9));
rx_cary_sense_i <= (Phy2Rmii_crs_dv and rx_cary_sense_i) or
(Phy2Rmii_crs_dv and not rxd_10_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(1)) or
(Phy2Rmii_crs_dv and not rxd_100_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(11));
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) & Phy2Rmii_crs_dv;
end if;
if (Sync_rst_n = '0') then
rx_data_valid_i <= '0';
elsif (rx_data_valid_i = '0') then
rx_data_valid_i <= Phy2Rmii_crs_dv or phy2Rmii_crs_dv_sr(0);
elsif (rx_data_valid_i = '1') then
rx_data_valid_i <= not rx_end_of_packet_i;
end if;
end if;
end process;
Rx_end_of_packet <= rx_end_of_packet_i;
---------------------------------------------------------------------------
-- RXD_PIPELINE_DELAY_PROCESS
---------------------------------------------------------------------------
RXD_PIPELINE_DELAY_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
phy2rmii_rxd_d2 <= (others => '0');
phy2rmii_rxd_d1 <= (others => '0');
else
phy2rmii_rxd_d2 <= phy2rmii_rxd_d1;
phy2rmii_rxd_d1 <= Phy2Rmii_rxd;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- REPEATED_DATA_CNT_PROCESS
---------------------------------------------------------------------------
REPEATED_DATA_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
repeated_data_cnt <= 0;
elsif (phy2rmii_rxd_d1 = Phy2Rmii_rxd) then
if (repeated_data_cnt = 63) then
repeated_data_cnt <= 63;
else
repeated_data_cnt <= repeated_data_cnt + 1;
end if;
else
repeated_data_cnt <= 0;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- SAMPLE_RXD_CNT_PROCESS
---------------------------------------------------------------------------
SAMPLE_RXD_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
sample_rxd_cnt <= "00000";
sample_rxd <= '0';
elsif (rxd_10_i = '1') then
if (sample_rxd_cnt = "00000") then
sample_rxd <= '1';
else
sample_rxd <= '0';
end if;
sample_rxd_cnt <= sample_rxd_cnt(3 downto 0) & not sample_rxd_cnt(4);
elsif (rxd_is_preamble10 = '1') then
sample_rxd_cnt <= "10000";
else
sample_rxd_cnt <= "00001";
sample_rxd <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_CNT_PROCESS
---------------------------------------------------------------------------
DIBIT_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ((Sync_rst_n = '0') or (rxd_is_idle = '1')) then
dibit_cnt <= "0001";
elsif (rxd_is_preamble10 = '1') then
dibit_cnt <= "0100";
elsif ((sample_rxd = '1') and (rxd_is_idle = '0')) then
dibit_cnt <= dibit_cnt(2 downto 0) & (dibit_cnt(3));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_TO_BYTE_MAPPING_PROCESS
---------------------------------------------------------------------------
DIBIT_TO_BYTE_MAPPING_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
Rx_data <= (others => '0');
elsif (dibit_cnt(0) = '1') then
Rx_data(0) <= phy2rmii_rxd_d2(0);
Rx_data(1) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(1) = '1') then
Rx_data(2) <= phy2rmii_rxd_d2(0);
Rx_data(3) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(2) = '1') then
Rx_data(4) <= phy2rmii_rxd_d2(0);
Rx_data(5) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(3) = '1') then
Rx_data(6) <= phy2rmii_rxd_d2(0);
Rx_data(7) <= phy2rmii_rxd_d2(1);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR_FIFO_EN_PROCESS
---------------------------------------------------------------------------
WR_FIFO_EN_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_fifo_wr_en <= '0';
elsif ((sample_rxd = '1') and (dibit_cnt(3) = '1') and (rxd_is_idle = '0') and
(rxd_is_preamble10 = '0')) then
Rx_fifo_wr_en <= '1';
else
Rx_fifo_wr_en <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IPG;
else
present_state <= next_state;
end if;
case next_state is
when IPG =>
rxd_is_idle <= '1';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE =>
rxd_is_idle <= '0';
rxd_is_preamble <= '1';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE_10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '1';
rxd_100_i <= '0';
rxd_10_i <= '0';
when RX100 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '1';
rxd_10_i <= '0';
when RX10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '1';
end case;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
repeated_data_cnt,
phy2rmii_rxd_d1,
Phy2Rmii_rxd,
Phy2Rmii_crs_dv,
rx_data_valid_i
)
begin
case present_state is
when IPG =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "01") and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE;
else
next_state <= IPG;
end if;
when PREAMBLE =>
if ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt < 31) and (Phy2Rmii_rxd = "11")) then
next_state <= RX100;
elsif ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt > 30) and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE_10;
else
next_state <= PREAMBLE;
end if;
when PREAMBLE_10 =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "11")) then
next_state <= RX10;
else
next_state <= PREAMBLE_10;
end if;
when RX100 =>
if (rx_data_valid_i = '0')then
next_state <= IPG;
else
next_state <= RX100;
end if;
when RX10 =>
if (rx_data_valid_i = '0') then
next_state <= IPG;
else
next_state <= RX10;
end if;
end case;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
RX_10 <= rxd_10_i;
RX_100 <= rxd_100_i;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_loader.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_loader is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end rx_fifo_loader;
------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_loader is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
type STATES_TYPE is (
IPG,
PREAMBLE,
PREAMBLE_10,
RX100,
RX10
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal rx_cary_sense_i : std_logic;
signal rx_data_valid_i : std_logic;
signal rx_end_of_packet_i : std_logic;
signal repeated_data_cnt : integer range 0 to 63;
signal phy2rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal phy2rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal dibit_cnt : std_logic_vector(3 downto 0);
signal sample_rxd_cnt : std_logic_vector(4 downto 0);
signal sample_rxd : std_logic;
signal rxd_is_idle : std_logic;
signal rxd_is_preamble : std_logic;
signal rxd_is_preamble10 : std_logic;
signal rxd_10_i : std_logic;
signal rxd_100_i : std_logic;
begin
------------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
------------------------------------------------------------------------------
--RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
--begin
-- if (Ref_Clk'event and Ref_Clk = '1') then
-- if (Sync_rst_n = '0') then
-- phy2Rmii_crs_dv_sr <= (others => '0');
-- else
-- phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
-- Phy2Rmii_crs_dv;
-- end if;
-- end if;
--end process;
------------------------------------------------------------------------------
-- RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_error <= '0';
Rx_cary_sense <= '0';
rx_cary_sense_i <= '0';
rx_end_of_packet_i <= '0';
Rx_data_valid <= '0';
phy2Rmii_crs_dv_sr <= (others => '0');
else
Rx_error <= Phy2Rmii_rx_er;
Rx_cary_sense <= rx_cary_sense_i;
Rx_data_valid <= rx_data_valid_i;
rx_end_of_packet_i <= (rxd_100_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(0)) or
(rxd_10_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(9));
rx_cary_sense_i <= (Phy2Rmii_crs_dv and rx_cary_sense_i) or
(Phy2Rmii_crs_dv and not rxd_10_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(1)) or
(Phy2Rmii_crs_dv and not rxd_100_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(11));
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) & Phy2Rmii_crs_dv;
end if;
if (Sync_rst_n = '0') then
rx_data_valid_i <= '0';
elsif (rx_data_valid_i = '0') then
rx_data_valid_i <= Phy2Rmii_crs_dv or phy2Rmii_crs_dv_sr(0);
elsif (rx_data_valid_i = '1') then
rx_data_valid_i <= not rx_end_of_packet_i;
end if;
end if;
end process;
Rx_end_of_packet <= rx_end_of_packet_i;
---------------------------------------------------------------------------
-- RXD_PIPELINE_DELAY_PROCESS
---------------------------------------------------------------------------
RXD_PIPELINE_DELAY_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
phy2rmii_rxd_d2 <= (others => '0');
phy2rmii_rxd_d1 <= (others => '0');
else
phy2rmii_rxd_d2 <= phy2rmii_rxd_d1;
phy2rmii_rxd_d1 <= Phy2Rmii_rxd;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- REPEATED_DATA_CNT_PROCESS
---------------------------------------------------------------------------
REPEATED_DATA_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
repeated_data_cnt <= 0;
elsif (phy2rmii_rxd_d1 = Phy2Rmii_rxd) then
if (repeated_data_cnt = 63) then
repeated_data_cnt <= 63;
else
repeated_data_cnt <= repeated_data_cnt + 1;
end if;
else
repeated_data_cnt <= 0;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- SAMPLE_RXD_CNT_PROCESS
---------------------------------------------------------------------------
SAMPLE_RXD_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
sample_rxd_cnt <= "00000";
sample_rxd <= '0';
elsif (rxd_10_i = '1') then
if (sample_rxd_cnt = "00000") then
sample_rxd <= '1';
else
sample_rxd <= '0';
end if;
sample_rxd_cnt <= sample_rxd_cnt(3 downto 0) & not sample_rxd_cnt(4);
elsif (rxd_is_preamble10 = '1') then
sample_rxd_cnt <= "10000";
else
sample_rxd_cnt <= "00001";
sample_rxd <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_CNT_PROCESS
---------------------------------------------------------------------------
DIBIT_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ((Sync_rst_n = '0') or (rxd_is_idle = '1')) then
dibit_cnt <= "0001";
elsif (rxd_is_preamble10 = '1') then
dibit_cnt <= "0100";
elsif ((sample_rxd = '1') and (rxd_is_idle = '0')) then
dibit_cnt <= dibit_cnt(2 downto 0) & (dibit_cnt(3));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_TO_BYTE_MAPPING_PROCESS
---------------------------------------------------------------------------
DIBIT_TO_BYTE_MAPPING_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
Rx_data <= (others => '0');
elsif (dibit_cnt(0) = '1') then
Rx_data(0) <= phy2rmii_rxd_d2(0);
Rx_data(1) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(1) = '1') then
Rx_data(2) <= phy2rmii_rxd_d2(0);
Rx_data(3) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(2) = '1') then
Rx_data(4) <= phy2rmii_rxd_d2(0);
Rx_data(5) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(3) = '1') then
Rx_data(6) <= phy2rmii_rxd_d2(0);
Rx_data(7) <= phy2rmii_rxd_d2(1);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR_FIFO_EN_PROCESS
---------------------------------------------------------------------------
WR_FIFO_EN_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_fifo_wr_en <= '0';
elsif ((sample_rxd = '1') and (dibit_cnt(3) = '1') and (rxd_is_idle = '0') and
(rxd_is_preamble10 = '0')) then
Rx_fifo_wr_en <= '1';
else
Rx_fifo_wr_en <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IPG;
else
present_state <= next_state;
end if;
case next_state is
when IPG =>
rxd_is_idle <= '1';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE =>
rxd_is_idle <= '0';
rxd_is_preamble <= '1';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE_10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '1';
rxd_100_i <= '0';
rxd_10_i <= '0';
when RX100 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '1';
rxd_10_i <= '0';
when RX10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '1';
end case;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
repeated_data_cnt,
phy2rmii_rxd_d1,
Phy2Rmii_rxd,
Phy2Rmii_crs_dv,
rx_data_valid_i
)
begin
case present_state is
when IPG =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "01") and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE;
else
next_state <= IPG;
end if;
when PREAMBLE =>
if ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt < 31) and (Phy2Rmii_rxd = "11")) then
next_state <= RX100;
elsif ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt > 30) and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE_10;
else
next_state <= PREAMBLE;
end if;
when PREAMBLE_10 =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "11")) then
next_state <= RX10;
else
next_state <= PREAMBLE_10;
end if;
when RX100 =>
if (rx_data_valid_i = '0')then
next_state <= IPG;
else
next_state <= RX100;
end if;
when RX10 =>
if (rx_data_valid_i = '0') then
next_state <= IPG;
else
next_state <= RX10;
end if;
end case;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
RX_10 <= rxd_10_i;
RX_100 <= rxd_100_i;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_loader.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_loader is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end rx_fifo_loader;
------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_loader is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
type STATES_TYPE is (
IPG,
PREAMBLE,
PREAMBLE_10,
RX100,
RX10
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal rx_cary_sense_i : std_logic;
signal rx_data_valid_i : std_logic;
signal rx_end_of_packet_i : std_logic;
signal repeated_data_cnt : integer range 0 to 63;
signal phy2rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal phy2rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal dibit_cnt : std_logic_vector(3 downto 0);
signal sample_rxd_cnt : std_logic_vector(4 downto 0);
signal sample_rxd : std_logic;
signal rxd_is_idle : std_logic;
signal rxd_is_preamble : std_logic;
signal rxd_is_preamble10 : std_logic;
signal rxd_10_i : std_logic;
signal rxd_100_i : std_logic;
begin
------------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
------------------------------------------------------------------------------
--RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
--begin
-- if (Ref_Clk'event and Ref_Clk = '1') then
-- if (Sync_rst_n = '0') then
-- phy2Rmii_crs_dv_sr <= (others => '0');
-- else
-- phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
-- Phy2Rmii_crs_dv;
-- end if;
-- end if;
--end process;
------------------------------------------------------------------------------
-- RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_error <= '0';
Rx_cary_sense <= '0';
rx_cary_sense_i <= '0';
rx_end_of_packet_i <= '0';
Rx_data_valid <= '0';
phy2Rmii_crs_dv_sr <= (others => '0');
else
Rx_error <= Phy2Rmii_rx_er;
Rx_cary_sense <= rx_cary_sense_i;
Rx_data_valid <= rx_data_valid_i;
rx_end_of_packet_i <= (rxd_100_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(0)) or
(rxd_10_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(9));
rx_cary_sense_i <= (Phy2Rmii_crs_dv and rx_cary_sense_i) or
(Phy2Rmii_crs_dv and not rxd_10_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(1)) or
(Phy2Rmii_crs_dv and not rxd_100_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(11));
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) & Phy2Rmii_crs_dv;
end if;
if (Sync_rst_n = '0') then
rx_data_valid_i <= '0';
elsif (rx_data_valid_i = '0') then
rx_data_valid_i <= Phy2Rmii_crs_dv or phy2Rmii_crs_dv_sr(0);
elsif (rx_data_valid_i = '1') then
rx_data_valid_i <= not rx_end_of_packet_i;
end if;
end if;
end process;
Rx_end_of_packet <= rx_end_of_packet_i;
---------------------------------------------------------------------------
-- RXD_PIPELINE_DELAY_PROCESS
---------------------------------------------------------------------------
RXD_PIPELINE_DELAY_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
phy2rmii_rxd_d2 <= (others => '0');
phy2rmii_rxd_d1 <= (others => '0');
else
phy2rmii_rxd_d2 <= phy2rmii_rxd_d1;
phy2rmii_rxd_d1 <= Phy2Rmii_rxd;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- REPEATED_DATA_CNT_PROCESS
---------------------------------------------------------------------------
REPEATED_DATA_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
repeated_data_cnt <= 0;
elsif (phy2rmii_rxd_d1 = Phy2Rmii_rxd) then
if (repeated_data_cnt = 63) then
repeated_data_cnt <= 63;
else
repeated_data_cnt <= repeated_data_cnt + 1;
end if;
else
repeated_data_cnt <= 0;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- SAMPLE_RXD_CNT_PROCESS
---------------------------------------------------------------------------
SAMPLE_RXD_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
sample_rxd_cnt <= "00000";
sample_rxd <= '0';
elsif (rxd_10_i = '1') then
if (sample_rxd_cnt = "00000") then
sample_rxd <= '1';
else
sample_rxd <= '0';
end if;
sample_rxd_cnt <= sample_rxd_cnt(3 downto 0) & not sample_rxd_cnt(4);
elsif (rxd_is_preamble10 = '1') then
sample_rxd_cnt <= "10000";
else
sample_rxd_cnt <= "00001";
sample_rxd <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_CNT_PROCESS
---------------------------------------------------------------------------
DIBIT_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ((Sync_rst_n = '0') or (rxd_is_idle = '1')) then
dibit_cnt <= "0001";
elsif (rxd_is_preamble10 = '1') then
dibit_cnt <= "0100";
elsif ((sample_rxd = '1') and (rxd_is_idle = '0')) then
dibit_cnt <= dibit_cnt(2 downto 0) & (dibit_cnt(3));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_TO_BYTE_MAPPING_PROCESS
---------------------------------------------------------------------------
DIBIT_TO_BYTE_MAPPING_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
Rx_data <= (others => '0');
elsif (dibit_cnt(0) = '1') then
Rx_data(0) <= phy2rmii_rxd_d2(0);
Rx_data(1) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(1) = '1') then
Rx_data(2) <= phy2rmii_rxd_d2(0);
Rx_data(3) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(2) = '1') then
Rx_data(4) <= phy2rmii_rxd_d2(0);
Rx_data(5) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(3) = '1') then
Rx_data(6) <= phy2rmii_rxd_d2(0);
Rx_data(7) <= phy2rmii_rxd_d2(1);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR_FIFO_EN_PROCESS
---------------------------------------------------------------------------
WR_FIFO_EN_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_fifo_wr_en <= '0';
elsif ((sample_rxd = '1') and (dibit_cnt(3) = '1') and (rxd_is_idle = '0') and
(rxd_is_preamble10 = '0')) then
Rx_fifo_wr_en <= '1';
else
Rx_fifo_wr_en <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IPG;
else
present_state <= next_state;
end if;
case next_state is
when IPG =>
rxd_is_idle <= '1';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE =>
rxd_is_idle <= '0';
rxd_is_preamble <= '1';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE_10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '1';
rxd_100_i <= '0';
rxd_10_i <= '0';
when RX100 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '1';
rxd_10_i <= '0';
when RX10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '1';
end case;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
repeated_data_cnt,
phy2rmii_rxd_d1,
Phy2Rmii_rxd,
Phy2Rmii_crs_dv,
rx_data_valid_i
)
begin
case present_state is
when IPG =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "01") and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE;
else
next_state <= IPG;
end if;
when PREAMBLE =>
if ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt < 31) and (Phy2Rmii_rxd = "11")) then
next_state <= RX100;
elsif ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt > 30) and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE_10;
else
next_state <= PREAMBLE;
end if;
when PREAMBLE_10 =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "11")) then
next_state <= RX10;
else
next_state <= PREAMBLE_10;
end if;
when RX100 =>
if (rx_data_valid_i = '0')then
next_state <= IPG;
else
next_state <= RX100;
end if;
when RX10 =>
if (rx_data_valid_i = '0') then
next_state <= IPG;
else
next_state <= RX10;
end if;
end case;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
RX_10 <= rxd_10_i;
RX_100 <= rxd_100_i;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_loader.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_loader is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end rx_fifo_loader;
------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_loader is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
type STATES_TYPE is (
IPG,
PREAMBLE,
PREAMBLE_10,
RX100,
RX10
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal rx_cary_sense_i : std_logic;
signal rx_data_valid_i : std_logic;
signal rx_end_of_packet_i : std_logic;
signal repeated_data_cnt : integer range 0 to 63;
signal phy2rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal phy2rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal dibit_cnt : std_logic_vector(3 downto 0);
signal sample_rxd_cnt : std_logic_vector(4 downto 0);
signal sample_rxd : std_logic;
signal rxd_is_idle : std_logic;
signal rxd_is_preamble : std_logic;
signal rxd_is_preamble10 : std_logic;
signal rxd_10_i : std_logic;
signal rxd_100_i : std_logic;
begin
------------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
------------------------------------------------------------------------------
--RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
--begin
-- if (Ref_Clk'event and Ref_Clk = '1') then
-- if (Sync_rst_n = '0') then
-- phy2Rmii_crs_dv_sr <= (others => '0');
-- else
-- phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
-- Phy2Rmii_crs_dv;
-- end if;
-- end if;
--end process;
------------------------------------------------------------------------------
-- RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_error <= '0';
Rx_cary_sense <= '0';
rx_cary_sense_i <= '0';
rx_end_of_packet_i <= '0';
Rx_data_valid <= '0';
phy2Rmii_crs_dv_sr <= (others => '0');
else
Rx_error <= Phy2Rmii_rx_er;
Rx_cary_sense <= rx_cary_sense_i;
Rx_data_valid <= rx_data_valid_i;
rx_end_of_packet_i <= (rxd_100_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(0)) or
(rxd_10_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(9));
rx_cary_sense_i <= (Phy2Rmii_crs_dv and rx_cary_sense_i) or
(Phy2Rmii_crs_dv and not rxd_10_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(1)) or
(Phy2Rmii_crs_dv and not rxd_100_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(11));
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) & Phy2Rmii_crs_dv;
end if;
if (Sync_rst_n = '0') then
rx_data_valid_i <= '0';
elsif (rx_data_valid_i = '0') then
rx_data_valid_i <= Phy2Rmii_crs_dv or phy2Rmii_crs_dv_sr(0);
elsif (rx_data_valid_i = '1') then
rx_data_valid_i <= not rx_end_of_packet_i;
end if;
end if;
end process;
Rx_end_of_packet <= rx_end_of_packet_i;
---------------------------------------------------------------------------
-- RXD_PIPELINE_DELAY_PROCESS
---------------------------------------------------------------------------
RXD_PIPELINE_DELAY_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
phy2rmii_rxd_d2 <= (others => '0');
phy2rmii_rxd_d1 <= (others => '0');
else
phy2rmii_rxd_d2 <= phy2rmii_rxd_d1;
phy2rmii_rxd_d1 <= Phy2Rmii_rxd;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- REPEATED_DATA_CNT_PROCESS
---------------------------------------------------------------------------
REPEATED_DATA_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
repeated_data_cnt <= 0;
elsif (phy2rmii_rxd_d1 = Phy2Rmii_rxd) then
if (repeated_data_cnt = 63) then
repeated_data_cnt <= 63;
else
repeated_data_cnt <= repeated_data_cnt + 1;
end if;
else
repeated_data_cnt <= 0;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- SAMPLE_RXD_CNT_PROCESS
---------------------------------------------------------------------------
SAMPLE_RXD_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
sample_rxd_cnt <= "00000";
sample_rxd <= '0';
elsif (rxd_10_i = '1') then
if (sample_rxd_cnt = "00000") then
sample_rxd <= '1';
else
sample_rxd <= '0';
end if;
sample_rxd_cnt <= sample_rxd_cnt(3 downto 0) & not sample_rxd_cnt(4);
elsif (rxd_is_preamble10 = '1') then
sample_rxd_cnt <= "10000";
else
sample_rxd_cnt <= "00001";
sample_rxd <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_CNT_PROCESS
---------------------------------------------------------------------------
DIBIT_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ((Sync_rst_n = '0') or (rxd_is_idle = '1')) then
dibit_cnt <= "0001";
elsif (rxd_is_preamble10 = '1') then
dibit_cnt <= "0100";
elsif ((sample_rxd = '1') and (rxd_is_idle = '0')) then
dibit_cnt <= dibit_cnt(2 downto 0) & (dibit_cnt(3));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_TO_BYTE_MAPPING_PROCESS
---------------------------------------------------------------------------
DIBIT_TO_BYTE_MAPPING_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
Rx_data <= (others => '0');
elsif (dibit_cnt(0) = '1') then
Rx_data(0) <= phy2rmii_rxd_d2(0);
Rx_data(1) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(1) = '1') then
Rx_data(2) <= phy2rmii_rxd_d2(0);
Rx_data(3) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(2) = '1') then
Rx_data(4) <= phy2rmii_rxd_d2(0);
Rx_data(5) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(3) = '1') then
Rx_data(6) <= phy2rmii_rxd_d2(0);
Rx_data(7) <= phy2rmii_rxd_d2(1);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR_FIFO_EN_PROCESS
---------------------------------------------------------------------------
WR_FIFO_EN_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_fifo_wr_en <= '0';
elsif ((sample_rxd = '1') and (dibit_cnt(3) = '1') and (rxd_is_idle = '0') and
(rxd_is_preamble10 = '0')) then
Rx_fifo_wr_en <= '1';
else
Rx_fifo_wr_en <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IPG;
else
present_state <= next_state;
end if;
case next_state is
when IPG =>
rxd_is_idle <= '1';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE =>
rxd_is_idle <= '0';
rxd_is_preamble <= '1';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE_10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '1';
rxd_100_i <= '0';
rxd_10_i <= '0';
when RX100 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '1';
rxd_10_i <= '0';
when RX10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '1';
end case;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
repeated_data_cnt,
phy2rmii_rxd_d1,
Phy2Rmii_rxd,
Phy2Rmii_crs_dv,
rx_data_valid_i
)
begin
case present_state is
when IPG =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "01") and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE;
else
next_state <= IPG;
end if;
when PREAMBLE =>
if ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt < 31) and (Phy2Rmii_rxd = "11")) then
next_state <= RX100;
elsif ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt > 30) and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE_10;
else
next_state <= PREAMBLE;
end if;
when PREAMBLE_10 =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "11")) then
next_state <= RX10;
else
next_state <= PREAMBLE_10;
end if;
when RX100 =>
if (rx_data_valid_i = '0')then
next_state <= IPG;
else
next_state <= RX100;
end if;
when RX10 =>
if (rx_data_valid_i = '0') then
next_state <= IPG;
else
next_state <= RX10;
end if;
end case;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
RX_10 <= rxd_10_i;
RX_100 <= rxd_100_i;
end simulation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc354.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00354ent IS
END c03s02b01x01p02n01i00354ent;
ARCHITECTURE c03s02b01x01p02n01i00354arch OF c03s02b01x01p02n01i00354ent IS
type b1 is array (0 to 'B') of integer;
type b2 is array (0.0 to 7) of real;
type days is (mon, tue, wed, thu, fri, sat, sun);
type weekdays is (mon, tue, wed, thu, fri);
type startdays is array (mon to wed) of integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00354 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00354arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc354.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00354ent IS
END c03s02b01x01p02n01i00354ent;
ARCHITECTURE c03s02b01x01p02n01i00354arch OF c03s02b01x01p02n01i00354ent IS
type b1 is array (0 to 'B') of integer;
type b2 is array (0.0 to 7) of real;
type days is (mon, tue, wed, thu, fri, sat, sun);
type weekdays is (mon, tue, wed, thu, fri);
type startdays is array (mon to wed) of integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00354 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00354arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc354.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00354ent IS
END c03s02b01x01p02n01i00354ent;
ARCHITECTURE c03s02b01x01p02n01i00354arch OF c03s02b01x01p02n01i00354ent IS
type b1 is array (0 to 'B') of integer;
type b2 is array (0.0 to 7) of real;
type days is (mon, tue, wed, thu, fri, sat, sun);
type weekdays is (mon, tue, wed, thu, fri);
type startdays is array (mon to wed) of integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00354 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00354arch;
|
-- NEED RESULT: ARCH00086.P1: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P2: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P3: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P4: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P5: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P6: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P7: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P8: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P9: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P10: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P11: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P12: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P13: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P14: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P15: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P16: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P17: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00086
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00086(ARCH00086)
-- ENT00086_Test_Bench(ARCH00086_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00086 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00086 ;
--
architecture ARCH00086 of ENT00086 is
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00086.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00086" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00086" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P17 ;
--
--
end ARCH00086 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00086_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00086_Test_Bench ;
--
architecture ARCH00086_Test_Bench of ENT00086_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00086 ( ARCH00086 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00086_Test_Bench ;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leon
-- File: leon.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Complete processor
------------------------------------------------------------------------------
-- 30.01.02 added 32 bits conversion for DDM and XSV800
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity leon is
port (
resetn : in std_logic; -- system signals
clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0); -- memory bus
---
datain : in std_logic_vector(31 downto 0); -- 32 bits conversion LA
dataout : out std_logic_vector(31 downto 0);
datasel : out std_logic_vector(3 downto 0);
---
ramsn : out std_logic_vector(3 downto 0);
ramoen : out std_logic_vector(3 downto 0);
rwen : inout std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : inout std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
---
pioo : out std_logic_vector(15 downto 0); -- I/O port 32 bits LA
pioi : in std_logic_vector(15 downto 0);
piod : out std_logic_vector(15 downto 0);
buttons : in std_logic_vector(3 downto 0); -- ddm ports
audioin : in std_logic;
digit0 : out std_logic_vector(6 downto 0);
digit1 : out std_logic_vector(6 downto 0);
audioout : out std_logic;
lr_out : out std_logic;
shift_clk : out std_logic;
mclk : out std_logic;
dispen : out std_logic;
---
wdogn : out std_logic; -- watchdog output
test : in std_logic
);
end;
architecture rtl of leon is
component mcore
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
--
ddmi : in ddm_in_type; -- DDM signals LA
ddmo : out ddm_out_type;
--
test : in std_logic
);
end component;
signal gnd, clko, resetno : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
--
signal ddmi : ddm_in_type; -- DDM signals LA
signal ddmo : ddm_out_type;
--
begin
gnd <= '0';
-- main processor core
mcore0 : mcore
port map (
resetn => resetno, clk => clko,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
-- pcii => pcii, pcio => pcio, test => test
pcii => pcii, pcio => pcio, ddmi => ddmi, ddmo => ddmo, test => test -- DDM LA
);
-- pads
-- clk_pad : inpad port map (clk, clko); -- clock
clko <= clk; -- avoid buffering during synthesis
-- original lines
reset_pad : smpad port map (resetn, resetno); -- reset
brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
--DDM lines
-- smpad0 : smpad port map (resetn, resetno); -- reset
-- inpad2 : inpad port map (brdyn, memi.brdyn); -- bus ready
-- inpad3 : inpad port map (bexcn, memi.bexcn); -- bus exception
-- outpad0 : odpad port map (ioo.errorn, errorn); -- cpu error mode
inpad4 : inpad port map (audioin, ddmi.audioin);
inpad5 : inpad port map (buttons(0),ddmi.button0);
inpad6 : inpad port map (buttons(1),ddmi.button1);
inpad7 : inpad port map (buttons(2),ddmi.button2);
inpad8 : inpad port map (buttons(3),ddmi.button3);
-- d_pads: for i in 0 to 31 generate -- data bus
-- d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
-- end generate;
dataout <= memo.data; -- databus DDM LA
memi.data <= datain;
datasel <= memo.bdrive;
-- pio_pads : for i in 0 to 15 generate -- parallel I/O port
-- pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
-- end generate;
pioo <= ioo.piol; -- parallel I/O port DDM
ioi.piol <= pioi;
piod <= ioo.piodir;
rwen(0) <= memo.wrn(0);
memi.wrn(0) <= memo.wrn(0);
rwen(1) <= memo.wrn(1);
memi.wrn(1) <= memo.wrn(1);
rwen(2) <= memo.wrn(2);
memi.wrn(2) <= memo.wrn(2);
rwen(3) <= memo.wrn(3);
memi.wrn(3) <= memo.wrn(3);
-- rwen_pads : for i in 0 to 3 generate -- ram write strobe
-- rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
-- end generate;
-- I/O write strobe
-- writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
writen <= memo.writen; -- DDM LA
memi.writen <= memo.writen;
a_pads: for i in 0 to 27 generate -- memory address
a_pad : outpad generic map (3) port map (memo.address(i), address(i));
end generate;
ramsn_pads : for i in 0 to 3 generate -- ram oen/rasn
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
end generate;
ramoen_pads : for i in 0 to 3 generate -- ram chip select
eamoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
end generate;
romsn_pads : for i in 0 to 1 generate -- rom chip select
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
end generate;
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
--
outpadb7: outpad port map (ddmo.shift_clk, shift_clk); -- DDM
outpadb8: outpad port map (ddmo.lr_out, lr_out);
outpadb9: outpad port map (ddmo.audioout, audioout);
outpadb10: for i in 0 to 6 generate
outpad101: outpad port map(ddmo.digit0(i), digit0(i));
end generate;
outpadb11: for i in 0 to 6 generate
outpad111: outpad port map(ddmo.digit1(i), digit1(i));
end generate;
outpadb12: outpad port map (ddmo.mclk, mclk);
dispen <= ddmo.dispen;
--
wd : if WDOGEN generate
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
end generate;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_top_ppro_sdram is
port (
CLK: in std_logic;
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
-- SPI flash
MOSI: out std_logic;
MISO: in std_logic;
SCK: out std_logic;
NCS: out std_logic;
--NNMI: in std_logic;
-- SD card
SDMOSI: out std_logic;
SDMISO: in std_logic;
SDSCK: out std_logic;
SDNCS: out std_logic;
HSYNC: out std_logic;
VSYNC: out std_logic;
BLUE: out std_logic_vector(3 downto 0);
GREEN: out std_logic_vector(3 downto 0);
RED: out std_logic_vector(3 downto 0);
JOY_FIRE2: in std_logic;
JOY_FIRE1: in std_logic;
JOY_LEFT: in std_logic;
JOY_RIGHT: in std_logic;
JOY_SEL: in std_logic;
JOY_UP: in std_logic;
JOY_DOWN: in std_logic;
AUDIO: out std_logic_vector(1 downto 0);
RESET: in std_logic
-- The LED
--LED: out std_logic
);
end entity xtc_top_ppro_sdram;
architecture behave of xtc_top_ppro_sdram is
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal clk_off_3ns: std_ulogic;
signal wbi: wb_mosi_type;
signal wbo: wb_miso_type;
signal dmawbi: wb_mosi_type;
signal dmawbo: wb_miso_type;
signal syscon: wb_syscon_type;
signal swbi: slot_wbi;
signal swbo: slot_wbo;
signal sids: slot_ids;
signal nmi, nmi_q, nmiack, rstreq,rstreq_q, do_reset: std_logic;
signal vgaclk: std_logic;
begin
AUDIO(0) <= '0';
AUDIO(1) <= '0';
process(sysclk)
begin
if rising_edge(sysclk) then
if sysrst='1' then
rstreq_q<='0';
else
rstreq_q<=rstreq;
end if;
end if;
end process;
do_reset<='1' when rstreq_q='0' and rstreq='1' else '0';
syscon.clk<=sysclk;
syscon.rst<=sysrst or do_reset;
cpu: entity work.xtc_top_sdram
port map (
wb_syscon => syscon,
iowbi => wbo,
iowbo => wbi,
nmi => nmi,
nmiack => nmiack,
rstreq => rstreq,
dmawbi => dmawbi,
dmawbo => dmawbo,
-- extra clocking
clk_off_3ns => clk_off_3ns,
-- SDRAM signals
DRAM_ADDR => DRAM_ADDR(11 downto 0),
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
--DRAM_ADDR(12)<='0';
ioctrl: entity work.xtc_ioctrl
port map (
syscon => syscon,
wbi => wbi,
wbo => wbo,
swbi => swbi,
swbo => swbo,
sids => sids
);
myrom: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(0),
wbo => swbi(0)
);
myuart: entity work.uart
generic map (
bits => 11
)
port map (
syscon => syscon,
wbi => swbo(1),
wbo => swbi(1),
tx => TXD,
rx => RXD
);
flashspi: entity work.spi
generic map (
INTERNAL_SPI => true
)
port map (
syscon => syscon,
wbi => swbo(2),
wbo => swbi(2),
mosi => MOSI,
miso => MISO,
sck => SCK,
cs => NCS
);
sdspi: entity work.spi
generic map (
INTERNAL_SPI => false
)
port map (
syscon => syscon,
wbi => swbo(3),
wbo => swbi(3),
mosi => SDMOSI,
miso => SDMISO,
sck => SDSCK,
cs => SDNCS
);
vgaenabled: if false generate
vga: entity work.vga_320_240_idx
port map (
wb_clk_i => syscon.clk,
wb_rst_i => syscon.rst,
wb_dat_o => swbi(4).dat,
wb_dat_i => swbo(4).dat,
wb_adr_i => swbo(4).adr(31 downto 2),
wb_we_i => swbo(4).we,
wb_cyc_i => swbo(4).cyc,
wb_stb_i => swbo(4).stb,
wb_ack_o => swbi(4).ack,
-- Wishbone MASTER interface
mi_wb_dat_i => dmawbo.dat,
mi_wb_dat_o => dmawbi.dat,
mi_wb_adr_o => dmawbi.adr,
mi_wb_sel_o => dmawbi.sel,
--mi_wb_cti_o => dmawbi.cti,
mi_wb_we_o => dmawbi.we,
mi_wb_cyc_o => dmawbi.cyc,
mi_wb_stb_o => dmawbi.stb,
mi_wb_ack_i => dmawbo.ack,
mi_wb_stall_i => dmawbo.stall,
-- VGA signals
vgaclk => vgaclk,
vga_hsync => HSYNC,
vga_vsync => VSYNC,
vga_b(0) => open,
vga_b(4 downto 1) => BLUE,
vga_r(0) => open,
vga_r(4 downto 1) => RED,
vga_g(0) => open,
vga_g(4 downto 1) => GREEN,
blank => open
);
end generate;
vgadisabled: if true generate
eslot: entity work.sinkdev
port map (
syscon => syscon,
wbi => swbo(4),
wbo => swbi(4)
);
dmawbi.dat <= (others => 'X');
dmawbi.adr <= (others => 'X');
dmawbi.sel <= (others => 'X');
dmawbi.we <='0';
dmawbi.cyc<='0';
dmawbi.stb<='0';
RED<=(others => '0');
GREEN<=(others => '0');
BLUE<=(others => '0');
HSYNC<='0';
VSYNC<='0';
end generate;
emptyslots: for N in 5 to 15 generate
eslot: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(N),
wbo => swbi(N)
);
--swbi(N) <= wb_miso_default;
end generate;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
rstgen: entity work.xtc_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => RXD,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: entity work.clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout1 => clk_off_3ns,
vgaclk => vgaclk,
rstout => clkgen_rst
);
-- NMI
process (sysclk)
begin
if rising_edge(sysclk) then
if sysrst='1' then
nmi <= '0';
else
if RESET='1' then
nmi<='1';
elsif nmiack='1' then
nmi<='0';
end if;
end if;
end if;
end process;
end behave;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY zpu_config_regs IS
GENERIC
(
platform : integer := 1; -- So ROM can detect which type of system...
spi_clock_div : integer := 4 -- Quite conservative by default - probably want to use 1 with 28MHz input clock, 2 for 57MHz input clock, 4 for 114MHz input clock etc
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
POKEY_ENABLE : in std_logic;
ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
WR_EN : IN STD_LOGIC;
-- GENERIC INPUT REGS (need to synchronize upstream...)
IN1 : in std_logic_vector(31 downto 0);
IN2 : in std_logic_vector(31 downto 0);
IN3 : in std_logic_vector(31 downto 0);
IN4 : in std_logic_vector(31 downto 0);
-- GENERIC OUTPUT REGS
OUT1 : out std_logic_vector(31 downto 0);
OUT2 : out std_logic_vector(31 downto 0);
OUT3 : out std_logic_vector(31 downto 0);
OUT4 : out std_logic_vector(31 downto 0);
-- SDCARD
SDCARD_CLK : out std_logic;
SDCARD_CMD : out std_logic;
SDCARD_DAT : in std_logic;
SDCARD_DAT3 : out std_logic;
-- SD DMA
sd_addr : out std_logic_vector(15 downto 0);
sd_data : out std_logic_vector(7 downto 0);
sd_write : out std_logic;
-- ATARI interface (in future we can also turbo load by directly hitting memory...)
SIO_DATA_IN : out std_logic;
SIO_COMMAND : in std_logic;
SIO_DATA_OUT : in std_logic;
-- CPU interface
DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
PAUSE_ZPU : out std_logic
);
END zpu_config_regs;
ARCHITECTURE vhdl OF zpu_config_regs IS
function vectorize(s: std_logic) return std_logic_vector is
variable v: std_logic_vector(0 downto 0);
begin
v(0) := s;
return v;
end;
signal addr_decoded : std_logic_vector(15 downto 0);
signal out1_next : std_logic_vector(31 downto 0);
signal out1_reg : std_logic_vector(31 downto 0);
signal out2_next : std_logic_vector(31 downto 0);
signal out2_reg : std_logic_vector(31 downto 0);
signal out3_next : std_logic_vector(31 downto 0);
signal out3_reg : std_logic_vector(31 downto 0);
signal out4_next : std_logic_vector(31 downto 0);
signal out4_reg : std_logic_vector(31 downto 0);
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal spi_busy : std_logic;
signal spi_enable : std_logic;
signal spi_chip_select : std_logic_vector(0 downto 0);
signal spi_clk_out : std_logic;
signal spi_tx_data : std_logic_vector(7 downto 0);
signal spi_rx_data : std_logic_vector(7 downto 0);
signal spi_addr_next : std_logic;
signal spi_addr_reg : std_logic;
signal spi_addr_reg_integer : integer;
signal spi_speed_next : std_logic_vector(7 downto 0);
signal spi_speed_reg : std_logic_vector(7 downto 0);
signal spi_speed_reg_integer : integer;
signal pokey_data_out : std_logic_vector(7 downto 0);
signal wr_en_pokey : std_logic;
signal pause_next : std_logic_vector(31 downto 0);
signal pause_reg : std_logic_vector(31 downto 0);
signal paused_next : std_logic;
signal paused_reg : std_logic;
signal spi_dma_addr_next : std_logic_vector(15 downto 0);
signal spi_dma_addrend_next : std_logic_vector(15 downto 0);
signal spi_dma_wr : std_logic;
signal spi_dma_next : std_logic;
signal spi_dma_addr_reg : std_logic_vector(15 downto 0);
signal spi_dma_addrend_reg : std_logic_vector(15 downto 0);
signal spi_dma_reg : std_logic;
begin
-- register
process(clk,reset_n)
begin
if (reset_n='0') then
out1_reg <= (others=>'0');
out2_reg <= (others=>'0');
out3_reg <= (others=>'0');
out4_reg <= (others=>'0');
spi_addr_reg <= '1';
spi_speed_reg <= X"80";
pause_reg <= (others=>'0');
paused_reg <= '0';
spi_dma_addr_reg <= (others=>'0');
spi_dma_addrend_reg <= (others=>'0');
spi_dma_reg <= '0';
elsif (clk'event and clk='1') then
out1_reg <= out1_next;
out2_reg <= out2_next;
out3_reg <= out3_next;
out4_reg <= out4_next;
spi_addr_reg <= spi_addr_next;
spi_speed_reg <= spi_speed_next;
pause_reg <= pause_next;
paused_reg <= paused_next;
spi_dma_addr_reg <= spi_dma_addr_next;
spi_dma_addrend_reg <= spi_dma_addrend_next;
spi_dma_reg <= spi_dma_next;
end if;
end process;
-- decode address
decode_addr1 : entity work.complete_address_decoder
generic map(width=>4)
port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
-- spi - for sd card access without bit banging...
-- 200KHz to start with - probably fine for 8-bit, can up it later after init
spi_master1 : entity work.spi_master
generic map(slaves=>1,d_width=>8)
port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
rx_data=>spi_rx_data,busy=>spi_busy);
-- spi-programming model:
-- reg for write/read
-- data (send/receive)
-- busy
-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
-- chip select
-- uart - another Pokey! Running at atari frequency.
wr_en_pokey <= addr(4) and wr_en;
pokey1 : entity work.pokey
port map (clk=>clk,ENABLE_179=>pokey_enable,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>wr_en_pokey,
reset_n=>reset_n,keyboard_response=>"11",pot_in=>X"00",
sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
data_out=>pokey_data_out,
sio_out1=>sio_data_in);
-- hardware regs for ZPU
--
-- 0-3: GENERIC INPUT (RO)
-- 4-7: GENERIC OUTPUT (R/W)
-- 8: PAUSE
-- 9: SPI_DATA
-- SPI_DATA (DONE)
-- W - write data (starts transmission)
-- R - read data (wait for complete first)
-- 10: SPI_STATE
-- SPI_STATE/SPI_CTRL (DONE)
-- R: 0=busy
-- W: 0=select_n, speed
-- 11: SIO
-- SIO
-- R: 0=CMD
-- 12: TYPE
-- FPGA board (DONE)
-- R(32 bits) 0=DE1
-- 13 : SPI_DMA
-- W(15 downto 0 = addr),(31 downto 16 = endAddr)
-- 16-31: POKEY! Low bytes only... i.e. pokey reg every 4 bytes...
-- Writes to registers
process(cpu_data_in,wr_en,addr,addr_decoded, spi_speed_reg, spi_addr_reg, out1_reg, out2_reg, out3_reg, out4_reg, pause_reg, pokey_enable, spi_dma_addr_reg, spi_dma_addrend_reg, spi_dma_reg, spi_busy, spi_dma_addr_next)
begin
spi_speed_next <= spi_speed_reg;
spi_addr_next <= spi_addr_reg;
spi_tx_data <= (others=>'0');
spi_enable <= '0';
out1_next <= out1_reg;
out2_next <= out2_reg;
out3_next <= out3_reg;
out4_next <= out4_reg;
paused_next <= '0';
pause_next <= pause_reg;
if (not(pause_reg = X"00000000")) then
if (POKEY_ENABLE='1') then
pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
end if;
paused_next <= '1';
end if;
spi_dma_addr_next <= spi_dma_addr_reg;
spi_dma_addrend_next <= spi_dma_addrend_reg;
spi_dma_wr <= '0';
spi_dma_next <= spi_dma_reg;
if (spi_dma_reg = '1') then
paused_next <= '1';
if (spi_busy = '0') then
spi_dma_wr <= '1';
spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+1);
spi_dma_next <= '0';
if (not(spi_dma_addr_next = spi_dma_addrend_reg)) then
spi_tx_data <= X"ff";
spi_enable <= '1';
spi_dma_next <= '1';
end if;
end if;
end if;
if (wr_en = '1' and addr(4) = '0') then
if(addr_decoded(4) = '1') then
out1_next <= cpu_data_in;
end if;
if(addr_decoded(5) = '1') then
out2_next <= cpu_data_in;
end if;
if(addr_decoded(6) = '1') then
out3_next <= cpu_data_in;
end if;
if(addr_decoded(7) = '1') then
out4_next <= cpu_data_in;
end if;
if(addr_decoded(8) = '1') then
pause_next <= cpu_data_in;
paused_next <= '1';
end if;
if(addr_decoded(9) = '1') then
-- TODO, check overrun?
spi_tx_data <= cpu_data_in(7 downto 0);
spi_enable <= '1';
end if;
if(addr_decoded(10) = '1') then
spi_addr_next <= cpu_data_in(0);
if (cpu_data_in(1) = '1') then
spi_speed_next <= X"80"; -- slow, for init
else
spi_speed_next <= std_logic_vector(to_unsigned(spi_clock_div,8)); -- turbo - up to 25MHz for SD, 20MHz for MMC I believe... If 1 then clock is half input, if 2 then clock is 1/4 input etc.
end if;
end if;
if(addr_decoded(13) = '1') then
paused_next <= '1';
spi_dma_addr_next <= cpu_data_in(15 downto 0);
spi_dma_addrend_next <= cpu_data_in(31 downto 16);
spi_dma_next <= '1';
spi_tx_data <= X"ff";
spi_enable <= '1';
end if;
end if;
end process;
-- Read from registers
process(addr,addr_decoded, in1, in2, in3, in4, out1_reg, out2_reg, out3_reg, out4_reg, SIO_COMMAND, spi_rx_data, spi_busy, pokey_data_out)
begin
data_out <= (others=>'0');
if (addr(4) = '0') then
if (addr_decoded(0) = '1') then
data_out <= in1;
end if;
if (addr_decoded(1) = '1') then
data_out <= in2;
end if;
if (addr_decoded(2) = '1') then
data_out <= in3;
end if;
if (addr_decoded(3) = '1') then
data_out <= in4;
end if;
if (addr_decoded(4) = '1') then
data_out <= out1_reg;
end if;
if (addr_decoded(5) = '1') then
data_out <= out2_reg;
end if;
if (addr_decoded(6) = '1') then
data_out <= out3_reg;
end if;
if (addr_decoded(7) = '1') then
data_out <= out4_reg;
end if;
if (addr_decoded(9) = '1') then
data_out(7 downto 0) <= spi_rx_data;
end if;
if (addr_decoded(10) = '1') then
data_out(0) <= spi_busy;
end if;
if(addr_decoded(11) = '1') then
data_out(0) <= SIO_COMMAND;
end if;
if (addr_decoded(12) = '1') then
data_out <= std_logic_vector(to_unsigned(platform,32));
end if;
else
data_out(7 downto 0) <= pokey_data_out;
end if;
end process;
-- outputs
PAUSE_ZPU <= paused_reg;
out1 <= out1_reg;
out2 <= out2_reg;
out3 <= out3_reg;
out4 <= out4_reg;
SDCARD_CLK <= spi_clk_out;
SDCARD_CMD <= spi_mosi;
spi_miso <= SDCARD_DAT; -- INPUT!! XXX
SDCARD_DAT3 <= spi_chip_select(0);
sd_addr <= spi_dma_addr_reg;
sd_data <= spi_rx_data;
sd_write <= spi_dma_wr;
end vhdl;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.numeric_std.all;
entity alu is
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end; --alu
architecture logic of alu is
signal do_add : std_logic;
signal sum : std_logic_vector(32 downto 0);
signal less_than : std_logic;
begin
sum <= STD_LOGIC_VECTOR( RESIZE(SIGNED(a_in), 33) + RESIZE(SIGNED(b_in), 33) ) WHEN alu_function = ALU_ADD
ELSE STD_LOGIC_VECTOR( RESIZE(SIGNED(a_in), 33) - RESIZE(SIGNED(b_in), 33) );
--sum <= bv_adder(a_in, b_in, do_add);
do_add <= '1' when alu_function = ALU_ADD else '0';
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
less_than <= sum(32) when (a_in(31) = b_in(31)) or (alu_function = ALU_LESS_THAN) else a_in(31);
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
GENERIC_ALU: if alu_type = "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function = ALU_ADD or alu_function = ALU_SUBTRACT else
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
ZERO(31 downto 1) & less_than when alu_function = ALU_LESS_THAN or alu_function = ALU_LESS_THAN_SIGNED else
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
a_in or b_in when alu_function=ALU_OR else
-- BEGIN ENABLE_(AND,ANDI)
a_in and b_in when alu_function=ALU_AND else
-- END ENABLE_(AND,ANDI)
-- BEGIN ENABLE_(XOR,XORI)
a_in xor b_in when alu_function=ALU_XOR else
-- END ENABLE_(XOR,XORI)
-- BEGIN ENABLE_(NOR)
a_in nor b_in when alu_function=ALU_NOR else
-- END ENABLE_(NOR)
ZERO;
end generate;
AREA_OPTIMIZED_ALU: if alu_type /= "DEFAULT" generate
c_alu <= sum (31 downto 0) when alu_function = ALU_ADD or alu_function = ALU_SUBTRACT else (others => 'Z');
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
c_alu <= ZERO(31 downto 1) & less_than when alu_function = ALU_LESS_THAN or alu_function = ALU_LESS_THAN_SIGNED else (others => 'Z');
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
c_alu <= a_in or b_in when alu_function = ALU_OR else (others => 'Z');
-- BEGIN ENABLE_(AND,ANDI)
c_alu <= a_in and b_in when alu_function = ALU_AND else (others => 'Z');
-- END ENABLE_(AND,ANDI)
-- BEGIN ENABLE_(XOR,XORI)
c_alu <= a_in xor b_in when alu_function = ALU_XOR else (others => 'Z');
-- END ENABLE_(XOR,XORI)
-- BEGIN ENABLE_(NOR)
c_alu <= a_in nor b_in when alu_function = ALU_NOR else (others => 'Z');
-- END ENABLE_(NOR)
c_alu <= ZERO when alu_function = ALU_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Title : test1
-- Project :
-------------------------------------------------------------------------------
-- File : test1.vhd
-- Author : <kristoffer.nordstrom@HELVNB0100>
-- Company :
-- Created : 2015-04-27
-- Last update: 2015-04-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-27 1.0 kn Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity test1 is
port (
Clk : in std_logic;
Clr : in std_logic;
Test1_A : in std_logic_vector(3 downto 0);
Test1_B : in std_logic_vector(3 downto 0);
Test1_AB : out std_logic_vector(4 downto 0)
);
end entity test1;
-------------------------------------------------------------------------------
architecture str of test1 is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal AB : unsigned(Test1_AB'range);
begin -- architecture str
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
Test1_AB <= std_logic_vector(AB);
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
p_addAandB: process (Clk) is
begin -- process p_addAandB
if Clk'event and Clk = '1' then -- rising clock edge
if Clr = '1' then
AB <= to_unsigned(0, AB'length);
else
AB <= resize(unsigned(Test1_A), AB'length) + resize(unsigned(Test1_B), AB'length);
end if;
end if;
end process p_addAandB;
end architecture str;
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 02/11/2018 03:24:43 PM
-- Module Name: sext - Behavioral
-- Description: Sign extender for immediate values
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity sext is
Port(
imm12: in std_logic_vector(11 downto 0);
imm20: in std_logic_vector(19 downto 0);
output_imm12: out std_logic_vector(63 downto 0);
output_imm20: out std_logic_vector(63 downto 0)
);
end sext;
architecture Behavioral of sext is
begin
output_imm12(63 downto 12) <= (others => imm12(11));
output_imm12(11 downto 0) <= imm12;
output_imm20(63 downto 20) <= (others => imm20(19));
output_imm20(19 downto 0) <= imm20;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity pid is
generic
(
-- Coefficients are shifted left is positive and right if negative
-- Proportional coefficient
P_SHIFT_N : integer;
-- Integral coefficient
I_SHIFT_N : integer;
-- Number of bits in the filter
BITS_N : positive;
-- Initial output value
INIT_OUT_VAL : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
upd_clk_in : in std_logic;
setpoint_in : in signed(BITS_N - 1 downto 0);
pid_in : in signed(BITS_N - 1 downto 0);
pid_out : out signed(BITS_N - 1 downto 0)
);
end entity;
architecture rtl of pid is
begin
pid_p: process(clk, reset)
variable step : std_logic;
variable setpoint_err : signed(BITS_N - 1 downto 0);
variable prop : signed(BITS_N + 2 downto 0);
variable integ : signed(BITS_N + 2 downto 0);
variable sum : signed(BITS_N + 2 downto 0);
variable last_state : std_logic;
begin
if reset = '1' then
step := '0';
pid_out <= to_signed(INIT_OUT_VAL, pid_out'length);
setpoint_err := (others => '0');
integ := (others => '0');
prop := (others => '0');
sum := (others => '0');
last_state := '0';
elsif rising_edge(clk) then
if not upd_clk_in = last_state and upd_clk_in = '1' then
setpoint_err := setpoint_in - pid_in;
if P_SHIFT_N < 0 then
prop := shift_right(resize(setpoint_err, prop'length)
, -P_SHIFT_N);
else
prop := shift_left(resize(setpoint_err, prop'length)
, P_SHIFT_N);
end if;
-- Stop integrating to precent windup
if integ + setpoint_err >= 2**(integ'length - 2) - 1 then
integ := to_signed(2**(integ'length - 2) - 1
, integ'length);
elsif integ + setpoint_err <= -2**(integ'length - 2) + 1 then
integ := to_signed(-2**(integ'length - 2) + 1
, integ'length);
else
integ := integ + setpoint_err;
end if;
if I_SHIFT_N < 0 then
sum := prop + shift_right(integ, -I_SHIFT_N);
else
sum := prop + shift_left(integ, I_SHIFT_N);
end if;
step := '1';
elsif step = '1' then
if sum >= 2**(pid_out'length - 1) - 1 then
sum := to_signed(2**(pid_out'length - 1) - 1, sum'length);
elsif sum <= -2**(pid_out'length - 1) + 1 then
sum := to_signed(-2**(pid_out'length - 1) + 1, sum'length);
end if;
pid_out <= resize(sum, pid_out'length);
step := '0';
end if;
last_state := upd_clk_in;
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1086.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01086ent IS
END c06s05b00x00p02n01i01086ent;
ARCHITECTURE c06s05b00x00p02n01i01086arch OF c06s05b00x00p02n01i01086ent IS
BEGIN
TESTING: PROCESS
variable str : string (1 to 25) := "This is array slice check";
variable k : integer;
BEGIN
if str(1 to 3) = "Thi" then -- Success_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c06s05b00x00p02n01i01086"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c06s05b00x00p02n01i01086 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01086arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1086.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01086ent IS
END c06s05b00x00p02n01i01086ent;
ARCHITECTURE c06s05b00x00p02n01i01086arch OF c06s05b00x00p02n01i01086ent IS
BEGIN
TESTING: PROCESS
variable str : string (1 to 25) := "This is array slice check";
variable k : integer;
BEGIN
if str(1 to 3) = "Thi" then -- Success_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c06s05b00x00p02n01i01086"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c06s05b00x00p02n01i01086 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01086arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1086.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01086ent IS
END c06s05b00x00p02n01i01086ent;
ARCHITECTURE c06s05b00x00p02n01i01086arch OF c06s05b00x00p02n01i01086ent IS
BEGIN
TESTING: PROCESS
variable str : string (1 to 25) := "This is array slice check";
variable k : integer;
BEGIN
if str(1 to 3) = "Thi" then -- Success_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c06s05b00x00p02n01i01086"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c06s05b00x00p02n01i01086 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01086arch;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This is the TOP-Level for TG68KdotC_Kernel to generate 68K Bus signals --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68K is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
vpa : in std_logic:='1';
ein : in std_logic:='1';
addr : buffer std_logic_vector(31 downto 0);
data_read : in std_logic_vector(15 downto 0);
data_write : buffer std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
e : out std_logic;
vma : buffer std_logic:='1';
wrd : out std_logic;
ena7RDreg : in std_logic:='1';
ena7WRreg : in std_logic:='1';
enaWRreg : in std_logic:='1';
fromram : in std_logic_vector(15 downto 0);
ramready : in std_logic:='0';
cpu : in std_logic_vector(1 downto 0);
fastramcfg : in std_logic_vector(2 downto 0);
eth_en : in std_logic:='0';
sel_eth : buffer std_logic;
frometh : in std_logic_vector(15 downto 0);
ethready : in std_logic;
turbochipram : in std_logic;
turbokick : in std_logic;
cache_inhibit : out std_logic;
ovr : in std_logic;
ramaddr : out std_logic_vector(31 downto 0);
cpustate : out std_logic_vector(5 downto 0);
nResetOut : buffer std_logic;
skipFetch : buffer std_logic;
cpuDMA : buffer std_logic;
ramlds : out std_logic;
ramuds : out std_logic;
CACR_out : buffer std_logic_vector(3 downto 0);
VBR_out : buffer std_logic_vector(31 downto 0)
);
end TG68K;
ARCHITECTURE logic OF TG68K IS
COMPONENT TG68KdotC_Kernel
generic(
SR_Read : integer := 2; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer := 2; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer := 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 2 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(
clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only same parts - yet)
addr_out : buffer std_logic_vector(31 downto 0);
data_write : buffer std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
skipFetch : out std_logic;
regin_out : buffer std_logic_vector(31 downto 0);
CACR_out : buffer std_logic_vector(3 downto 0);
VBR_out : buffer std_logic_vector(31 downto 0)
);
END COMPONENT;
SIGNAL cpuaddr : std_logic_vector(31 downto 0);
SIGNAL r_data : std_logic_vector(15 downto 0);
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL vpad : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
SIGNAL vmaena : std_logic;
SIGNAL state_ena : std_logic;
SIGNAL eind : std_logic;
SIGNAL eindd : std_logic;
SIGNAL sel_autoconfig : std_logic;
SIGNAL autoconfig_out : std_logic_vector(1 downto 0); -- We use this as a counter since we have two cards to configure
SIGNAL autoconfig_data : std_logic_vector(3 downto 0); -- Zorro II RAM
SIGNAL autoconfig_data2 : std_logic_vector(3 downto 0); -- Zorro III RAM
SIGNAL autoconfig_data3 : std_logic_vector(3 downto 0); -- Zorro III ethernet
SIGNAL sel_fast : std_logic;
SIGNAL sel_chipram : std_logic;
SIGNAL turbochip_ena : std_logic := '0';
SIGNAL turbochip_d : std_logic := '0';
SIGNAL turbokick_d : std_logic := '0';
SIGNAL slower : std_logic_vector(3 downto 0);
TYPE sync_states IS (sync0, sync1, sync2, sync3, sync4, sync5, sync6, sync7, sync8, sync9);
SIGNAL sync_state : sync_states;
SIGNAL datatg68 : std_logic_vector(15 downto 0);
SIGNAL ramcs : std_logic;
SIGNAL z2ram_ena : std_logic;
SIGNAL z3ram_base : std_logic_vector(7 downto 0);
SIGNAL z3ram_ena : std_logic;
SIGNAL eth_base : std_logic_vector(7 downto 0);
SIGNAL eth_cfgd : std_logic;
SIGNAL sel_z2ram : std_logic;
SIGNAL sel_z3ram : std_logic;
SIGNAL sel_kickram : std_logic;
--SIGNAL sel_eth : std_logic;
SIGNAL NMI_vector : std_logic_vector(15 downto 0);
SIGNAL NMI_addr : std_logic_vector(31 downto 0);
SIGNAL NMI_active : std_logic;
SIGNAL sel_interrupt : std_logic;
SIGNAL cpuaddr_w : std_logic_vector(31 downto 0);
SIGNAL data_write_w : std_logic_vector(15 downto 0);
SIGNAL state_w : std_logic_vector(1 downto 0);
SIGNAL wr_w : std_logic;
SIGNAL uds_in_w : std_logic;
SIGNAL lds_in_w : std_logic;
SIGNAL nResetOut_w : std_logic;
SIGNAL skipFetch_w : std_logic;
SIGNAL CACR_out_w : std_logic_vector(3 downto 0);
SIGNAL VBR_out_w : std_logic_vector(31 downto 0);
BEGIN
-- NMI
PROCESS(clk) BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
NMI_addr <= X"0000007c";
NMI_active <= '0';
ELSE
NMI_addr <= VBR_out + X"0000007c";
IF (IPL="000") THEN
NMI_active <= '1';
ELSIF (cpuaddr(23 downto 1) = "1111111111111111111111") THEN
NMI_active <= '0';
END IF;
END IF;
END IF;
END PROCESS;
NMI_vector <= X"000c" WHEN cpuaddr(1)='1' ELSE X"00a0"; -- 16-bit bus!
wrd <= wr;
addr <= cpuaddr;
datatg68 <= NMI_vector WHEN sel_interrupt='1' ELSE
fromram WHEN sel_fast='1'
--ELSE frometh WHEN sel_eth='1'
ELSE autoconfig_data&r_data(11 downto 0) WHEN sel_autoconfig='1' AND autoconfig_out="01" -- Zorro II RAM autoconfig
ELSE autoconfig_data2&r_data(11 downto 0) WHEN sel_autoconfig='1' AND autoconfig_out="10" -- Zorro III RAM autoconfig
--ELSE autoconfig_data3&r_data(11 downto 0) WHEN sel_autoconfig='1' AND autoconfig_out="11" -- Zorro III ethernet autoconfig
ELSE r_data;
sel_autoconfig <= '1' WHEN fastramcfg(2 downto 0)/="000" AND cpuaddr(23 downto 19)="11101" AND autoconfig_out/="00" ELSE '0'; --$E80000 - $EFFFFF
sel_z3ram <= '1' WHEN (cpuaddr(31 downto 24)=z3ram_base) AND z3ram_ena='1' ELSE '0';
sel_z2ram <= '1' WHEN (cpuaddr(31 downto 24) = "00000000") AND ((cpuaddr(23 downto 21) = "001") OR (cpuaddr(23 downto 21) = "010") OR (cpuaddr(23 downto 21) = "011") OR (cpuaddr(23 downto 21) = "100")) AND z2ram_ena='1' ELSE '0';
--sel_eth <= '1' WHEN (cpuaddr(31 downto 24) = eth_base) AND eth_cfgd='1' ELSE '0';
sel_chipram <= '1' WHEN (cpuaddr(31 downto 24) = "00000000") AND (cpuaddr(23 downto 21)="000") AND turbochip_ena='1' AND turbochip_d='1' ELSE '0'; --$000000 - $1FFFFF
--sel_chipram <= '1' WHEN sel_z3ram/='1' AND turbochip_ena='1' AND turbochip_d='1' AND (cpuaddr(23 downto 21)="000") ELSE '0'; --$000000 - $1FFFFF
sel_kickram <= '1' WHEN (cpuaddr(31 downto 24) = "00000000") AND ((cpuaddr(23 downto 19)="11111") OR (cpuaddr(23 downto 19)="11100")) AND turbochip_ena='1' AND turbokick_d='1' ELSE '0'; -- $f8xxxx, e0xxxx
--sel_kickram <= '1' WHEN sel_z3ram/='1' AND turbochip_ena='1' AND turbokick_d='1' AND (cpuaddr(23 downto 19)="11111") ELSE '0'; -- $f8xxxx
sel_interrupt <= '1' WHEN (cpuaddr(31 downto 2) = NMI_addr(31 downto 2)) AND wr='0' ELSE '0';
sel_fast <= '1' WHEN state/="01" AND (
sel_z2ram='1'
OR sel_z3ram='1'
OR sel_chipram='1'
OR sel_kickram='1'
) ELSE '0';
--sel_fast <= '1' when state/="01" AND (
-- cpuaddr(23 downto 21)="001"
-- OR cpuaddr(23 downto 21)="010"
-- OR cpuaddr(23 downto 21)="011"
-- OR cpuaddr(23 downto 21)="100"
-- OR sel_z3ram='1'
-- OR sel_chipram='1'
-- OR sel_kickram='1'
-- ) ELSE '0'; --$200000 - $9FFFFF
cache_inhibit <= '1' WHEN sel_chipram='1' OR sel_kickram='1' ELSE '0';
--ramcs <= (NOT sel_fast AND NOT sel_eth) or slower(0);-- OR (state(0) AND NOT state(1));
ramcs <= (NOT sel_fast) or slower(0);-- OR (state(0) AND NOT state(1));
cpuDMA <= sel_fast;
cpustate <= clkena&slower(1 downto 0)&ramcs&state;
ramlds <= lds_in;
ramuds <= uds_in;
ramaddr(31 downto 25) <= "0000000";
ramaddr(24) <= sel_z3ram; -- Remap the Zorro III RAM to 0x1000000
ramaddr(23 downto 21)
<= "100" WHEN sel_z2ram&cpuaddr(23 downto 21)="1001" -- 2 -> 8
ELSE "101" WHEN sel_z2ram&cpuaddr(23 downto 21)="1010" -- 4 -> A
ELSE "110" WHEN sel_z2ram&cpuaddr(23 downto 21)="1011" -- 6 -> C
ELSE "111" WHEN sel_z2ram&cpuaddr(23 downto 21)="1100" -- 8 -> E
ELSE "001" WHEN sel_kickram='1'
ELSE cpuaddr(23 downto 21); -- pass through others
ramaddr(20 downto 19)
<= "11" WHEN sel_kickram='1' AND cpuaddr(23 downto 19)="11111"
ELSE "00" WHEN sel_kickram='1' AND cpuaddr(23 downto 19)="11100"
ELSE cpuaddr(20 downto 19);
ramaddr(18 downto 0) <= cpuaddr(18 downto 0);
--ramaddr(23 downto 21) <= "100" when sel_z3ram&cpuaddr(23 downto 21)="0001" -- 2 -> 8
-- else "101" when sel_z3ram&cpuaddr(23 downto 21)="0010" -- 4 -> A
-- else "110" when sel_z3ram&cpuaddr(23 downto 21)="0011" -- 6 -> C
-- else "111" when sel_z3ram&cpuaddr(23 downto 21)="0100" -- 8 -> E
-- else "001" when sel_kickram='1'
-- else cpuaddr(23 downto 21); -- pass through others
--ramaddr(20 downto 19) <= "11" when sel_kickram='1'
-- else cpuaddr(20 downto 19);
--ramaddr(18 downto 0) <= cpuaddr(18 downto 0);
pf68K_Kernel_inst: TG68KdotC_Kernel
generic map (
SR_Read => 2, -- 0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe => 2, -- 0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode => 2, -- 0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode => 2, -- 0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode => 2 -- 0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
)
PORT MAP (
clk => clk, -- : in std_logic;
nReset => reset, -- : in std_logic:='1'; --low active
clkena_in => clkena, -- : in std_logic:='1';
data_in => datatg68, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0):="111";
IPL_autovector => '1', -- : in std_logic:='0';
CPU => cpu,
regin_out => open, -- : out std_logic_vector(31 downto 0);
addr_out => cpuaddr, -- : buffer std_logic_vector(31 downto 0);
data_write => data_write, -- : out std_logic_vector(15 downto 0);
busstate => state, -- : buffer std_logic_vector(1 downto 0);
nWr => wr, -- : out std_logic;
nUDS => uds_in,
nLDS => lds_in, -- : out std_logic;
nResetOut => nResetOut,
skipFetch => skipFetch, -- : out std_logic
CACR_out => CACR_out,
VBR_out => VBR_out
--addr_out => cpuaddr_w, -- : buffer std_logic_vector(31 downto 0);
--data_write => data_write_w, -- : out std_logic_vector(15 downto 0);
--busstate => state_w, -- : buffer std_logic_vector(1 downto 0);
--nWr => wr_w, -- : out std_logic;
--nUDS => uds_in_w,
--nLDS => lds_in_w, -- : out std_logic;
--nResetOut => nResetOut_w,
--skipFetch => skipFetch_w, -- : out std_logic
--CACR_out => CACR_out_w,
--VBR_out => VBR_out_w
);
--PROCESS (clk) BEGIN
-- IF rising_edge(clk) THEN
-- IF reset='0' THEN
-- cpuaddr <= X"00000000";
-- data_write <= X"0000";
-- state <= "01";
-- wr <= '1';
-- uds_in <= '1';
-- lds_in <= '1';
-- nResetOut <= '1';
-- skipFetch <= '0';
-- CACR_out <= "0000";
-- VBR_out <= X"00000000";
-- ELSE
-- cpuaddr <= cpuaddr_w;
-- data_write <= data_write_w;
-- state <= state_w;
-- wr <= wr_w;
-- uds_in <= uds_in_w;
-- lds_in <= lds_in_w;
-- nResetOut <= nResetOut_w;
-- skipFetch <= skipFetch_w;
-- CACR_out <= CACR_out_w;
-- VBR_out <= VBR_out_w;
-- END IF;
-- END IF;
--END PROCESS;
PROCESS(clk,turbochipram, turbokick) BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
turbochip_d <= '0';
turbokick_d <= '0';
ELSIF state="01" THEN -- No mem access, so safe to switch chipram access mode
turbochip_d<=turbochipram;
turbokick_d<=turbokick;
END IF;
END IF;
END PROCESS;
PROCESS (clk) BEGIN
-- Zorro II RAM (Up to 8 meg at 0x200000)
autoconfig_data <= "1111";
IF fastramcfg/="000" THEN
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data <= "1110"; -- Zorro-II card, add mem, no ROM
WHEN "000001" => --autoconfig_data <= "0111"; -- 4MB
CASE fastramcfg(1 downto 0) IS
WHEN "01" => autoconfig_data <= "0110"; -- 2MB
WHEN "10" => autoconfig_data <= "0111"; -- 4MB
WHEN OTHERS => autoconfig_data <= "0000"; -- 8MB
END CASE;
WHEN "001000" => autoconfig_data <= "1110"; -- Manufacturer ID: 0x139c
WHEN "001001" => autoconfig_data <= "1100";
WHEN "001010" => autoconfig_data <= "0110";
WHEN "001011" => autoconfig_data <= "0011";
WHEN "010011" => autoconfig_data <= "1110"; --serial=1
WHEN OTHERS => null;
END CASE;
END IF;
-- Zorro III RAM (Up to 16 meg, address assigned by ROM)
autoconfig_data2 <= "1111";
IF fastramcfg(2)='1' THEN -- Zorro III RAM
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data2 <= "1010"; -- Zorro-III card, add mem, no ROM
WHEN "000001" => autoconfig_data2 <= "0000"; -- 8MB (extended to 16 in reg 08)
WHEN "000010" => autoconfig_data2 <= "1110"; -- ProductID=0x10 (only setting upper nibble)
WHEN "000100" => autoconfig_data2 <= "0000"; -- Memory card, not silenceable, Extended size (16 meg), reserved.
WHEN "000101" => autoconfig_data2 <= "1111"; -- 0000 - logical size matches physical size TODO change this to 0001, so it is autosized by the OS, WHEN it will be 24MB.
WHEN "001000" => autoconfig_data2 <= "1110"; -- Manufacturer ID: 0x139c
WHEN "001001" => autoconfig_data2 <= "1100";
WHEN "001010" => autoconfig_data2 <= "0110";
WHEN "001011" => autoconfig_data2 <= "0011";
WHEN "010011" => autoconfig_data2 <= "1101"; -- serial=2
WHEN OTHERS => null;
END CASE;
END IF;
-- Zorro III ethernet
autoconfig_data3 <= "1111";
IF eth_en='1' THEN
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data3 <= "1000"; -- 00H: Zorro-III card, no link, no ROM
WHEN "000001" => autoconfig_data3 <= "0001"; -- 00L: next board not related, size 64K
WHEN "000010" => autoconfig_data3 <= "1101"; -- 04H: ProductID=0x20 (only setting upper nibble)
WHEN "000100" => autoconfig_data3 <= "1110"; -- 08H: Not memory, silenceable, normal size, Zorro III
WHEN "000101" => autoconfig_data3 <= "1101"; -- 08L: Logical size 64K
WHEN "001000" => autoconfig_data3 <= "1110"; -- Manufacturer ID: 0x139c
WHEN "001001" => autoconfig_data3 <= "1100";
WHEN "001010" => autoconfig_data3 <= "0110";
WHEN "001011" => autoconfig_data3 <= "0011";
WHEN "010011" => autoconfig_data3 <= "1100"; -- serial=2
WHEN OTHERS => null;
END CASE;
END IF;
IF rising_edge(clk) THEN
IF reset='0' THEN
autoconfig_out <= "01"; --autoconfig on
turbochip_ena <= '0'; -- disable turbo_chipram until we know kickstart's running...
z2ram_ena <='0';
z3ram_ena <='0';
z3ram_base<=X"01";
--eth_cfgd <='0';
--eth_base<=X"02";
ELSIF enaWRreg='1' THEN
IF sel_autoconfig='1' AND state="11"AND uds_in='0' AND clkena='1' THEN
CASE cpuaddr(6 downto 1) IS
WHEN "100100" => -- Register 0x48 - config
IF autoconfig_out="01" THEN
z2ram_ena <= '1';
autoconfig_out<=fastramcfg(2)&'0';
END IF;
turbochip_ena <= '1'; -- enable turbo_chipram after autoconfig has been done...
-- FIXME - this is a hack to allow ROM overlay to work.
WHEN "100010" => -- Register 0x44, assign base address to ZIII RAM.
-- We ought to take 16 bits here, but for now we take liberties and use a single byte.
IF autoconfig_out="10" THEN
z3ram_base<=data_write(15 downto 8);
z3ram_ena <='1';
-- autoconfig_out<= eth_en & eth_en;
-- ELSIF autoconfig_out="11" THEN
-- eth_base <= data_write(15 downto 8);
-- eth_cfgd <= '1';
autoconfig_out <= "00";
END IF;
WHEN others =>
null;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
vmaena <= '0';
ELSIF ena7RDreg='1' THEN
vmaena <= '0';
IF sync_state=sync5 THEN
e <= '1';
END IF;
IF sync_state=sync9 THEN
e <= '0';
vmaena <= NOT vma;
END IF;
END IF;
END IF;
IF rising_edge(clk) THEN
IF ena7WRreg='1' THEN
eind <= ein;
eindd <= eind;
CASE sync_state IS
WHEN sync0 => sync_state <= sync1;
WHEN sync1 => sync_state <= sync2;
WHEN sync2 => sync_state <= sync3;
WHEN sync3 => sync_state <= sync4;
vma <= vpa;
WHEN sync4 => sync_state <= sync5;
WHEN sync5 => sync_state <= sync6;
WHEN sync6 => sync_state <= sync7;
WHEN sync7 => sync_state <= sync8;
WHEN sync8 => sync_state <= sync9;
WHEN OTHERS => sync_state <= sync0;
vma <= '1';
END CASE;
IF eind='1' AND eindd='0' THEN
sync_state <= sync7;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, clkena_in, enaWRreg, state, ena7RDreg, clkena_e, ramready) BEGIN
state_ena <= '0';
-- IF clkena_in='1' AND enaWRreg='1' AND (state="01" OR (ena7RDreg='1' AND clkena_e='1') OR ramready='1' OR ethready='1') THEN
IF clkena_in='1' AND enaWRreg='1' AND (state="01" OR (ena7RDreg='1' AND clkena_e='1') OR ramready='1') THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
IF state="01" THEN
state_ena <= '1';
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
slower <= "0111"; -- rokk
-- slower <= "0111";
ELSE
slower(3 downto 0) <= '0'&slower(3 downto 1); -- enaWRreg&slower(3 downto 1);
-- slower(0) <= NOT slower(3) AND NOT slower(2);
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e, sel_fast)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= (as_s AND as_e) OR sel_fast;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "00";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF ena7WRreg='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
CASE S_state IS
WHEN "00" => IF state/="01" AND sel_fast='0' THEN
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "01";
END IF;
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
r_data <= data_read;
IF waitm='0' OR (vma='0' AND sync_state=sync9) THEN
S_state <= "11";
ELSE
as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
ELSIF rising_edge(clk) THEN
IF ena7RDreg='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
CASE S_state IS
WHEN "00" =>
cpuIPL <= IPL;
IF sel_fast='0' THEN
IF state/="01" THEN
as_e <= '0';
END IF;
rw_e <= wr;
IF wr='1' THEN
uds_e <= uds_in;
lds_e <= lds_in;
END IF;
END IF;
WHEN "01" =>
as_e <= '0';
rw_e <= wr;
uds_e <= uds_in;
lds_e <= lds_in;
WHEN "10" => rw_e <= wr;
cpuIPL <= IPL;
waitm <= dtack;
WHEN OTHERS => --null;
clkena_e <= '1';
END CASE;
END IF;
END IF;
END PROCESS;
END;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ROM01_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : ROM01.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ROM01_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ROM01_prod;
ARCHITECTURE xilinx OF ROM01_prod IS
COMPONENT ROM01_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ROM01_exdes
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
library verilog;
use verilog.vl_types.all;
entity matching is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iFREE_DEFAULT : in vl_logic;
iFREE_RESTART : in vl_logic;
iCOMMIT_OFFSET : in vl_logic_vector(2 downto 0);
oLOOPBUFFER_LIMIT: out vl_logic;
iOTHER_INFO_RENAME_0_VALID: in vl_logic;
iOTHER_INFO_RENAME_1_VALID: in vl_logic;
iOTHER_INFO_SCHEDULER1_0_VALID: in vl_logic;
iOTHER_INFO_SCHEDULER1_1_VALID: in vl_logic;
iOTHER_INFO_SCHEDULER1_REGIST_POINTER: in vl_logic_vector(5 downto 0);
iOTHER_INFO_SCHEDULER1_COMMIT_POINTER: in vl_logic_vector(5 downto 0);
iPREVIOUS_0_VALID: in vl_logic;
iPREVIOUS_0_MMU_FLAGS: in vl_logic_vector(5 downto 0);
iPREVIOUS_0_SOURCE0_ACTIVE: in vl_logic;
iPREVIOUS_0_SOURCE1_ACTIVE: in vl_logic;
iPREVIOUS_0_SOURCE0_SYSREG: in vl_logic;
iPREVIOUS_0_SOURCE1_SYSREG: in vl_logic;
iPREVIOUS_0_SOURCE0_SYSREG_RENAME: in vl_logic;
iPREVIOUS_0_SOURCE1_SYSREG_RENAME: in vl_logic;
iPREVIOUS_0_ADV_ACTIVE: in vl_logic;
iPREVIOUS_0_DESTINATION_SYSREG: in vl_logic;
iPREVIOUS_0_DEST_RENAME: in vl_logic;
iPREVIOUS_0_WRITEBACK: in vl_logic;
iPREVIOUS_0_FLAGS_WRITEBACK: in vl_logic;
iPREVIOUS_0_FRONT_COMMIT_WAIT: in vl_logic;
iPREVIOUS_0_CMD : in vl_logic_vector(4 downto 0);
iPREVIOUS_0_CC_AFE: in vl_logic_vector(3 downto 0);
iPREVIOUS_0_SOURCE0: in vl_logic_vector(4 downto 0);
iPREVIOUS_0_SOURCE1: in vl_logic_vector(31 downto 0);
iPREVIOUS_0_ADV_DATA: in vl_logic_vector(5 downto 0);
iPREVIOUS_0_SOURCE0_FLAGS: in vl_logic;
iPREVIOUS_0_SOURCE1_IMM: in vl_logic;
iPREVIOUS_0_DESTINATION: in vl_logic_vector(4 downto 0);
iPREVIOUS_0_EX_SYS_ADDER: in vl_logic;
iPREVIOUS_0_EX_SYS_LDST: in vl_logic;
iPREVIOUS_0_EX_LOGIC: in vl_logic;
iPREVIOUS_0_EX_SHIFT: in vl_logic;
iPREVIOUS_0_EX_ADDER: in vl_logic;
iPREVIOUS_0_EX_MUL: in vl_logic;
iPREVIOUS_0_EX_SDIV: in vl_logic;
iPREVIOUS_0_EX_UDIV: in vl_logic;
iPREVIOUS_0_EX_LDST: in vl_logic;
iPREVIOUS_0_EX_BRANCH: in vl_logic;
iPREVIOUS_1_VALID: in vl_logic;
iPREVIOUS_1_MMU_FLAGS: in vl_logic_vector(5 downto 0);
iPREVIOUS_1_SOURCE0_ACTIVE: in vl_logic;
iPREVIOUS_1_SOURCE1_ACTIVE: in vl_logic;
iPREVIOUS_1_SOURCE0_SYSREG: in vl_logic;
iPREVIOUS_1_SOURCE1_SYSREG: in vl_logic;
iPREVIOUS_1_SOURCE0_SYSREG_RENAME: in vl_logic;
iPREVIOUS_1_SOURCE1_SYSREG_RENAME: in vl_logic;
iPREVIOUS_1_ADV_ACTIVE: in vl_logic;
iPREVIOUS_1_DESTINATION_SYSREG: in vl_logic;
iPREVIOUS_1_DEST_RENAME: in vl_logic;
iPREVIOUS_1_WRITEBACK: in vl_logic;
iPREVIOUS_1_FLAGS_WRITEBACK: in vl_logic;
iPREVIOUS_1_FRONT_COMMIT_WAIT: in vl_logic;
iPREVIOUS_1_CMD : in vl_logic_vector(4 downto 0);
iPREVIOUS_1_CC_AFE: in vl_logic_vector(3 downto 0);
iPREVIOUS_1_SOURCE0: in vl_logic_vector(4 downto 0);
iPREVIOUS_1_SOURCE1: in vl_logic_vector(31 downto 0);
iPREVIOUS_1_ADV_DATA: in vl_logic_vector(5 downto 0);
iPREVIOUS_1_SOURCE0_FLAGS: in vl_logic;
iPREVIOUS_1_SOURCE1_IMM: in vl_logic;
iPREVIOUS_1_DESTINATION: in vl_logic_vector(4 downto 0);
iPREVIOUS_1_EX_SYS_ADDER: in vl_logic;
iPREVIOUS_1_EX_SYS_LDST: in vl_logic;
iPREVIOUS_1_EX_LOGIC: in vl_logic;
iPREVIOUS_1_EX_SHIFT: in vl_logic;
iPREVIOUS_1_EX_ADDER: in vl_logic;
iPREVIOUS_1_EX_MUL: in vl_logic;
iPREVIOUS_1_EX_SDIV: in vl_logic;
iPREVIOUS_1_EX_UDIV: in vl_logic;
iPREVIOUS_1_EX_LDST: in vl_logic;
iPREVIOUS_1_EX_BRANCH: in vl_logic;
iPREVIOUS_PC : in vl_logic_vector(31 downto 0);
oPREVIOUS_LOCK : out vl_logic;
oNEXT_0_VALID : out vl_logic;
oNEXT_0_SOURCE0_ACTIVE: out vl_logic;
oNEXT_0_SOURCE1_ACTIVE: out vl_logic;
oNEXT_0_SOURCE0_SYSREG: out vl_logic;
oNEXT_0_SOURCE1_SYSREG: out vl_logic;
oNEXT_0_SOURCE0_SYSREG_RENAME: out vl_logic;
oNEXT_0_SOURCE1_SYSREG_RENAME: out vl_logic;
oNEXT_0_ADV_ACTIVE: out vl_logic;
oNEXT_0_DESTINATION_SYSREG: out vl_logic;
oNEXT_0_DEST_RENAME: out vl_logic;
oNEXT_0_WRITEBACK: out vl_logic;
oNEXT_0_FLAGS_WRITEBACK: out vl_logic;
oNEXT_0_CMD : out vl_logic_vector(4 downto 0);
oNEXT_0_CC_AFE : out vl_logic_vector(3 downto 0);
oNEXT_0_SOURCE0 : out vl_logic_vector(4 downto 0);
oNEXT_0_SOURCE1 : out vl_logic_vector(31 downto 0);
oNEXT_0_ADV_DATA: out vl_logic_vector(5 downto 0);
oNEXT_0_SOURCE0_FLAGS: out vl_logic;
oNEXT_0_SOURCE1_IMM: out vl_logic;
oNEXT_0_DESTINATION: out vl_logic_vector(4 downto 0);
oNEXT_0_EX_SYS_ADDER: out vl_logic;
oNEXT_0_EX_SYS_LDST: out vl_logic;
oNEXT_0_EX_LOGIC: out vl_logic;
oNEXT_0_EX_SHIFT: out vl_logic;
oNEXT_0_EX_ADDER: out vl_logic;
oNEXT_0_EX_MUL : out vl_logic;
oNEXT_0_EX_SDIV : out vl_logic;
oNEXT_0_EX_UDIV : out vl_logic;
oNEXT_0_EX_LDST : out vl_logic;
oNEXT_0_EX_BRANCH: out vl_logic;
oNEXT_1_VALID : out vl_logic;
oNEXT_1_SOURCE0_ACTIVE: out vl_logic;
oNEXT_1_SOURCE1_ACTIVE: out vl_logic;
oNEXT_1_SOURCE0_SYSREG: out vl_logic;
oNEXT_1_SOURCE1_SYSREG: out vl_logic;
oNEXT_1_SOURCE0_SYSREG_RENAME: out vl_logic;
oNEXT_1_SOURCE1_SYSREG_RENAME: out vl_logic;
oNEXT_1_ADV_ACTIVE: out vl_logic;
oNEXT_1_DESTINATION_SYSREG: out vl_logic;
oNEXT_1_DEST_RENAME: out vl_logic;
oNEXT_1_WRITEBACK: out vl_logic;
oNEXT_1_FLAGS_WRITEBACK: out vl_logic;
oNEXT_1_CMD : out vl_logic_vector(4 downto 0);
oNEXT_1_CC_AFE : out vl_logic_vector(3 downto 0);
oNEXT_1_SOURCE0 : out vl_logic_vector(4 downto 0);
oNEXT_1_SOURCE1 : out vl_logic_vector(31 downto 0);
oNEXT_1_ADV_DATA: out vl_logic_vector(5 downto 0);
oNEXT_1_SOURCE0_FLAGS: out vl_logic;
oNEXT_1_SOURCE1_IMM: out vl_logic;
oNEXT_1_DESTINATION: out vl_logic_vector(4 downto 0);
oNEXT_1_EX_SYS_ADDER: out vl_logic;
oNEXT_1_EX_SYS_LDST: out vl_logic;
oNEXT_1_EX_LOGIC: out vl_logic;
oNEXT_1_EX_SHIFT: out vl_logic;
oNEXT_1_EX_ADDER: out vl_logic;
oNEXT_1_EX_MUL : out vl_logic;
oNEXT_1_EX_SDIV : out vl_logic;
oNEXT_1_EX_UDIV : out vl_logic;
oNEXT_1_EX_LDST : out vl_logic;
oNEXT_1_EX_BRANCH: out vl_logic;
oNEXT_PC : out vl_logic_vector(31 downto 0);
iNEXT_LOCK : in vl_logic
);
end matching;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_gen_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_reg is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram_reg is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr : signal is "registers";
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
-- synchronous 2-port ram, common clock, flip-flops
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p_reg is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p_reg is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd : signal is "registers";
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_4p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_4p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, ra3, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if (re3 = '1')
-- pragma translate_off
and (conv_integer(raddr3) < numregs)
-- pragma translate_on
then ra3 <= raddr3; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
if g0addr > 0 and g0addr < numregs then
memarr(g0addr) <= (others => '0');
end if;
end if;
end process;
rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata3 <= din when (wr = '1') and (wa = ra3) and (wrfst = 1)
else memarr(conv_integer(ra3));
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY kbBuffer IS
PORT(
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END kbBuffer;
ARCHITECTURE behavioral OF kbBuffer IS
SIGNAL DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK, CLR)
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
IF(LOAD = '1' and DATA = x"00") THEN
DATA <= I;
ELSIF(CLR = '1') THEN
O <= "00000000" & DATA;
DATA <= (others => '0');
else
O <= (others => 'Z');
END IF;
END IF;
END PROCESS;
END behavioral; |
-- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v14.1%
-- GENERATION: XML
-- ddr3controller.vhd
-- Generated using ACDS version 14.1 186 at 2015.02.11.15:25:43
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr3controller is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_reset_n : out std_logic; -- .mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- .readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(15 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rzqin : in std_logic := '0'; -- oct.rzqin
pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
pll_write_clk : out std_logic; -- .pll_write_clk
pll_locked : out std_logic; -- .pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- .pll_avl_clk
pll_config_clk : out std_logic; -- .pll_config_clk
pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk
afi_phy_clk : out std_logic; -- .afi_phy_clk
pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk
);
end entity ddr3controller;
architecture rtl of ddr3controller is
component ddr3controller_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(14 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_locked : out std_logic; -- pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component ddr3controller_0002;
begin
ddr3controller_inst : component ddr3controller_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_reset_n => mem_reset_n, -- .mem_reset_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
avl_ready => avl_ready, -- avl.waitrequest_n
avl_burstbegin => avl_burstbegin, -- .beginbursttransfer
avl_addr => avl_addr, -- .address
avl_rdata_valid => avl_rdata_valid, -- .readdatavalid
avl_rdata => avl_rdata, -- .readdata
avl_wdata => avl_wdata, -- .writedata
avl_be => avl_be, -- .byteenable
avl_read_req => avl_read_req, -- .read
avl_write_req => avl_write_req, -- .write
avl_size => avl_size, -- .burstcount
local_init_done => local_init_done, -- status.local_init_done
local_cal_success => local_cal_success, -- .local_cal_success
local_cal_fail => local_cal_fail, -- .local_cal_fail
oct_rzqin => oct_rzqin, -- oct.rzqin
pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk
pll_write_clk => pll_write_clk, -- .pll_write_clk
pll_locked => pll_locked, -- .pll_locked
pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk
pll_avl_clk => pll_avl_clk, -- .pll_avl_clk
pll_config_clk => pll_config_clk, -- .pll_config_clk
pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk
afi_phy_clk => afi_phy_clk, -- .afi_phy_clk
pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk
);
end architecture rtl; -- of ddr3controller
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_ddr3_emif" version="14.1" >
-- Retrieval info: <generic name="MEM_VENDOR" value="JEDEC" />
-- Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" />
-- Retrieval info: <generic name="RDIMM_CONFIG" value="0000000000000000" />
-- Retrieval info: <generic name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="15" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="32" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="DUPLICATE_AC" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="AP_MODE_EN" value="0" />
-- Retrieval info: <generic name="AP_MODE" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="OTF" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_ASR" value="Manual" />
-- Retrieval info: <generic name="MEM_SRT" value="Normal" />
-- Retrieval info: <generic name="MEM_PD" value="DLL off" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="RZQ/7" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_RTT_NOM" value="RZQ/6" />
-- Retrieval info: <generic name="MEM_RTT_WR" value="RZQ/4" />
-- Retrieval info: <generic name="MEM_WTCL" value="5" />
-- Retrieval info: <generic name="MEM_ATCL" value="Disabled" />
-- Retrieval info: <generic name="MEM_TCL" value="6" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="200" />
-- Retrieval info: <generic name="TIMING_TIH" value="275" />
-- Retrieval info: <generic name="TIMING_TDS" value="75" />
-- Retrieval info: <generic name="TIMING_TDH" value="150" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="200" />
-- Retrieval info: <generic name="TIMING_TQH" value="0.38" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="400" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-- Retrieval info: <generic name="TIMING_TQSH" value="0.38" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="500" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="4" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="37.5" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="300.0" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="4" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="50.0" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="13.2" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="13.2" />
-- Retrieval info: <generic name="RATE" value="Half" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="300.0" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="6" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="4" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="true" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="16" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="32" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="50.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-- Retrieval info: <generic name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-- Retrieval info: <generic name="TREFI" value="35100" />
-- Retrieval info: <generic name="REFRESH_INTERVAL" value="15000" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL_TEST" value="false" />
-- Retrieval info: <generic name="TRFC" value="350" />
-- Retrieval info: <generic name="ENABLE_NON_DES_CAL" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="false" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_VOLTAGE" value="1.5V DDR3" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Full" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.03" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.03" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: <generic name="AUTO_DEVICE_SPEEDGRADE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : ddr3controller.vho
-- RELATED_FILES: ddr3controller.vhd, ddr3controller_0002.v, ddr3controller_pll0.sv, ddr3controller_p0_clock_pair_generator.v, ddr3controller_p0_read_valid_selector.v, ddr3controller_p0_addr_cmd_datapath.v, ddr3controller_p0_reset.v, ddr3controller_p0_acv_ldc.v, ddr3controller_p0_memphy.sv, ddr3controller_p0_reset_sync.v, ddr3controller_p0_new_io_pads.v, ddr3controller_p0_fr_cycle_shifter.v, ddr3controller_p0_fr_cycle_extender.v, ddr3controller_p0_read_datapath.sv, ddr3controller_p0_write_datapath.v, ddr3controller_p0_core_shadow_registers.sv, ddr3controller_p0_simple_ddio_out.sv, ddr3controller_p0_phy_csr.sv, ddr3controller_p0_iss_probe.v, ddr3controller_p0_addr_cmd_pads.v, ddr3controller_p0_flop_mem.v, ddr3controller_p0.sv, ddr3controller_p0_altdqdqs.v, altdq_dqs2_acv_cyclonev.sv, afi_mux_ddr3_ddrx.v, ddr3controller_s0.v, ddr3controller_s0_mm_interconnect_0_rsp_demux_003.sv, ddr3controller_s0_mm_interconnect_0_cmd_demux_001.sv, sequencer_phy_mgr.sv, ddr3controller_s0_mm_interconnect_0_router_001.sv, rw_manager_ram.v, rw_manager_inst_ROM_no_ifdef_params.v, ddr3controller_s0_mm_interconnect_0_rsp_mux_001.sv, rw_manager_inst_ROM_reg.v, ddr3controller_s0_mm_interconnect_0_router_005.sv, sequencer_scc_reg_file.v, altera_avalon_sc_fifo.v, rw_manager_bitcheck.v, rw_manager_lfsr36.v, sequencer_scc_sv_phase_decode.v, rw_manager_di_buffer_wrap.v, rw_manager_ac_ROM_reg.v, rw_manager_jumplogic.v, sequencer_reg_file.sv, rw_manager_ddr3.v, ddr3controller_s0_mm_interconnect_0.v, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, rw_manager_core.sv, rw_manager_di_buffer.v, rw_manager_dm_decoder.v, rw_manager_write_decoder.v, altera_mem_if_sequencer_mem_no_ifdef_params.sv, rw_manager_data_broadcast.v, sequencer_data_mgr.sv, altera_merlin_slave_translator.sv, ddr3controller_s0_mm_interconnect_0_rsp_mux.sv, ddr3controller_s0_mm_interconnect_0_cmd_mux_003.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, sequencer_scc_siii_phase_decode.v, ddr3controller_s0_irq_mapper.sv, rw_manager_pattern_fifo.v, ddr3controller_s0_mm_interconnect_0_router.sv, ddr3controller_s0_mm_interconnect_0_cmd_mux.sv, rw_manager_lfsr12.v, rw_manager_lfsr72.v, rw_manager_ram_csr.v, sequencer_scc_acv_wrapper.sv, sequencer_scc_acv_phase_decode.v, sequencer_scc_siii_wrapper.sv, altera_merlin_master_translator.sv, rw_manager_read_datapath.v, sequencer_scc_sv_wrapper.sv, altera_mem_if_sequencer_rst.sv, ddr3controller_s0_mm_interconnect_0_cmd_demux.sv, rw_manager_generic.sv, ddr3controller_s0_mm_interconnect_0_router_002.sv, altera_merlin_slave_agent.sv, altera_merlin_master_agent.sv, rw_manager_datamux.v, rw_manager_ac_ROM_no_ifdef_params.v, sequencer_scc_mgr.sv, rw_manager_data_decoder.v, altera_merlin_arbitrator.sv, altera_merlin_burst_uncompressor.sv, ddr3controller_c0.v, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_ddr3_controller_core.sv, alt_mem_ddrx_mm_st_converter.v
|
-------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the top level file for the iic Bus
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613282
-- ~~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_IIC_REGS -- Number of IIC Registers
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IIC Signals
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic is
generic (
-- System Generics
C_NUM_IIC_REGS : integer := 10;
--IIC Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_SCL_INERTIAL_DELAY : integer := 0;
C_SDA_INERTIAL_DELAY : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_EXIST : boolean := TRUE;
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7";
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IIC Bus Signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to C_GPO_WIDTH-1)
);
end entity iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Calls the function from the iic_pkg.vhd
constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
signal Msms_rst : std_logic;
signal Msms_set : std_logic;
signal Rsta_rst : std_logic;
signal Dtc : std_logic;
signal Rdy_new_xmt : std_logic;
signal New_rcv_dta : std_logic;
signal Ro_prev : std_logic;
signal Dtre : std_logic;
signal Bb : std_logic;
signal Aas : std_logic;
signal Al : std_logic;
signal Srw : std_logic;
signal Txer : std_logic;
signal Tx_under_prev : std_logic;
signal Abgc : std_logic;
signal Data_i2c : std_logic_vector(0 to 7);
signal Adr : std_logic_vector(0 to 7);
signal Ten_adr : std_logic_vector(5 to 7);
signal Cr : std_logic_vector(0 to 7);
signal Drr : std_logic_vector(0 to 7);
signal Dtr : std_logic_vector(0 to 7);
signal Tx_fifo_data : std_logic_vector(0 to 7);
signal Tx_data_exists : std_logic;
signal Tx_fifo_wr : std_logic;
signal Tx_fifo_wr_i : std_logic;
signal Tx_fifo_wr_d : std_logic;
signal Tx_fifo_rd : std_logic;
signal Tx_fifo_rd_i : std_logic;
signal Tx_fifo_rd_d : std_logic;
signal Tx_fifo_rst : std_logic;
signal Tx_fifo_full : std_logic;
signal Tx_addr : std_logic_vector(0 to TX_FIFO_BITS - 1);
signal Rc_fifo_data : std_logic_vector(0 to 7);
signal Rc_fifo_wr : std_logic;
signal Rc_fifo_wr_i : std_logic;
signal Rc_fifo_wr_d : std_logic;
signal Rc_fifo_rd : std_logic;
signal Rc_fifo_rd_i : std_logic;
signal Rc_fifo_rd_d : std_logic;
signal Rc_fifo_full : std_logic;
signal Rc_Data_Exists : std_logic;
signal Rc_addr : std_logic_vector(0 to RC_FIFO_BITS -1);
signal Bus2IIC_Clk : std_logic;
signal Bus2IIC_Reset : std_logic;
signal IIC2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1) :=
(others => '0');
signal IIC2Bus_IntrEvent : std_logic_vector(0 to 7) := (others => '0');
signal Bus2IIC_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal Bus2IIC_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal Bus2IIC_RNW : std_logic;
signal Bus2IIC_RdCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
signal Bus2IIC_WrCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
-- signals for dynamic start/stop
signal ctrlFifoDin : std_logic_vector(0 to 1);
signal dynamic_MSMS : std_logic_vector(0 to 1);
signal dynRstaSet : std_logic;
signal dynMsmsSet : std_logic;
signal txak : std_logic;
signal earlyAckDataState : std_logic;
signal ackDataState : std_logic;
signal earlyAckHdr : std_logic;
signal cr_txModeSelect_set : std_logic;
signal cr_txModeSelect_clr : std_logic;
signal txFifoRd : std_logic;
signal Msms_rst_r : std_logic;
signal ctrl_fifo_wr_i : std_logic;
-- Cleaned up inputs
signal scl_clean : std_logic;
signal sda_clean : std_logic;
-- Timing Parameters
signal Timing_param_tsusta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsusto : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thdsta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsudat : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tbuf : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thigh : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tlow : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thddat : std_logic_vector(C_SIZE-1 downto 0);
----------Mathew
-- signal transfer_done : std_logic;
signal reg_empty : std_logic;
----------Mathew
begin
----------------------------------------------------------------------------
-- axi_ipif_ssp1 instantiation
----------------------------------------------------------------------------
X_AXI_IPIF_SSP1 : entity axi_iic_v2_0.axi_ipif_ssp1
generic map (
C_NUM_IIC_REGS => C_NUM_IIC_REGS,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
-- Width of AXI Data Bus (in bits) Must be 32
C_FAMILY => C_FAMILY)
port map (
-- System signals ----------------------------------------------------
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent, -- IIC Interrupt events
IIC2INTC_Irpt => IIC2INTC_Irpt,
-- AXI Interface signals --------------
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals used by the IIC registers. ----
Bus2IIC_Clk => Bus2IIC_Clk,
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data,
Bus2IIC_RNW => Bus2IIC_RNW,
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data
);
----------------------------------------------------------------------------
-- reg_interface instantiation
----------------------------------------------------------------------------
REG_INTERFACE_I : entity axi_iic_v2_0.reg_interface
generic map (
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
C_TX_FIFO_EXIST => C_TX_FIFO_EXIST ,
C_TX_FIFO_BITS => 4 ,
C_RC_FIFO_EXIST => C_RC_FIFO_EXIST ,
C_RC_FIFO_BITS => 4 ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR ,
C_GPO_WIDTH => C_GPO_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SIZE => C_SIZE ,
C_NUM_IIC_REGS => C_NUM_IIC_REGS ,
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map (
Clk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data(0 to C_S_AXI_DATA_WIDTH - 1),
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data(0 to C_S_AXI_DATA_WIDTH - 1),
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent,
Gpo => Gpo(0 to C_GPO_WIDTH-1),
Cr => Cr,
Dtr => Dtr,
Drr => Drr,
Adr => Adr,
Ten_adr => Ten_adr,
Msms_set => Msms_set,
Msms_rst => Msms_rst,
DynMsmsSet => dynMsmsSet,
DynRstaSet => dynRstaSet,
Cr_txModeSelect_set => cr_txModeSelect_set,
Cr_txModeSelect_clr => cr_txModeSelect_clr,
Rsta_rst => Rsta_rst,
Rdy_new_xmt => Rdy_new_xmt,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Aas => Aas,
Bb => Bb,
Srw => Srw,
Al => Al,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Tx_fifo_data => Tx_fifo_data(0 to 7),
Tx_data_exists => Tx_data_exists,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_full => Tx_fifo_full,
Tx_fifo_rst => Tx_fifo_rst,
Tx_addr => Tx_addr(0 to TX_FIFO_BITS - 1),
Rc_fifo_data => Rc_fifo_data(0 to 7),
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_full => Rc_fifo_full,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr => Rc_addr(0 to RC_FIFO_BITS - 1),
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- The V5 inputs are so fast that they typically create glitches longer then
-- the clock period due to the extremely slow rise/fall times on SDA/SCL
-- signals. The inertial delay filter removes these.
----------------------------------------------------------------------------
FILTER_I: entity axi_iic_v2_0.filter
generic map (
SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY -- [range 0 to 255]
)
port map
(
Sysclk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Scl_noisy => Scl_I,
Scl_clean => scl_clean,
Sda_noisy => Sda_I,
Sda_clean => sda_clean
);
----------------------------------------------------------------------------
-- iic_control instantiation
----------------------------------------------------------------------------
IIC_CONTROL_I : entity axi_iic_v2_0.iic_control
generic map
(
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SIZE => C_SIZE ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR,
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST
)
port map
(
Sys_clk => Bus2IIC_Clk,
Reset => Cr(7),
Sda_I => sda_clean,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => scl_clean,
Scl_O => Scl_O,
Scl_T => Scl_T,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Txak => txak,
Msms => Cr(5),
Msms_set => Msms_set,
Msms_rst => Msms_rst_r,
Rsta => Cr(2),
Rsta_rst => Rsta_rst,
Tx => Cr(4),
Gc_en => Cr(1),
Dtr => Dtr,
Adr => Adr,
Ten_adr => Ten_adr,
Bb => Bb,
Dtc => Dtc,
Aas => Aas,
Al => Al,
Srw => Srw,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Rdy_new_xmt => Rdy_new_xmt,
EarlyAckHdr => earlyAckHdr,
EarlyAckDataState => earlyAckDataState,
AckDataState => ackDataState,
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- Transmitter FIFO instantiation
----------------------------------------------------------------------------
WRITE_FIFO_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => Tx_fifo_wr_i,
Data_In => Bus2IIC_Data(24 to 31),
FIFO_Read => txFifoRd,
Data_Out => Tx_fifo_data(0 to 7),
FIFO_Full => Tx_fifo_full,
Data_Exists => Tx_data_exists,
Addr => Tx_addr(0 to TX_FIFO_BITS - 1)
);
-------Mathew
-- transfer_done <= '1' when Tx_data_exists = '0' and reg_empty ='1' else '0';
-------Mathew
----------------------------------------------------------------------------
-- Receiver FIFO instantiation
----------------------------------------------------------------------------
READ_FIFO_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => RC_FIFO_BITS
)
port map (
Clk => Bus2IIC_Clk,
Reset => Bus2IIC_Reset,
FIFO_Write => Rc_fifo_wr_i,
Data_In => Data_i2c(0 to 7),
FIFO_Read => Rc_fifo_rd_i,
Data_Out => Rc_fifo_data(0 to 7),
FIFO_Full => Rc_fifo_full,
Data_Exists => Rc_Data_Exists,
Addr => Rc_addr(0 to RC_FIFO_BITS - 1)
);
----------------------------------------------------------------------------
-- PROCESS: TX_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
TX_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Tx_fifo_wr_d <= '0';
Tx_fifo_rd_d <= '0';
else
Tx_fifo_wr_d <= Tx_fifo_wr;
Tx_fifo_rd_d <= Tx_fifo_rd;
end if;
end if;
end process TX_FIFO_WR_GEN;
----------------------------------------------------------------------------
-- PROCESS: RC_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
RC_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Rc_fifo_wr_d <= '0';
Rc_fifo_rd_d <= '0';
else
Rc_fifo_wr_d <= Rc_fifo_wr;
Rc_fifo_rd_d <= Rc_fifo_rd;
end if;
end if;
end process RC_FIFO_WR_GEN;
Tx_fifo_wr_i <= Tx_fifo_wr and (not Tx_fifo_wr_d);
Rc_fifo_wr_i <= Rc_fifo_wr and (not Rc_fifo_wr_d);
Tx_fifo_rd_i <= Tx_fifo_rd and (not Tx_fifo_rd_d);
Rc_fifo_rd_i <= Rc_fifo_rd and (not Rc_fifo_rd_d);
----------------------------------------------------------------------------
-- Dynamic master interface
-- Dynamic master start/stop and control logic
----------------------------------------------------------------------------
DYN_MASTER_I : entity axi_iic_v2_0.dynamic_master
port map (
Clk => Bus2IIC_Clk ,
Rst => Tx_fifo_rst ,
dynamic_MSMS => dynamic_MSMS ,
Cr => Cr ,
Tx_fifo_rd_i => Tx_fifo_rd_i ,
Tx_data_exists => Tx_data_exists ,
ackDataState => ackDataState ,
Tx_fifo_data => Tx_fifo_data ,
earlyAckHdr => earlyAckHdr ,
earlyAckDataState => earlyAckDataState ,
Bb => Bb ,
Msms_rst_r => Msms_rst_r ,
dynMsmsSet => dynMsmsSet ,
dynRstaSet => dynRstaSet ,
Msms_rst => Msms_rst ,
txFifoRd => txFifoRd ,
txak => txak ,
cr_txModeSelect_set => cr_txModeSelect_set,
cr_txModeSelect_clr => cr_txModeSelect_clr
);
-- virtual reset. Since srl fifo address is rst at the same time, only the
-- first entry in the srl fifo needs to have a value of '00' to appear
-- reset. Also, force data to 0 if a byte write is done to the txFifo.
ctrlFifoDin <= Bus2IIC_Data(22 to 23) when (Tx_fifo_rst = '0' and
Bus2IIC_Reset = '0') else
"00";
-- continuously write srl fifo while reset active
ctrl_fifo_wr_i <= Tx_fifo_rst or Bus2IIC_Reset or Tx_fifo_wr_i;
----------------------------------------------------------------------------
-- Control FIFO instantiation
-- fifo used to set/reset MSMS bit in control register to create automatic
-- START/STOP conditions
----------------------------------------------------------------------------
WRITE_FIFO_CTRL_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => 2,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => ctrl_fifo_wr_i,
Data_In => ctrlFifoDin,
FIFO_Read => txFifoRd,
Data_Out => dynamic_MSMS,
FIFO_Full => open,
Data_Exists => open,
Addr => open
);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the top level file for the iic Bus
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613282
-- ~~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_IIC_REGS -- Number of IIC Registers
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IIC Signals
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic is
generic (
-- System Generics
C_NUM_IIC_REGS : integer := 10;
--IIC Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_SCL_INERTIAL_DELAY : integer := 0;
C_SDA_INERTIAL_DELAY : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_EXIST : boolean := TRUE;
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7";
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IIC Bus Signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to C_GPO_WIDTH-1)
);
end entity iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Calls the function from the iic_pkg.vhd
constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
signal Msms_rst : std_logic;
signal Msms_set : std_logic;
signal Rsta_rst : std_logic;
signal Dtc : std_logic;
signal Rdy_new_xmt : std_logic;
signal New_rcv_dta : std_logic;
signal Ro_prev : std_logic;
signal Dtre : std_logic;
signal Bb : std_logic;
signal Aas : std_logic;
signal Al : std_logic;
signal Srw : std_logic;
signal Txer : std_logic;
signal Tx_under_prev : std_logic;
signal Abgc : std_logic;
signal Data_i2c : std_logic_vector(0 to 7);
signal Adr : std_logic_vector(0 to 7);
signal Ten_adr : std_logic_vector(5 to 7);
signal Cr : std_logic_vector(0 to 7);
signal Drr : std_logic_vector(0 to 7);
signal Dtr : std_logic_vector(0 to 7);
signal Tx_fifo_data : std_logic_vector(0 to 7);
signal Tx_data_exists : std_logic;
signal Tx_fifo_wr : std_logic;
signal Tx_fifo_wr_i : std_logic;
signal Tx_fifo_wr_d : std_logic;
signal Tx_fifo_rd : std_logic;
signal Tx_fifo_rd_i : std_logic;
signal Tx_fifo_rd_d : std_logic;
signal Tx_fifo_rst : std_logic;
signal Tx_fifo_full : std_logic;
signal Tx_addr : std_logic_vector(0 to TX_FIFO_BITS - 1);
signal Rc_fifo_data : std_logic_vector(0 to 7);
signal Rc_fifo_wr : std_logic;
signal Rc_fifo_wr_i : std_logic;
signal Rc_fifo_wr_d : std_logic;
signal Rc_fifo_rd : std_logic;
signal Rc_fifo_rd_i : std_logic;
signal Rc_fifo_rd_d : std_logic;
signal Rc_fifo_full : std_logic;
signal Rc_Data_Exists : std_logic;
signal Rc_addr : std_logic_vector(0 to RC_FIFO_BITS -1);
signal Bus2IIC_Clk : std_logic;
signal Bus2IIC_Reset : std_logic;
signal IIC2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1) :=
(others => '0');
signal IIC2Bus_IntrEvent : std_logic_vector(0 to 7) := (others => '0');
signal Bus2IIC_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal Bus2IIC_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal Bus2IIC_RNW : std_logic;
signal Bus2IIC_RdCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
signal Bus2IIC_WrCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
-- signals for dynamic start/stop
signal ctrlFifoDin : std_logic_vector(0 to 1);
signal dynamic_MSMS : std_logic_vector(0 to 1);
signal dynRstaSet : std_logic;
signal dynMsmsSet : std_logic;
signal txak : std_logic;
signal earlyAckDataState : std_logic;
signal ackDataState : std_logic;
signal earlyAckHdr : std_logic;
signal cr_txModeSelect_set : std_logic;
signal cr_txModeSelect_clr : std_logic;
signal txFifoRd : std_logic;
signal Msms_rst_r : std_logic;
signal ctrl_fifo_wr_i : std_logic;
-- Cleaned up inputs
signal scl_clean : std_logic;
signal sda_clean : std_logic;
-- Timing Parameters
signal Timing_param_tsusta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsusto : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thdsta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsudat : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tbuf : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thigh : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tlow : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thddat : std_logic_vector(C_SIZE-1 downto 0);
----------Mathew
-- signal transfer_done : std_logic;
signal reg_empty : std_logic;
----------Mathew
begin
----------------------------------------------------------------------------
-- axi_ipif_ssp1 instantiation
----------------------------------------------------------------------------
X_AXI_IPIF_SSP1 : entity axi_iic_v2_0.axi_ipif_ssp1
generic map (
C_NUM_IIC_REGS => C_NUM_IIC_REGS,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
-- Width of AXI Data Bus (in bits) Must be 32
C_FAMILY => C_FAMILY)
port map (
-- System signals ----------------------------------------------------
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent, -- IIC Interrupt events
IIC2INTC_Irpt => IIC2INTC_Irpt,
-- AXI Interface signals --------------
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals used by the IIC registers. ----
Bus2IIC_Clk => Bus2IIC_Clk,
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data,
Bus2IIC_RNW => Bus2IIC_RNW,
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data
);
----------------------------------------------------------------------------
-- reg_interface instantiation
----------------------------------------------------------------------------
REG_INTERFACE_I : entity axi_iic_v2_0.reg_interface
generic map (
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
C_TX_FIFO_EXIST => C_TX_FIFO_EXIST ,
C_TX_FIFO_BITS => 4 ,
C_RC_FIFO_EXIST => C_RC_FIFO_EXIST ,
C_RC_FIFO_BITS => 4 ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR ,
C_GPO_WIDTH => C_GPO_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SIZE => C_SIZE ,
C_NUM_IIC_REGS => C_NUM_IIC_REGS ,
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map (
Clk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data(0 to C_S_AXI_DATA_WIDTH - 1),
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data(0 to C_S_AXI_DATA_WIDTH - 1),
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent,
Gpo => Gpo(0 to C_GPO_WIDTH-1),
Cr => Cr,
Dtr => Dtr,
Drr => Drr,
Adr => Adr,
Ten_adr => Ten_adr,
Msms_set => Msms_set,
Msms_rst => Msms_rst,
DynMsmsSet => dynMsmsSet,
DynRstaSet => dynRstaSet,
Cr_txModeSelect_set => cr_txModeSelect_set,
Cr_txModeSelect_clr => cr_txModeSelect_clr,
Rsta_rst => Rsta_rst,
Rdy_new_xmt => Rdy_new_xmt,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Aas => Aas,
Bb => Bb,
Srw => Srw,
Al => Al,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Tx_fifo_data => Tx_fifo_data(0 to 7),
Tx_data_exists => Tx_data_exists,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_full => Tx_fifo_full,
Tx_fifo_rst => Tx_fifo_rst,
Tx_addr => Tx_addr(0 to TX_FIFO_BITS - 1),
Rc_fifo_data => Rc_fifo_data(0 to 7),
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_full => Rc_fifo_full,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr => Rc_addr(0 to RC_FIFO_BITS - 1),
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- The V5 inputs are so fast that they typically create glitches longer then
-- the clock period due to the extremely slow rise/fall times on SDA/SCL
-- signals. The inertial delay filter removes these.
----------------------------------------------------------------------------
FILTER_I: entity axi_iic_v2_0.filter
generic map (
SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY -- [range 0 to 255]
)
port map
(
Sysclk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Scl_noisy => Scl_I,
Scl_clean => scl_clean,
Sda_noisy => Sda_I,
Sda_clean => sda_clean
);
----------------------------------------------------------------------------
-- iic_control instantiation
----------------------------------------------------------------------------
IIC_CONTROL_I : entity axi_iic_v2_0.iic_control
generic map
(
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SIZE => C_SIZE ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR,
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST
)
port map
(
Sys_clk => Bus2IIC_Clk,
Reset => Cr(7),
Sda_I => sda_clean,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => scl_clean,
Scl_O => Scl_O,
Scl_T => Scl_T,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Txak => txak,
Msms => Cr(5),
Msms_set => Msms_set,
Msms_rst => Msms_rst_r,
Rsta => Cr(2),
Rsta_rst => Rsta_rst,
Tx => Cr(4),
Gc_en => Cr(1),
Dtr => Dtr,
Adr => Adr,
Ten_adr => Ten_adr,
Bb => Bb,
Dtc => Dtc,
Aas => Aas,
Al => Al,
Srw => Srw,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Rdy_new_xmt => Rdy_new_xmt,
EarlyAckHdr => earlyAckHdr,
EarlyAckDataState => earlyAckDataState,
AckDataState => ackDataState,
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- Transmitter FIFO instantiation
----------------------------------------------------------------------------
WRITE_FIFO_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => Tx_fifo_wr_i,
Data_In => Bus2IIC_Data(24 to 31),
FIFO_Read => txFifoRd,
Data_Out => Tx_fifo_data(0 to 7),
FIFO_Full => Tx_fifo_full,
Data_Exists => Tx_data_exists,
Addr => Tx_addr(0 to TX_FIFO_BITS - 1)
);
-------Mathew
-- transfer_done <= '1' when Tx_data_exists = '0' and reg_empty ='1' else '0';
-------Mathew
----------------------------------------------------------------------------
-- Receiver FIFO instantiation
----------------------------------------------------------------------------
READ_FIFO_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => RC_FIFO_BITS
)
port map (
Clk => Bus2IIC_Clk,
Reset => Bus2IIC_Reset,
FIFO_Write => Rc_fifo_wr_i,
Data_In => Data_i2c(0 to 7),
FIFO_Read => Rc_fifo_rd_i,
Data_Out => Rc_fifo_data(0 to 7),
FIFO_Full => Rc_fifo_full,
Data_Exists => Rc_Data_Exists,
Addr => Rc_addr(0 to RC_FIFO_BITS - 1)
);
----------------------------------------------------------------------------
-- PROCESS: TX_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
TX_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Tx_fifo_wr_d <= '0';
Tx_fifo_rd_d <= '0';
else
Tx_fifo_wr_d <= Tx_fifo_wr;
Tx_fifo_rd_d <= Tx_fifo_rd;
end if;
end if;
end process TX_FIFO_WR_GEN;
----------------------------------------------------------------------------
-- PROCESS: RC_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
RC_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Rc_fifo_wr_d <= '0';
Rc_fifo_rd_d <= '0';
else
Rc_fifo_wr_d <= Rc_fifo_wr;
Rc_fifo_rd_d <= Rc_fifo_rd;
end if;
end if;
end process RC_FIFO_WR_GEN;
Tx_fifo_wr_i <= Tx_fifo_wr and (not Tx_fifo_wr_d);
Rc_fifo_wr_i <= Rc_fifo_wr and (not Rc_fifo_wr_d);
Tx_fifo_rd_i <= Tx_fifo_rd and (not Tx_fifo_rd_d);
Rc_fifo_rd_i <= Rc_fifo_rd and (not Rc_fifo_rd_d);
----------------------------------------------------------------------------
-- Dynamic master interface
-- Dynamic master start/stop and control logic
----------------------------------------------------------------------------
DYN_MASTER_I : entity axi_iic_v2_0.dynamic_master
port map (
Clk => Bus2IIC_Clk ,
Rst => Tx_fifo_rst ,
dynamic_MSMS => dynamic_MSMS ,
Cr => Cr ,
Tx_fifo_rd_i => Tx_fifo_rd_i ,
Tx_data_exists => Tx_data_exists ,
ackDataState => ackDataState ,
Tx_fifo_data => Tx_fifo_data ,
earlyAckHdr => earlyAckHdr ,
earlyAckDataState => earlyAckDataState ,
Bb => Bb ,
Msms_rst_r => Msms_rst_r ,
dynMsmsSet => dynMsmsSet ,
dynRstaSet => dynRstaSet ,
Msms_rst => Msms_rst ,
txFifoRd => txFifoRd ,
txak => txak ,
cr_txModeSelect_set => cr_txModeSelect_set,
cr_txModeSelect_clr => cr_txModeSelect_clr
);
-- virtual reset. Since srl fifo address is rst at the same time, only the
-- first entry in the srl fifo needs to have a value of '00' to appear
-- reset. Also, force data to 0 if a byte write is done to the txFifo.
ctrlFifoDin <= Bus2IIC_Data(22 to 23) when (Tx_fifo_rst = '0' and
Bus2IIC_Reset = '0') else
"00";
-- continuously write srl fifo while reset active
ctrl_fifo_wr_i <= Tx_fifo_rst or Bus2IIC_Reset or Tx_fifo_wr_i;
----------------------------------------------------------------------------
-- Control FIFO instantiation
-- fifo used to set/reset MSMS bit in control register to create automatic
-- START/STOP conditions
----------------------------------------------------------------------------
WRITE_FIFO_CTRL_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => 2,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => ctrl_fifo_wr_i,
Data_In => ctrlFifoDin,
FIFO_Read => txFifoRd,
Data_Out => dynamic_MSMS,
FIFO_Full => open,
Data_Exists => open,
Addr => open
);
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity matchfilter is
port(
clk : in vl_logic;
reset_n : in vl_logic;
ast_sink_data : in vl_logic_vector(14 downto 0);
ast_sink_valid : in vl_logic;
ast_source_ready: in vl_logic;
ast_sink_error : in vl_logic_vector(1 downto 0);
ast_source_data : out vl_logic_vector(29 downto 0);
ast_sink_ready : out vl_logic;
ast_source_valid: out vl_logic;
ast_source_error: out vl_logic_vector(1 downto 0)
);
end matchfilter;
|
library verilog;
use verilog.vl_types.all;
entity matchfilter is
port(
clk : in vl_logic;
reset_n : in vl_logic;
ast_sink_data : in vl_logic_vector(14 downto 0);
ast_sink_valid : in vl_logic;
ast_source_ready: in vl_logic;
ast_sink_error : in vl_logic_vector(1 downto 0);
ast_source_data : out vl_logic_vector(29 downto 0);
ast_sink_ready : out vl_logic;
ast_source_valid: out vl_logic;
ast_source_error: out vl_logic_vector(1 downto 0)
);
end matchfilter;
|
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE work.GlobalDefines.ALL;
entity <name> is
port(
);
end <name>;
architecture bhv of <name> is
component <bla> is
port(
);
end component;
begin
end bhv;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myXor2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end myXor2;
architecture behavorial of myXor2 is
-- declare components
component myNand2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myOr2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myAnd2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signals
signal a_or_b_out: std_logic;
signal a_nand_b_out: std_logic;
begin
-- initialize components and port map
myOr2_1: myOr2 port map(a => a, b => b, s => a_or_b_out);
myNand2_1: myNand2 port map(a => a, b => b, s => a_nand_b_out);
myAnd2_1: myAnd2 port map(a => a_or_b_out, b => a_nand_b_out, s => s);
end behavorial;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans;
architecture a_aff_trans of aff_trans is
begin
-- Tranformation Process
b_out(0) <= not (a(0)) xor a(4) xor a(5) xor a(6) xor a(7);
b_out(1) <= not (a(5)) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(2) <= a(2) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(3) <= a(7) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(4) <= a(4) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(5) <= not (a(1)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(6) <= not (a(6)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(7) <= a(3) xor a(4) xor a(5) xor a(6) xor a(7);
end a_aff_trans;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans;
architecture a_aff_trans of aff_trans is
begin
-- Tranformation Process
b_out(0) <= not (a(0)) xor a(4) xor a(5) xor a(6) xor a(7);
b_out(1) <= not (a(5)) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(2) <= a(2) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(3) <= a(7) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(4) <= a(4) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(5) <= not (a(1)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(6) <= not (a(6)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(7) <= a(3) xor a(4) xor a(5) xor a(6) xor a(7);
end a_aff_trans;
|
-- This is the top level of the ethernet block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ethernet_package.all;
entity ethernet_udp is
port (
--- External ports
CLK125 : in STD_LOGIC;
reset_n : in std_logic;
PHY_RESET_L : out STD_LOGIC;
PHY_MDC : out STD_LOGIC;
PHY_MDIO : inout STD_LOGIC;
TX : out rgmii_t;
RX : in rgmii_t;
GE_TXCLK : out std_logic;
--- Clock from PLL to synchronize received data
clk250_marvell : in STD_LOGIC;
clk250_fpga : in STD_LOGIC;
--- parameters from slave
mac_addr_hal_msb : in std_logic_vector(23 downto 0);
mac_addr_hal_lsb : in std_logic_vector(23 downto 0);
mac_addr_dest_msb : in std_logic_vector(23 downto 0);
mac_addr_dest_lsb : in std_logic_vector(23 downto 0);
ip_hal : in std_logic_vector(31 downto 0);
ip_dest : in std_logic_vector(31 downto 0);
port_dest : in std_logic_vector(15 downto 0);
--- Receiving flows to send on link
hal_ready : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_size_i : in std_logic_vector(15 downto 0);
ready_i : in std_logic;
read_data_o : out std_logic;
--- Transmitting flows received by link
data_o : out std_logic_vector(7 downto 0);
write_o : out std_logic
);
end ethernet_udp;
architecture RTL of ethernet_udp is
signal eth_tx_stream : std_logic_vector(8 downto 0);
signal TX_s : rgmii_t;
signal TX_udp : gmii_t;
signal RX_gmii : gmii_t;
signal RX_sync : gmii_t;
signal RX_gmii_dl : gmii_t;
signal RX_filtered : gmii_t;
signal port_detected : std_logic_vector(15 downto 0);
signal TX_encapsulated : gmii_t;
signal TEST_rx_sync : std_logic;
signal data_valid_i : std_logic;
signal count : std_logic_vector(15 downto 0);
signal read_data_s,hal_ready_s : std_logic;
signal data_valid_dl1,data_valid_dl2 : std_logic;
signal read_data_dl : std_logic;
signal TX_s_dl : std_logic;
begin
data_o <= RX_filtered.data;
write_o <= RX_filtered.dv;
eth_tx_stream <= TX_encapsulated.dv & TX_encapsulated.data;
TX <= TX_s;
read_data_o <= read_data_s;
hal_ready <= hal_ready_s;
GE_TXCLK <= CLK125;
----- Read data from com, read data when the flow_to_com is ready
process(CLK125,reset_n)
begin
if reset_n='0' then
read_data_s <= '0';
hal_ready_s <= '1';
elsif CLK125'event and CLK125='1' then
data_valid_dl1 <= read_data_s;
data_valid_dl2 <= data_valid_dl1;
TX_s_dl <= TX_s.dv;
--- Read data from com, read data when the flow_to_com is ready
if ready_i='1' and read_data_s='0' and hal_ready_s='1' then
read_data_s <= '1';
elsif ready_i='0' then
read_data_s <= '0';
end if;
--- Set hal_ready : high when it starts reading data and low when the packet has been fully sent
if read_data_s='1' and data_valid_dl1='0' then
hal_ready_s <= '0';
elsif TX_s.dv='0' and TX_s_dl='1' then
hal_ready_s <= '1';
end if;
end if;
end process;
data_valid_i <= read_data_s and data_valid_dl2;
--- RGMII to GMII and GMII to RGMII
interface_managemet_inst : entity work.interface_management
port map (
clk125 => clk125,
clk250_marvell => clk250_marvell,
clk250_fpga => clk250_fpga,
reset_n => reset_n,
RX_i => RX,
RX_o => RX_gmii,
TX_i => TX_udp,
TX_o => TX_s
);
----- Filter mac/ip address and detect destination port
filter_mac_ip_port : entity work.eth_udp_filter
port map (
RXCLK => clk125,
reset_n => reset_n,
RX_i => RX_gmii,
RX_o => RX_filtered,
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
ip_hal => ip_hal,
port_detected => port_detected
);
----- Adding ip/udp header and gps header to data to send
eth_tx_hdr_inst : entity work.eth_tx_header
Port map(
CLK125 => CLK125,
reset_n => reset_n,
data_i => data_i,
data_size_i => data_size_i,
TX_i.dv => data_valid_i,
TX_i.data => data_i,
TX_o => TX_encapsulated,
--- Parameters from slave
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
mac_addr_dest_msb => mac_addr_dest_msb,
mac_addr_dest_lsb => mac_addr_dest_lsb,
ip_hal => ip_hal,
ip_dest => ip_dest,
port_dest => port_dest
);
----- Data to send : padding if needed, adding CRC and preamble
GMStream_inst : entity work.eth_tx_encap(Behavioral)
port map(
GE_TXEN => TX_udp.dv,
GE_TXD => TX_udp.data,
CLK125 => CLK125,
reset_n => reset_n,
ETH_TX_STREAM => eth_tx_stream
);
----- Control the configuration of the marvell and the hardware reset
eth_ctrl : entity work.eth_mdio
port map(
CLK => CLK125,
RESET => reset_n,
E_RST_L => PHY_RESET_L,
E_MDC => PHY_MDC,
E_MDIO => PHY_MDIO
);
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myvga is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
hsync : out std_logic;
vsync : out std_logic;
gr : out std_logic_vector(2 downto 0);
re : out std_logic_vector(2 downto 0);
bl : out std_logic_vector(1 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
end myvga;
architecture EXAMPLE of myvga is
constant hpixels : unsigned(9 downto 0) := "1100100000"; -- 800
constant vlines : unsigned(9 downto 0) := "1000001101"; -- 525
constant hbp : unsigned(9 downto 0) := "0010010000"; -- 144 backp h
constant hfp: unsigned(9 downto 0) := "1100010000"; -- 784 frontp h
constant vbp : unsigned(9 downto 0) := "0000011111"; -- 31 backp v
constant vfp : unsigned(9 downto 0) := "0111111111"; -- 511 frontp v
signal clk_div_c, clk_div_n : unsigned(1 downto 0); -- mod 4
signal h_count_c, h_count_n, v_count_c, v_count_n : unsigned(9 downto 0);
signal vsenable : std_logic; -- enable for vertical count
signal vidon : std_logic;
begin
FSL_S_Read <= '0';
clk_proc: process(FSL_Clk) is
begin
if FSL_Clk'event and FSL_Clk = '1' then
if FSL_Rst = '1' then
clk_div_c <= (others => '0');
h_count_c <= (others => '0');
v_count_c <= (others => '0');
else
clk_div_c <= clk_div_n;
h_count_c <= h_count_n;
v_count_c <= v_count_n;
end if;
end if;
end process;
clk_div_proc: process(clk_div_c)
begin
clk_div_n <= clk_div_c + 1;
if clk_div_c = 3 then
clk_div_n <= (others => '0');
end if;
end process;
h_proc: process(clk_div_c, h_count_c)
begin
vsenable <= '0';
h_count_n <= h_count_c;
if (clk_div_c = 3) then
h_count_n <= h_count_c + 1;
if h_count_c = hpixels - 1 then
h_count_n <= (others => '0');
vsenable <= '1';
end if;
end if;
end process;
hsync <= '0' when h_count_c < 96 else '1';
v_proc: process(clk_div_c, vsenable, v_count_c)
begin
v_count_n <= v_count_c;
if (clk_div_c = 3 and vsenable = '1') then
v_count_n <= v_count_c + 1;
if v_count_c = vlines - 1 then
v_count_n <= (others => '0');
end if;
end if;
end process;
vsync <= '0' when v_count_c < 2 else '1';
vidon <= '1' when (((h_count_c < hfp) and (h_count_c >= hbp)) and ((v_count_c < vfp) and (v_count_c >= vbp))) else '0';
rgb_proc: process(vidon)
begin
gr <= (others => '0');
re <= (others => '0');
bl <= (others => '0');
if (vidon = '1') then
re <= "111";
end if;
end process;
--hsync <= '0' when (h_count_c >= (HD+HF)) and (h_count_c <= (HD+HF+HR-1)) else '1';
--vsync <= '0' when (v_count_c >= (VD+VF)) and (h_count_c <= (VD+VF+VR-1)) else '1';
end architecture EXAMPLE;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05500_good.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of latches: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_05500_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_05500_good;
architecture Behavioral of STD_05500_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
|
entity bug is
end entity;
architecture test of bug is
constant engnum : integer:=8;
subtype engrange is integer range 0 to engnum-1;
type bit_array is array(engrange) of bit;
type byte_array is array(engrange) of bit_vector(7 downto 0);
type mode_t is (RDBMG, C2ENC, C2DEC, C1DEC, WRBMG);
type mode_arr_t is array (natural range <>) of mode_t;
constant ECC_RD_DATA_VAL : bit := '1';
signal buf_ce : bit_vector(engrange);
signal bufmode : mode_arr_t(0 to 0);
signal index : natural := 0;
signal c2enc_ce, c2dec_ce, c1dec_ce : bit_vector(engrange);
signal task4_ce : bit := '1';
begin
ce: with bufmode(index) select buf_ce <=
(engrange => ECC_RD_DATA_VAL) WHEN RDBMG, -- OK
c2enc_ce when C2ENC,
c2dec_ce WHEN C2DEC,
c1dec_ce WHEN C1DEC,
(engrange => task4_ce) WHEN WRBMG, -- OK
(engrange => '0') WHEN others; -- OK
buf_ce <= (bit => '0'); -- Error
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_coder is
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
d : in std_logic;
x : out std_logic;
y : out std_logic
);
end conv_coder;
architecture rtl of conv_coder is
signal delay : std_logic_vector(0 to 5) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
delay <= (others => '0');
elsif clk_en = '1' then
delay <= d & delay(0 to 4);
-- X has G = 171o = 121d = 1111001
x <= d xor delay(0) xor delay(1) xor delay(2) xor delay(5);
-- Y has G = 133o = 91d = 1011011
y <= d xor delay(1) xor delay(2) xor delay(4) xor delay(5);
end if;
end process;
end rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic; -- Behrad: In FIFO, this is actually an internal signal "named as credit_in", which I guess should keep the previous value of credit_out.
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
begin
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
err_empty_full <= '0';
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
end if;
end process;
-- Checked!
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
err_empty_read_en <= '0';
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
err_full_write_en <= '0';
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
err_read_pointer_in_onehot <= '0';
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
err_write_pointer_in_onehot <= '0';
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
err_write_en_write_pointer <= '0';
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
end if;
end process;
process (write_en_out, write_pointer_in, write_pointer)
begin
err_not_write_en_write_pointer <= '0';
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
err_read_pointer_write_pointer_not_empty <= '0';
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
err_read_pointer_write_pointer_empty <= '0';
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
err_read_pointer_write_pointer_not_full <= '0';
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
err_read_pointer_write_pointer_full <= '0';
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
err_read_pointer_increment <= '0';
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
err_read_pointer_not_increment <= '0';
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_write_en <= '0';
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en <= '0';
if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en1 <= '0';
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en2 <= '0';
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
end if;
end process;
-- Checked! (Not sure yet if actually needed!)
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
err_read_en_mismatch <= '0';
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
err_read_en_mismatch1 <= '0';
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
end if;
end process;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Newly added checkers for FIFO with packet drop and fault classifier support --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Checkers for fake credit generation logic in FIFO
---------------------------------------------------------------------------------
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked!
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked! (Behrad: Is it OK to see fake credit counter like this ?? Because being negative, can also be understood as positive,
-- depending on how the data is evaluated (signed or unsigned), or may I am wrong.)
process (fake_credit, read_en_out, credit_out)
begin
err_fake_credit_read_en_credit_out <= '0';
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
end if;
end process;
-- Checked! (Behrad: Credit_out here in Checker is actually credit_in in FIFO. Well, FIFO generated credit_out.
-- But here, credit_in would mean the registered value of credit_out I guess. )
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Checkers related to the packet dropping FSM of FIFO
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Idle state
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, fault_out, valid_in, state_in)
begin
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
err_state_out_Idle_not_fault_out_not_fault_info_in <= '0';
if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then
err_state_out_Idle_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
err_state_out_Idle_fault_out_fake_credit <= '0';
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, fault_out, state_in)
begin
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
err_state_out_Idle_fault_out_fault_info_in <= '0';
if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then
err_state_out_Idle_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
end if;
end process;
process (state_out, write_fake_flit)
begin
err_state_out_Idle_not_write_fake_flit <= '0';
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
-- health_info only gets updated when the FSM is in "Body" state (flit type is Body)
process (state_out, health_info)
begin
err_state_out_Idle_not_health_info <= '0';
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, state_in)
begin
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, fake_credit)
begin
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Body_flit state
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, health_info)
begin
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, health_info)
begin
err_state_out_Body_flit_valid_in_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, state_in)
begin
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, fake_credit)
begin
err_state_out_Body_flit_not_fake_credit <= '0';
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- valid_in = '1' and fault_out = '0'
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
process (state_out, valid_in, state_in)
begin
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
end if;
end process;
process (state_out, write_fake_flit)
begin
err_state_out_Tail_flit_not_write_fake_flit <= '0';
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in)
begin
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in)
begin
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
end if;
end process;
process (fault_info, fault_info_out)
begin
err_fault_info_fault_info_out_equal <= '0';
if (fault_info /= fault_info_out) then
err_fault_info_fault_info_out_equal <= '1';
end if;
end process;
process (state_out, valid_in, state_in)
begin
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0';
if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_info_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_info_in /= '1') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fault_info_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001") and fault_info_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '1';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic; -- Behrad: In FIFO, this is actually an internal signal "named as credit_in", which I guess should keep the previous value of credit_out.
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
begin
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
err_empty_full <= '0';
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
end if;
end process;
-- Checked!
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
err_empty_read_en <= '0';
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
err_full_write_en <= '0';
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
err_read_pointer_in_onehot <= '0';
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
err_write_pointer_in_onehot <= '0';
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
err_write_en_write_pointer <= '0';
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
end if;
end process;
process (write_en_out, write_pointer_in, write_pointer)
begin
err_not_write_en_write_pointer <= '0';
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
err_read_pointer_write_pointer_not_empty <= '0';
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
err_read_pointer_write_pointer_empty <= '0';
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
err_read_pointer_write_pointer_not_full <= '0';
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
err_read_pointer_write_pointer_full <= '0';
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
err_read_pointer_increment <= '0';
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
err_read_pointer_not_increment <= '0';
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_write_en <= '0';
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en <= '0';
if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en1 <= '0';
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en2 <= '0';
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
end if;
end process;
-- Checked! (Not sure yet if actually needed!)
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
err_read_en_mismatch <= '0';
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
err_read_en_mismatch1 <= '0';
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
end if;
end process;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Newly added checkers for FIFO with packet drop and fault classifier support --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Checkers for fake credit generation logic in FIFO
---------------------------------------------------------------------------------
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked!
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked! (Behrad: Is it OK to see fake credit counter like this ?? Because being negative, can also be understood as positive,
-- depending on how the data is evaluated (signed or unsigned), or may I am wrong.)
process (fake_credit, read_en_out, credit_out)
begin
err_fake_credit_read_en_credit_out <= '0';
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
end if;
end process;
-- Checked! (Behrad: Credit_out here in Checker is actually credit_in in FIFO. Well, FIFO generated credit_out.
-- But here, credit_in would mean the registered value of credit_out I guess. )
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Checkers related to the packet dropping FSM of FIFO
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Idle state
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, fault_out, valid_in, state_in)
begin
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
err_state_out_Idle_not_fault_out_not_fault_info_in <= '0';
if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then
err_state_out_Idle_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
err_state_out_Idle_fault_out_fake_credit <= '0';
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, fault_out, state_in)
begin
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
err_state_out_Idle_fault_out_fault_info_in <= '0';
if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then
err_state_out_Idle_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
end if;
end process;
process (state_out, write_fake_flit)
begin
err_state_out_Idle_not_write_fake_flit <= '0';
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
-- health_info only gets updated when the FSM is in "Body" state (flit type is Body)
process (state_out, health_info)
begin
err_state_out_Idle_not_health_info <= '0';
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, state_in)
begin
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, fake_credit)
begin
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Body_flit state
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, health_info)
begin
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, health_info)
begin
err_state_out_Body_flit_valid_in_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, state_in)
begin
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, fake_credit)
begin
err_state_out_Body_flit_not_fake_credit <= '0';
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- valid_in = '1' and fault_out = '0'
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
process (state_out, valid_in, state_in)
begin
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
end if;
end process;
process (state_out, write_fake_flit)
begin
err_state_out_Tail_flit_not_write_fake_flit <= '0';
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in)
begin
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in)
begin
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
end if;
end process;
process (fault_info, fault_info_out)
begin
err_fault_info_fault_info_out_equal <= '0';
if (fault_info /= fault_info_out) then
err_fault_info_fault_info_out_equal <= '1';
end if;
end process;
process (state_out, valid_in, state_in)
begin
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0';
if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_info_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_info_in /= '1') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fault_info_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001") and fault_info_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '1';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic; -- Behrad: In FIFO, this is actually an internal signal "named as credit_in", which I guess should keep the previous value of credit_out.
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
begin
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
err_empty_full <= '0';
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
end if;
end process;
-- Checked!
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
err_empty_read_en <= '0';
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
err_full_write_en <= '0';
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
err_read_pointer_in_onehot <= '0';
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
err_write_pointer_in_onehot <= '0';
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
err_write_en_write_pointer <= '0';
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
end if;
end process;
process (write_en_out, write_pointer_in, write_pointer)
begin
err_not_write_en_write_pointer <= '0';
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
err_read_pointer_write_pointer_not_empty <= '0';
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
err_read_pointer_write_pointer_empty <= '0';
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
err_read_pointer_write_pointer_not_full <= '0';
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
err_read_pointer_write_pointer_full <= '0';
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
err_read_pointer_increment <= '0';
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
err_read_pointer_not_increment <= '0';
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_write_en <= '0';
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en <= '0';
if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en1 <= '0';
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
err_not_write_en2 <= '0';
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
end if;
end process;
-- Checked! (Not sure yet if actually needed!)
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
err_read_en_mismatch <= '0';
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
err_read_en_mismatch1 <= '0';
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
end if;
end process;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Newly added checkers for FIFO with packet drop and fault classifier support --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Checkers for fake credit generation logic in FIFO
---------------------------------------------------------------------------------
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked!
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
end if;
end process;
-- Checked! (Behrad: Is it OK to see fake credit counter like this ?? Because being negative, can also be understood as positive,
-- depending on how the data is evaluated (signed or unsigned), or may I am wrong.)
process (fake_credit, read_en_out, credit_out)
begin
err_fake_credit_read_en_credit_out <= '0';
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
end if;
end process;
-- Checked! (Behrad: Credit_out here in Checker is actually credit_in in FIFO. Well, FIFO generated credit_out.
-- But here, credit_in would mean the registered value of credit_out I guess. )
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Checkers related to the packet dropping FSM of FIFO
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Idle state
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, fault_out, valid_in, state_in)
begin
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
err_state_out_Idle_not_fault_out_not_fault_info_in <= '0';
if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then
err_state_out_Idle_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
err_state_out_Idle_fault_out_fake_credit <= '0';
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, fault_out, state_in)
begin
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
err_state_out_Idle_fault_out_fault_info_in <= '0';
if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then
err_state_out_Idle_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
end if;
end process;
process (state_out, write_fake_flit)
begin
err_state_out_Idle_not_write_fake_flit <= '0';
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
-- health_info only gets updated when the FSM is in "Body" state (flit type is Body)
process (state_out, health_info)
begin
err_state_out_Idle_not_health_info <= '0';
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, state_in)
begin
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, fake_credit)
begin
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Body_flit state
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, health_info)
begin
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, health_info)
begin
err_state_out_Body_flit_valid_in_not_health_info <= '0';
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, state_in)
begin
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, fake_credit)
begin
err_state_out_Body_flit_not_fake_credit <= '0';
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- valid_in = '1' and fault_out = '0'
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
end if;
end process;
process (state_out, valid_in, state_in)
begin
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0';
if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
end if;
end process;
process (state_out, write_fake_flit)
begin
err_state_out_Tail_flit_not_write_fake_flit <= '0';
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
end if;
end process;
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in)
begin
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in)
begin
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
end if;
end process;
process (fault_info, fault_info_out)
begin
err_fault_info_fault_info_out_equal <= '0';
if (fault_info /= fault_info_out) then
err_fault_info_fault_info_out_equal <= '1';
end if;
end process;
process (state_out, valid_in, state_in)
begin
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0';
if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0';
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_info_in)
begin
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_info_in /= '1') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '1';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fault_info_in)
begin
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '0';
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001") and fault_info_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '1';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
entity test3 is
port (led: out std_logic_vector (7 downto 0);
rst : std_logic;
clk : std_logic);
end test3;
architecture synth of test3 is
signal int : std_logic_vector(1 downto 0);
begin
-- led(7) <= '0';
-- led(6) <= '1';
-- led(5) <= '0';
-- led(3 downto 0) <= x"9";
process (clk) is
begin
if rising_edge (clk) then
if rst = '1' then
int(1) <= '0';
else
int(1) <= not int(1);
end if;
end if;
end process;
led(5) <= int (1);
end synth;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file mips_vram.vhd when simulating
-- the core, mips_vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY mips_vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mips_vram;
ARCHITECTURE mips_vram_a OF mips_vram IS
-- synthesis translate_off
COMPONENT wrapped_mips_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_mips_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mips_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END mips_vram_a;
|
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`protect end_protected
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_8 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_8 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 8, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_8 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_8 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 8, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_8 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_8 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 8, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_8 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_8 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 8, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_8 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_8 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 8, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- 7-segment display driver. It displays a 4-bit number on 7-segments
-- This is created as an entity so that it can be reused many times easily
--
entity SevenSegment is port (
dataIn : in std_logic_vector(3 downto 0); -- The 4 bit data to be displayed
blanking : in std_logic; -- This bit turns off all segments
segmentsOut : out std_logic_vector(6 downto 0) -- 7-bit outputs to a 7-segment
);
end SevenSegment;
architecture Behavioral of SevenSegment is
--
-- The following statements convert a 4-bit input, called dataIn to a pattern of 7 bits
-- The segment turns on when it is '0' otherwise '1'
-- The blanking input is added to turns off the all segments
--
begin
with blanking & dataIn select -- gfedcba b3210 -- D7S
segmentsOut(6 downto 0) <= "1000000" when "00000", -- [0]
"1111001" when "00001", -- [1]
"0100100" when "00010", -- [2] +---- a ----+
"0110000" when "00011", -- [3] | |
"0011001" when "00100", -- [4] | |
"0010010" when "00101", -- [5] f b
"0000010" when "00110", -- [6] | |
"1111000" when "00111", -- [7] | |
"0000000" when "01000", -- [8] +---- g ----+
"0010000" when "01001", -- [9] | |
"0001000" when "01010", -- [A] | |
"0000011" when "01011", -- [b] e c
"1000110" when "01100", -- [c] | |
"0100001" when "01101", -- [d] | |
"0000110" when "01110", -- [E] +---- d ----+
"0001110" when "01111", -- [F]
"1111111" when others; -- [ ]
end Behavioral;
--------------------------------------------------------------------------------
-- Main entity
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Lab2 is port (
sw : in std_logic_vector(17 downto 0); -- 18 dip switches
ledr : out std_logic_vector(17 downto 0); -- 18 red LEDs
hex0, hex1, hex2, hex4, hex5, hex6, hex7 : out std_logic_vector( 6 downto 0) -- 7-segment displays
);
end Lab2;
architecture SimpleCircuit of Lab2 is
--
-- In order to use the "SevenSegment" entity, we should declare it first
--
component SevenSegment port (
dataIn : in std_logic_vector(3 downto 0);
blanking : in std_logic;
segmentsOut : out std_logic_vector(6 downto 0)
);
end component;
-- Create any signals, or temporary variables to be used
--
-- Note that there are two basic types and mixing them is difficult
-- unsigned is a signal which can be used to perform math operations such as +, -, *
-- std_logic_vector is a signal which can be used for logic operations such as OR, AND, NOT, XOR
--
signal A, B: std_logic_vector(7 downto 0);
signal R: std_logic_vector(11 downto 0);
signal S: std_logic_vector(1 downto 0);
-- Here the circuit begins
begin
-- intermediate signal assignments
A <= sw(7 downto 0); -- connect the lowest 8 switches to A
B <= sw(15 downto 8); -- connect the next 8 switches to B
S <= sw(17 downto 16); -- connect the highest 2 switches to S
-- multiplexer
with S select
R <= "0000"&A and "0000"&B when "00",
"0000"&A or "0000"&B when "01",
"0000"&A xor "0000"&B when "10",
std_logic_vector(unsigned("0000"&A)+unsigned("0000"&B)) when others;
-- signal is assigned to LED
ledr(8 downto 0) <= R(8 downto 0);
ledr(17 downto 16) <= S;
-- signal is sidplayed on seven-segment. '0' is concatenated with signal to make a 4-bit input
D7SH0: SevenSegment port map(R(3 downto 0), '0', hex0 ); -- R(3 downto 0) is diplayed on HEX0, blanking is disabled
D7SH1: SevenSegment port map(R(7 downto 4), '0', hex1 ); -- R(7 downto 4) is diplayed on HEX1, blanking is disabled
D7SH2: SevenSegment port map(R(11 downto 8), not R(8), hex2); -- R(11 downto 8) is displayed on HEX2, blanking is disabled when no carry
D7SH4: SevenSegment port map(A(3 downto 0), '0', hex4 ); -- A(3 downto 0) is diplayed on HEX4, blanking is disabled
D7SH5: SevenSegment port map(A(7 downto 4), '0', hex5 ); -- A(7 downto 4) is diplayed on HEX5, blanking is disabled
D7SH6: SevenSegment port map(B(3 downto 0), '0', hex6 ); -- B(3 downto 0) is diplayed on HEX6, blanking is disabled
D7SH7: SevenSegment port map(B(7 downto 4), '0', hex7 ); -- B(7 downto 4) is diplayed on HEX7, blanking is disabled
end SimpleCircuit;
|
-------------------------------------------------------------------------------------
-- FILE NAME : sip_lvds_reg.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_lvds_reg
-- architecture - arch_sip_lvds_reg
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- sip_lvds_reg
-- Notes: sip_lvds_reg
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_toggle_4lvds is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'cmdclk_in' of type 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ext_lvds' of type 'ext_lvds':
lvds_in_n : in std_logic_vector(1 downto 0);
lvds_in_p : in std_logic_vector(1 downto 0);
lvds_out_n : out std_logic_vector(1 downto 0);
lvds_out_p : out std_logic_vector(1 downto 0)
);
end entity sip_toggle_4lvds;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture behav of sip_toggle_4lvds is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
constant WIDTH : natural := 2;
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
signal lvds_in : std_logic_vector(1 downto 0);
signal lvds_out : std_logic_vector(1 downto 0);
signal reg0 : std_logic_vector(31 downto 0);
signal reg1 : std_logic_vector(31 downto 0);
signal reg2 : std_logic_vector(31 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
clk <= cmdclk_in_cmdclk;
-------------------------------------------------------------------------------------
-- Local reset: asynchronous assert, synchronous release
-------------------------------------------------------------------------------------
process(clk, rst_rstin(2))
begin
if rst_rstin(2) = '1' then
rst <= '1';
elsif rising_edge(clk) then
rst <= '0';
end if;
end process;
-------------------------------------------------------------------------------------
-- Command Registers
-------------------------------------------------------------------------------------
ip_block_ctrl_inst0:
entity work.ip_block_ctrl
generic map (
START_ADDR => private_start_addr_gen,
STOP_ADDR => private_stop_addr_gen
)
port map (
rst => rst,
clk_cmd => clk,
in_cmd_val => cmd_in_cmdin_val,
in_cmd => cmd_in_cmdin,
out_cmd_val => cmd_out_cmdout_val,
out_cmd => cmd_out_cmdout,
cmd_busy => open,
reg0 => reg0, --out
reg1 => open, --out
reg2 => reg2, -- in
reg3 => (others=>'0'), -- in
reg4 => (others=>'0'), -- in
reg5 => (others=>'0'), -- in
reg6 => (others=>'0'), -- in
mbx_in_reg => (others=>'0'),
mbx_in_val => '0'
);
--register map
process(clk)
begin
if rising_edge(clk) then
lvds_out(1 downto 0) <= reg0(1 downto 0); -- lvds output out of fpga pin
reg2(1 downto 0) <= lvds_in(1 downto 0); -- lvds input from fpga pin
end if;
end process;
-------------------------------------------------------------------------------------
-- LVDS PHY
-------------------------------------------------------------------------------------
generate_width:
for I in 0 to WIDTH-1 generate
obufds_output : OBUFDS
generic map (
IOSTANDARD => "DEFAULT", -- Specify the output I/O standard
SLEW => "SLOW" -- Specify the output slew rate
)
port map (
O => lvds_out_p(I), -- Diff_p output (connect directly to top-level port)
OB => lvds_out_n(I), -- Diff_n output (connect directly to top-level port)
I => lvds_out(I) -- Buffer input
);
ibufds_input : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => lvds_in(I), -- Buffer output
I => lvds_in_p(I), -- Diff_p buffer input (connect directly to top-level port)
IB => lvds_in_n(I) -- Diff_n buffer input (connect directly to top-level port)
);
end generate;
--***********************************************************************************
end architecture behav;
--***********************************************************************************
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_c7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.1-2018.3; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.0.2 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.0.1 add sys_conf_ibd_kw11p
-- 2017-06-24 914 1.0 Initial version (cloned from _n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 10;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 512kB memory blocks => 512*16 = 8192 MMU blocks
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural :=
(512*16) + (256*sys_conf_memctl_nblock) - 1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 8; -- 16kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := false; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_32bit is
port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (31 downto 0);
B: in STD_LOGIC_VECTOR (31 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)
);
end mux_32bit;
architecture Behavioral of mux_32bit is
begin
OUTPUT <= A when (SEL = '1') else B;
end Behavioral; |
variable x : integer range 5 to 10;
x := expr;
|
--------------------------------------------------------------------------------
--
-- UART Rx module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : clock of frequency G_CLOCK_FREQ
-- rst : active high synchronous reset
-- rx_in : Rx data line. Should be routed to the Tx pin of the external
-- UART device.
-- rx_data_out : 8 bit data received
-- rx_valid_out : 1 clk cycle pulse that indicates rx_data_out is valid.
--
-- Parameters:
-- G_BAUD_RATE : UART baud rate
-- G_CLOCK_FREQ : clk frequency. Can be fractional
--
-- Optimally, the baud rate must be an integer multiple of the clock
-- frequency. If not, it's rouded to the closest integer. In such cases
-- care must be taken to ensure sampling does not deviate significantly from
-- the center of the "eye"(ie. the middle of the received bit).
--
-- It is recommended to use sync flip-flops and a glitch filter before
-- connecting the rx input to the external UART device.
--
-- Arty FPGA board specific notes:
-- The FT2232H chip does not support baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud
-- and 11 Mbaud.
-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_rx is
generic(
G_BAUD_RATE : positive := 1250000;
G_CLOCK_FREQ : real := 100.0e6
);
port(
clk : in std_logic;
rst : in std_logic;
rx_in : in std_logic;
rx_data_out : out std_logic_vector(7 downto 0);
rx_valid_out : out std_logic
);
end entity uart_rx;
architecture rtl of uart_rx is
constant C_CLK_DIVISOR : positive := positive(round(G_CLOCK_FREQ / real(G_BAUD_RATE)));
constant C_DIV_WIDTH : positive := positive(ceil(log2(real(C_CLK_DIVISOR))));
type fsm_rx_type is (
RX_IDLE,
RX_DATA,
RX_STOP
);
signal fsm_rx_state : fsm_rx_type := RX_IDLE;
signal cnt_div_r : unsigned(C_DIV_WIDTH-1 downto 0) := (others=>'0');
signal cnt_data_r : unsigned(7 downto 0) := (others=>'0');
signal rx_data_sr : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_r : std_logic := '0';
signal rx_falling_edge_c : std_logic := '0';
signal rx_valid_r : std_logic := '0';
begin
rx_falling_edge_c <= (not rx_in) and rx_r;
-- A counter is used to synchronize the clock to the baud rate. The counter
-- is reset at the falling edge of the start bit. Sampling should be done
-- exactly halfway (ie. after C_CLK_DIVISOR/2 cycles)
proc_div_counter:
process(clk)
begin
if rising_edge(clk) then
rx_r <= rx_in;
-- reset counter
if (rx_falling_edge_c = '1') and (fsm_rx_state = RX_IDLE) then
cnt_div_r <= (others=>'0');
else
if (cnt_div_r = C_CLK_DIVISOR - 1) then
cnt_div_r <= (others=>'0');
else
cnt_div_r <= cnt_div_r + 1;
end if;
end if;
end if;
end process;
proc_fsm_rx:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
rx_valid_r <= '0';
fsm_rx_state <= RX_IDLE;
else
rx_valid_r <= '0';
case fsm_rx_state is
-- Wait for the start bit
when RX_IDLE =>
-- We're checking rx_r and not rx_in
-- just in case the counter happens to be halway at the falling edge,
-- causing a false trigger
cnt_data_r <= (others=>'0');
if (rx_r = '0') and (cnt_div_r = C_CLK_DIVISOR/2 - 1) then
fsm_rx_state <= RX_DATA;
end if;
-- Sample the data bits and shift them into a register
when RX_DATA =>
if (cnt_div_r = C_CLK_DIVISOR/2 - 1) then
rx_data_sr <= rx_r & rx_data_sr(7 downto 1);
if (cnt_data_r = 7) then
fsm_rx_state <= RX_STOP;
else
cnt_data_r <= cnt_data_r + 1;
end if;
end if;
-- Check for the stop bit
when RX_STOP =>
if (cnt_div_r = C_CLK_DIVISOR/2 - 1) then
-- raise the valid flag only if the stop bit is 1
if (rx_r = '1') then
rx_valid_r <= '1';
end if;
fsm_rx_state <= RX_IDLE;
end if;
when others =>
fsm_rx_state <= RX_IDLE;
end case;
end if;
end if;
end process;
rx_data_out <= rx_data_sr;
rx_valid_out <= rx_valid_r;
end architecture; |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_td_mode is
port(
ctrl : in vl_logic_vector(8 downto 0);
td_mode : out vl_logic_vector(3 downto 0)
);
end usb_system_cpu_nios2_oci_td_mode;
|
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
|
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2;
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when others => r <= shift;
end case;
end process;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(4 downto 0);
left <= '1' when alu_op(0) = '1' else '0';
logical <= '1' when alu_op(2) = '0' else '0';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
result <= r;
end arch_alu;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2;
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when others => r <= shift;
end case;
end process;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(4 downto 0);
left <= '1' when alu_op(0) = '1' else '0';
logical <= '1' when alu_op(2) = '0' else '0';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
result <= r;
end arch_alu;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc630.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:47 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00630ent IS
END c03s04b01x00p01n01i00630ent;
ARCHITECTURE c03s04b01x00p01n01i00630arch OF c03s04b01x00p01n01i00630ent IS
type four_value is ('Z','0','1','X');
type four_value_map is array (four_value) of boolean;
type four_value_map_file is file of four_value_map;
constant C38 : four_value_map := (true,true,true,true);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_map_file open read_mode is "iofile.37";
variable v : four_value_map;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00630"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00630 - File reading operation (four_value_map file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00630arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc630.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:47 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00630ent IS
END c03s04b01x00p01n01i00630ent;
ARCHITECTURE c03s04b01x00p01n01i00630arch OF c03s04b01x00p01n01i00630ent IS
type four_value is ('Z','0','1','X');
type four_value_map is array (four_value) of boolean;
type four_value_map_file is file of four_value_map;
constant C38 : four_value_map := (true,true,true,true);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_map_file open read_mode is "iofile.37";
variable v : four_value_map;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00630"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00630 - File reading operation (four_value_map file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00630arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc630.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:47 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00630ent IS
END c03s04b01x00p01n01i00630ent;
ARCHITECTURE c03s04b01x00p01n01i00630arch OF c03s04b01x00p01n01i00630ent IS
type four_value is ('Z','0','1','X');
type four_value_map is array (four_value) of boolean;
type four_value_map_file is file of four_value_map;
constant C38 : four_value_map := (true,true,true,true);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_map_file open read_mode is "iofile.37";
variable v : four_value_map;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00630"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00630 - File reading operation (four_value_map file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00630arch;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
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