content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_buffer_addressable - Structural
-- Description: Outputs counterclockwise rotation over time
------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_buffer_addressable - Structural
-- Description: Outputs counterclockwise rotation over time
------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10.02.2017 11:21:03
-- Design Name:
-- Module Name: ClockManager - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
------------------------------------------------... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _ ... |
library verilog;
use verilog.vl_types.all;
entity usb_system_keycode is
port(
address : in vl_logic_vector(1 downto 0);
chipselect : in vl_logic;
clk : in vl_logic;
reset_n : in vl_logic;
write_n : in vl_logic;
... |
-------------------------------------------------------------------
--! @file
--! @author Stephan Doll
--! @brief Package for VHDL text output, from Stephan Doll's VHDL verification course.
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.al... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq2_code2_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end qq2_code2_table;
architecture augh of qq2_code2_table is
-- Embedded RAM
... |
--------------------------------------------------------------------------------
-- Programmable Interval Timer --
--------------------------------------------------------------------------------
-- Simplest implementation of a programmable interval timer. The timer is ... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00086.P1: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P2: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00086.P3: Multi transport transactions occurred on signal asg with slice n... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_top_ppro_sdram is
port (
CLK: in std_logic;
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
DRAM_ADDR : OUT STD_... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is ... |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is ... |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is ... |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is ... |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is ... |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is ... |
-------------------------------------------------------------------------------
-- Title : test1
-- Project :
-------------------------------------------------------------------------------
-- File : test1.vhd
-- Author : <kristoffer.nordstrom@HELVNB0100>
-- Company :
-- Created : 201... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 02/11/2018 03:24:43 PM
-- Module Name: sext - Behavioral
-- Description: Sign extender for immediate values
--
-- Additional Comments:
--
--------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic... |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity pid is
generic
(
-- Coefficients are shifted left is positive and right if negative
-- Proportional coefficient
P_SHIFT_N : integer;
-- Integral coefficien... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- S... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
library verilog;
use verilog.vl_types.all;
entity matching is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iFREE_DEFAULT : in vl_logic;
iFREE_RESTART : in vl_logic;
iCOMMIT_OFFSET : in vl_logic_vector(2 downto 0);
oLOOPB... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY kbBuffer IS
PORT(
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END kbBuffer;
... |
-- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v14.1%
-- GENERATION: XML
-- ddr3controller.vhd
-- Generated using ACDS version 14.1 186 at 2015.02.11.15:25:43
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr3controller is
port (
pll_ref_clk : in std_logi... |
-------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
library verilog;
use verilog.vl_types.all;
entity matchfilter is
port(
clk : in vl_logic;
reset_n : in vl_logic;
ast_sink_data : in vl_logic_vector(14 downto 0);
ast_sink_valid : in vl_logic;
ast_source_ready: in vl_logic;
as... |
library verilog;
use verilog.vl_types.all;
entity matchfilter is
port(
clk : in vl_logic;
reset_n : in vl_logic;
ast_sink_data : in vl_logic_vector(14 downto 0);
ast_sink_valid : in vl_logic;
ast_source_ready: in vl_logic;
as... |
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE work.GlobalDefines.ALL;
entity <name> is
port(
);
end <name>;
architecture bhv of <name> is
component <bla> is
port(
);
end component;
begin
end bhv;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myXor2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end myXor2;
architecture behavorial of myXor2 is
-- declare components
component myNand2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
compo... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans;
architecture a_aff_trans of aff_trans is
begin
-- Tranformation Process
b_out(0) <= no... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans;
architecture a_aff_trans of aff_trans is
begin
-- Tranformation Process
b_out(0) <= no... |
-- This is the top level of the ethernet block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ethernet_package.all;
entity ethernet_udp is
port (
--- External ports
CLK125 : in STD_LOGIC;
reset_n : in std_logic;
PHY_RESET_L : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myvga is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_D... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
entity bug is
end entity;
architecture test of bug is
constant engnum : integer:=8;
subtype engrange is integer range 0 to engnum-1;
type bit_array is array(engrange) of bit;
type byte_array is array(engrange) of bit_vector(7 downto 0);
type mode_t is (RDBMG, C2ENC, C2DEC, C1DEC, WRBMG);
type ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_coder is
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
d : in std_logic;
x : out std_logic;
y : out std_logic
);
end conv_coder;
architecture rtl of conv_coder is
signal delay : std_logic_vector(0 t... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N... |
library ieee;
use ieee.std_logic_1164.all;
entity test3 is
port (led: out std_logic_vector (7 downto 0);
rst : std_logic;
clk : std_logic);
end test3;
architecture synth of test3 is
signal int : std_logic_vector(1 downto 0);
begin
-- led(7) <= '0';
-- led(6) <= '1';
-- led(5) <= '0';
-- led(3 ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- 7-segment display driver. It displays a 4-bit number on 7-segments
-- This is created as an entity so that it can be reused many times easily
--
entity SevenSegment is port (
dataIn : in std_logic_vector(3 downto 0); -- The 4 ... |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_lvds_reg.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_lvds_reg
-- architecture - arch_sip_lvds_reg
--
-- LANGUAGE... |
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_32bit is
port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (31 downto 0);
B: in STD_LOGIC_VECTOR (31 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)
);
end mux_32bit;
architecture Behavioral of mux_32bit is
... |
variable x : integer range 5 to 10;
x := expr;
|
--------------------------------------------------------------------------------
--
-- UART Rx module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : clock of frequency G... |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_td_mode is
port(
ctrl : in vl_logic_vector(8 downto 0);
td_mode : out vl_logic_vector(3 downto 0)
);
end usb_system_cpu_nios2_oci_td_mode;
|
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
|
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
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